This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
577 lines
66 KiB
Plaintext
577 lines
66 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000016 # Number of seconds simulated
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sim_ticks 16282500 # Number of ticks simulated
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final_tick 16282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 46082 # Simulator instruction rate (inst/s)
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host_op_rate 46072 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 140796560 # Simulator tick rate (ticks/s)
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host_mem_usage 222960 # Number of bytes of host memory used
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host_seconds 0.12 # Real time elapsed on the host
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sim_insts 5327 # Number of instructions simulated
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sim_ops 5327 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory
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system.physmem.bytes_read::total 27072 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 18496 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 18496 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 423 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1135943498 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 526700445 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1662643943 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1135943498 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1135943498 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1135943498 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 526700445 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1662643943 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 423 # Total number of read requests seen
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system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 27072 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 27072 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 35 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 24 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 10 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 15 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 2 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 9 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 28 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 7 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 5 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 40 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 59 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 62 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 25 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 16 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 54 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 16231000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 423 # Categorize read packet sizes
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
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system.physmem.readPktSize::8 0 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # categorize write packet sizes
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system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.writePktSize::2 0 # categorize write packet sizes
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system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::5 0 # categorize write packet sizes
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system.physmem.writePktSize::6 0 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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system.physmem.rdQLenPdf::0 254 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.totQLat 2301921 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 11301921 # Sum of mem lat for all requests
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system.physmem.totBusLat 1692000 # Total cycles spent in databus access
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system.physmem.totBankLat 7308000 # Total cycles spent in bank access
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system.physmem.avgQLat 5441.89 # Average queueing delay per request
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system.physmem.avgBankLat 17276.60 # Average bank access latency per request
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system.physmem.avgBusLat 4000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 26718.49 # Average memory access latency
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system.physmem.avgRdBW 1662.64 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 1662.64 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 10.39 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.69 # Average read queue length over time
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system.physmem.avgWrQLen 0.00 # Average write queue length over time
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system.physmem.readRowHits 336 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 79.43 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 38371.16 # Average gap between requests
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system.cpu.workload.num_syscalls 11 # Number of system calls
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system.cpu.numCycles 32566 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.branch_predictor.lookups 1630 # Number of BP lookups
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system.cpu.branch_predictor.condPredicted 1034 # Number of conditional branches predicted
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system.cpu.branch_predictor.condIncorrect 901 # Number of conditional branches incorrect
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system.cpu.branch_predictor.BTBLookups 1165 # Number of BTB lookups
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system.cpu.branch_predictor.BTBHits 436 # Number of BTB hits
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system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target.
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system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions.
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system.cpu.branch_predictor.BTBHitPct 37.424893 # BTB Hit Percentage
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system.cpu.branch_predictor.predictedTaken 503 # Number of Branches Predicted As Taken (True).
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system.cpu.branch_predictor.predictedNotTaken 1127 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileReads 5631 # Number of Reads from Int. Register File
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system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File
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system.cpu.regfile_manager.intRegFileAccesses 9619 # Total Accesses (Read+Write) to the Int. Register File
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system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File
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system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
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system.cpu.regfile_manager.regForwards 1675 # Number of Registers Read Through Forwarding Logic
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system.cpu.agen_unit.agens 1483 # Number of Address Generations
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system.cpu.execution_unit.predictedTakenIncorrect 334 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.execution_unit.predictedNotTakenIncorrect 504 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.execution_unit.mispredicted 838 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.predicted 277 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.mispredictPct 75.156951 # Percentage of Incorrect Branches Predicts
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system.cpu.execution_unit.executions 3966 # Number of Instructions Executed.
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system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
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system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
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system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.threadCycles 9640 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
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system.cpu.timesIdled 478 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu.idleCycles 26364 # Number of cycles cpu's stages were not processed
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system.cpu.runCycles 6202 # Number of cycles cpu stages are processed.
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system.cpu.activity 19.044402 # Percentage of cycles cpu is active
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system.cpu.comLoads 715 # Number of Load instructions committed
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system.cpu.comStores 673 # Number of Store instructions committed
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system.cpu.comBranches 1115 # Number of Branches instructions committed
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system.cpu.comNops 173 # Number of Nop instructions committed
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system.cpu.comNonSpec 106 # Number of Non-Speculative instructions committed
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system.cpu.comInts 2526 # Number of Integer instructions committed
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system.cpu.comFloats 0 # Number of Floating Point instructions committed
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system.cpu.committedInsts 5327 # Number of Instructions committed (Per-Thread)
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system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread)
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system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
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system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total)
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system.cpu.cpi 6.113385 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.smt_cpi nan # CPI: Total SMT-CPI
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system.cpu.cpi_total 6.113385 # CPI: Total CPI of All Threads
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system.cpu.ipc 0.163576 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.smt_ipc nan # IPC: Total SMT-IPC
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system.cpu.ipc_total 0.163576 # IPC: Total IPC of All Threads
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system.cpu.stage0.idleCycles 28007 # Number of cycles 0 instructions are processed.
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system.cpu.stage0.runCycles 4559 # Number of cycles 1+ instructions are processed.
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system.cpu.stage0.utilization 13.999263 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.idleCycles 29377 # Number of cycles 0 instructions are processed.
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system.cpu.stage1.runCycles 3189 # Number of cycles 1+ instructions are processed.
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system.cpu.stage1.utilization 9.792422 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage2.idleCycles 29532 # Number of cycles 0 instructions are processed.
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system.cpu.stage2.runCycles 3034 # Number of cycles 1+ instructions are processed.
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system.cpu.stage2.utilization 9.316465 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage3.idleCycles 31591 # Number of cycles 0 instructions are processed.
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system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed.
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system.cpu.stage3.utilization 2.993920 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage4.idleCycles 29408 # Number of cycles 0 instructions are processed.
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system.cpu.stage4.runCycles 3158 # Number of cycles 1+ instructions are processed.
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system.cpu.stage4.utilization 9.697230 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.tagsinuse 143.411463 # Cycle average of tags in use
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system.cpu.icache.total_refs 814 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 2.797251 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 143.411463 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.070025 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.070025 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 814 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 814 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 814 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 814 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 814 # number of overall hits
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system.cpu.icache.overall_hits::total 814 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 364 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 18418500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 18418500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 18418500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 18418500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 18418500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 18418500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 1178 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 1178 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 1178 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 1178 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 1178 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 1178 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.308998 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.308998 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.308998 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.308998 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.308998 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.308998 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50600.274725 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 50600.274725 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 50600.274725 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 50600.274725 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 50600.274725 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 50600.274725 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15194000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 15194000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15194000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 15194000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15194000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 15194000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.247029 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.247029 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.247029 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52213.058419 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52213.058419 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52213.058419 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 52213.058419 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52213.058419 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 52213.058419 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
system.cpu.dcache.tagsinuse 85.214129 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 914 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 6.770370 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 85.214129 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.020804 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.020804 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 260 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 914 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 914 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 914 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 914 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 413 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 413 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 474 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3347500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 3347500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19185000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 19185000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 22532500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 22532500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 22532500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 22532500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085315 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.085315 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.613670 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.613670 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54877.049180 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 54877.049180 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46452.784504 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 46452.784504 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 47536.919831 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 47536.919831 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 47536.919831 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 47536.919831 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 405 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.656250 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 332 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 332 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2939000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2939000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4153500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4153500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7092500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 7092500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7092500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 7092500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54425.925926 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54425.925926 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51277.777778 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51277.777778 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52537.037037 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52537.037037 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52537.037037 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52537.037037 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 169.991473 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 142.874602 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 27.116871 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.004360 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.000828 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.005188 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 3 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 289 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 342 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 289 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 423 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 423 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14875500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2872500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 17748000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4070000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 4070000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 14875500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 6942500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 21818000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 14875500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 6942500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 21818000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 426 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 426 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993127 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981481 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.991304 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993127 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.992958 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51472.318339 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54198.113208 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 51894.736842 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50246.913580 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50246.913580 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51472.318339 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51809.701493 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 51579.196217 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51472.318339 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51809.701493 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 51579.196217 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 289 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 342 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 289 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 423 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11235436 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2207572 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13443008 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3066568 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3066568 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11235436 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5274140 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 16509576 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11235436 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5274140 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 16509576 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38876.941176 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41652.301887 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39307.040936 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37858.864198 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37858.864198 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38876.941176 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39359.253731 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39029.730496 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38876.941176 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39359.253731 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39029.730496 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|