10b70d5452
This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
842 lines
96 KiB
Text
842 lines
96 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.135739 # Number of seconds simulated
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sim_ticks 135738546500 # Number of ticks simulated
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final_tick 135738546500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 149707 # Simulator instruction rate (inst/s)
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host_op_rate 149707 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 35931284 # Simulator tick rate (ticks/s)
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host_mem_usage 219152 # Number of bytes of host memory used
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host_seconds 3777.73 # Real time elapsed on the host
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sim_insts 565552443 # Number of instructions simulated
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sim_ops 565552443 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 1636160 # Number of bytes read from this memory
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system.physmem.bytes_read::total 1697792 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 67072 # Number of bytes written to this memory
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system.physmem.bytes_written::total 67072 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 25565 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 26528 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 1048 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1048 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 454049 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 12053761 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 12507810 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 454049 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 454049 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 494126 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 494126 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 494126 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 454049 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 12053761 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 13001937 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 26528 # Total number of read requests seen
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system.physmem.writeReqs 1048 # Total number of write requests seen
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system.physmem.cpureqs 27576 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 1697792 # Total number of bytes read from memory
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system.physmem.bytesWritten 67072 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 1697792 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 67072 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 1724 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 1737 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 1613 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 1636 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 1721 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 1640 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 1683 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 1681 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 1569 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 1630 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 1617 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 1555 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 1665 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 1653 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 1711 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 1678 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 66 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 78 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 55 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 60 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 75 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 62 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 78 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 83 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 54 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 56 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 59 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 48 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 63 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 62 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 80 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 135738512500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 26528 # Categorize read packet sizes
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
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system.physmem.readPktSize::8 0 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # categorize write packet sizes
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system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.writePktSize::2 0 # categorize write packet sizes
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system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::5 0 # categorize write packet sizes
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system.physmem.writePktSize::6 1048 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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system.physmem.rdQLenPdf::0 10104 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 10480 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 4915 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 1000 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 42 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 46 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 46 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 46 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 46 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 46 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 46 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 46 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 46 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 46 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 46 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 46 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 45 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 45 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 45 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 45 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 45 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 45 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 45 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 45 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 45 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 45 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.totQLat 656768415 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 1272742415 # Sum of mem lat for all requests
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system.physmem.totBusLat 106052000 # Total cycles spent in databus access
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system.physmem.totBankLat 509922000 # Total cycles spent in bank access
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system.physmem.avgQLat 24771.56 # Average queueing delay per request
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system.physmem.avgBankLat 19232.90 # Average bank access latency per request
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system.physmem.avgBusLat 4000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 48004.47 # Average memory access latency
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system.physmem.avgRdBW 12.51 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.49 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 12.51 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.49 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 0.08 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.01 # Average read queue length over time
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system.physmem.avgWrQLen 10.03 # Average write queue length over time
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system.physmem.readRowHits 18053 # Number of row buffer hits during reads
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system.physmem.writeRowHits 56 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 68.09 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 5.34 # Row buffer hit rate for writes
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system.physmem.avgGap 4922342.34 # Average gap between requests
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 123922794 # DTB read hits
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system.cpu.dtb.read_misses 28366 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 123951160 # DTB read accesses
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system.cpu.dtb.write_hits 40833980 # DTB write hits
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system.cpu.dtb.write_misses 25612 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 40859592 # DTB write accesses
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system.cpu.dtb.data_hits 164756774 # DTB hits
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system.cpu.dtb.data_misses 53978 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 164810752 # DTB accesses
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system.cpu.itb.fetch_hits 66580671 # ITB hits
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system.cpu.itb.fetch_misses 40 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 66580711 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 17 # Number of system calls
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system.cpu.numCycles 271477094 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 78553522 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 72909571 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 3050106 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 42863354 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 41672348 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 1629524 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 245 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 68542455 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 711581178 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 78553522 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 43301872 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 119313775 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 13045820 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 73380337 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 247 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 1305 # Number of stall cycles due to pending traps
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system.cpu.fetch.IcacheWaitRetryStallCycles 7 # Number of stall cycles due to full MSHR
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system.cpu.fetch.CacheLines 66580671 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 946763 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 271202747 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.623798 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.454049 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 151888972 56.01% 56.01% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 10373570 3.83% 59.83% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 11841110 4.37% 64.20% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 10622549 3.92% 68.11% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 7004922 2.58% 70.70% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 2671761 0.99% 71.68% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 3503178 1.29% 72.97% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 3113300 1.15% 74.12% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 70183385 25.88% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 271202747 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.289356 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.621146 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 86023061 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 57429003 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 104152322 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 13634796 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 9963565 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 3909126 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 1128 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 702760367 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 4141 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 9963565 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 94304341 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 12784998 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 1531 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 104174044 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 49974268 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 690768624 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 416 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 38037873 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 5669894 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RenamedOperands 527681051 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 907529781 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 907526811 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 2970 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 63826162 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 100 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 107 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 112138467 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 129142032 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 42466663 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 14842304 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 10368291 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 626932339 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 92 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 608621790 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 344229 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 60678365 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 33855512 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 75 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 271202747 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 2.244158 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.828491 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 55518105 20.47% 20.47% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 55264401 20.38% 40.85% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 53914091 19.88% 60.73% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 37013789 13.65% 74.38% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 31720099 11.70% 86.07% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 23689667 8.74% 94.81% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 10003906 3.69% 98.50% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 3493839 1.29% 99.78% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 584850 0.22% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 271202747 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 2803923 71.85% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 36 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.85% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 717323 18.38% 90.23% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 381401 9.77% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 441148473 72.48% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 7331 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 29 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 126212456 20.74% 93.22% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 41253487 6.78% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 608621790 # Type of FU issued
|
|
system.cpu.iq.rate 2.241890 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 3902683 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.006412 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 1492689315 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 687613743 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 598990581 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 3924 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 2505 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 1722 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 612522503 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 1970 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 12211500 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 14627990 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 32965 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 5519 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 3015342 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 6777 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 53391 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 9963565 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 1456092 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 187737 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 670933978 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 1716868 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 129142032 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 42466663 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 92 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 140012 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 7404 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 5519 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 1345446 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 2210203 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 3555649 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 602801961 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 123951309 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 5819829 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 44001547 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 164826908 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 67037045 # Number of branches executed
|
|
system.cpu.iew.exec_stores 40875599 # Number of stores executed
|
|
system.cpu.iew.exec_rate 2.220452 # Inst execution rate
|
|
system.cpu.iew.wb_sent 600240253 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 598992303 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 417488059 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 532706701 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 2.206419 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.783711 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 68955725 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 3049050 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 261239182 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 2.303854 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.691353 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 82351408 31.52% 31.52% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 72672063 27.82% 59.34% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 25867656 9.90% 69.24% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 8932880 3.42% 72.66% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 10297113 3.94% 76.60% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 20861196 7.99% 84.59% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 6530231 2.50% 87.09% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 3837950 1.47% 88.56% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 29888685 11.44% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 261239182 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 601856963 # Number of instructions committed
|
|
system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 153965363 # Number of memory references committed
|
|
system.cpu.commit.loads 114514042 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 62547159 # Number of branches committed
|
|
system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 563954763 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 1197610 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 29888685 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 902098796 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 1351611788 # The number of ROB writes
|
|
system.cpu.timesIdled 34221 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 274347 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 565552443 # Number of Instructions Simulated
|
|
system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.480021 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.480021 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 2.083242 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 2.083242 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 848885274 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 492863541 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 396 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 49 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.icache.replacements 43 # number of replacements
|
|
system.cpu.icache.tagsinuse 832.109405 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 66579220 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 984 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 67661.808943 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 832.109405 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.406303 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.406303 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 66579220 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 66579220 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 66579220 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 66579220 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 66579220 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 66579220 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1449 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1449 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1449 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1449 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1449 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1449 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 74643000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 74643000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 74643000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 74643000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 74643000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 74643000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 66580669 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 66580669 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 66580669 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 66580669 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 66580669 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 66580669 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51513.457557 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 51513.457557 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 51513.457557 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 51513.457557 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 51513.457557 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 51513.457557 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 293 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 73.250000 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 465 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 465 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 465 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 465 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 465 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 465 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 984 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 984 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 984 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 984 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 984 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 984 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52158000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 52158000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52158000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 52158000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52158000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 52158000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53006.097561 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53006.097561 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53006.097561 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 53006.097561 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53006.097561 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 53006.097561 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 460800 # number of replacements
|
|
system.cpu.dcache.tagsinuse 4090.940281 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 148282429 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 464896 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 318.958281 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 305241000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 4090.940281 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.998765 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.998765 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 110633165 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 110633165 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 37649215 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 37649215 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 49 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 49 # number of LoadLockedReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 148282380 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 148282380 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 148282380 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 148282380 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1026018 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1026018 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1802106 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1802106 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 2828124 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 2828124 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 2828124 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 2828124 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 15421055000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 15421055000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 25889922656 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 25889922656 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 28500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 28500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 41310977656 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 41310977656 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 41310977656 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 41310977656 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 111659183 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 111659183 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 52 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 52 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 151110504 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 151110504 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 151110504 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 151110504 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009189 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.009189 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045679 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.045679 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057692 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057692 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.018716 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.018716 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.018716 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.018716 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.004347 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.004347 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14366.481581 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 14366.481581 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9500 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9500 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14607.201684 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 14607.201684 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14607.201684 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 14607.201684 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 279576 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 531 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 17250 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.207304 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 44.250000 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 445038 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 445038 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 815637 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 815637 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1547591 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 1547591 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 2363228 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 2363228 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 2363228 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 2363228 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210381 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 210381 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254515 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 254515 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 464896 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 464896 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 464896 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 464896 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2700521500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2700521500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4051961986 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4051961986 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6752483486 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 6752483486 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6752483486 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 6752483486 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001884 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001884 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006451 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006451 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003077 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.003077 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003077 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.003077 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12836.337407 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12836.337407 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15920.326841 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15920.326841 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14524.718402 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14524.718402 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14524.718402 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14524.718402 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 1080 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 22929.630995 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 547178 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 23523 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 23.261404 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 21483.752454 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 824.475298 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 621.403243 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.655632 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.025161 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.018964 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.699757 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 206090 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 206111 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 445038 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 445038 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 233241 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 233241 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 21 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 439331 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 439352 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 21 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 439331 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 439352 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 963 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 4290 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 5253 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 21275 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 21275 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 963 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 25565 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 26528 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 963 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 25565 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 26528 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50946500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 423158500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 474105000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1457229500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 1457229500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 50946500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 1880388000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 1931334500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 50946500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 1880388000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 1931334500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 984 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 210380 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 211364 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 445038 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 445038 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254516 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 254516 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 984 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 464896 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 465880 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 984 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 464896 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 465880 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.978659 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020392 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.024853 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083590 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.083590 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.978659 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.054991 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.056942 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.978659 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.054991 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.056942 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52903.946002 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 98638.344988 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 90254.140491 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68494.923619 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68494.923619 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52903.946002 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73553.217289 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 72803.622587 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52903.946002 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73553.217289 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 72803.622587 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 1049 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 1049 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 963 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4290 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 5253 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21275 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 21275 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 25565 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 26528 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 25565 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 26528 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38838509 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 367821283 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 406659792 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1190995676 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1190995676 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38838509 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1558816959 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 1597655468 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38838509 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1558816959 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 1597655468 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.978659 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020392 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024853 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083590 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083590 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.978659 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054991 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.056942 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.978659 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054991 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.056942 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40330.746625 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 85739.226807 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77414.770988 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55980.995347 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55980.995347 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40330.746625 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60974.651242 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60225.251357 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40330.746625 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60974.651242 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60225.251357 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|