10b70d5452
This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
867 lines
98 KiB
Plaintext
867 lines
98 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.515058 # Number of seconds simulated
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sim_ticks 515058060000 # Number of ticks simulated
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final_tick 515058060000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 166099 # Simulator instruction rate (inst/s)
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host_op_rate 185296 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 55388247 # Simulator tick rate (ticks/s)
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host_mem_usage 494292 # Number of bytes of host memory used
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host_seconds 9299.05 # Real time elapsed on the host
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sim_insts 1544563078 # Number of instructions simulated
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sim_ops 1723073890 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 48320 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 144392128 # Number of bytes read from this memory
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system.physmem.bytes_read::total 144440448 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 48320 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 48320 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 70617600 # Number of bytes written to this memory
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system.physmem.bytes_written::total 70617600 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 755 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 2256127 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 2256882 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 1103400 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1103400 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 93815 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 280341459 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 280435274 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 93815 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 93815 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 137106096 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 137106096 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 137106096 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 93815 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 280341459 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 417541370 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 2256882 # Total number of read requests seen
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system.physmem.writeReqs 1103400 # Total number of write requests seen
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system.physmem.cpureqs 3360282 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 144440448 # Total number of bytes read from memory
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system.physmem.bytesWritten 70617600 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 144440448 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 70617600 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 637 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 140407 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 144367 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 142491 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 141453 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 138510 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 140931 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 142120 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 141749 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 141832 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 140373 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 140948 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 141413 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 137790 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 141680 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 139536 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 140645 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 69366 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 70506 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 69820 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 68968 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 67927 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 68673 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 68853 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 68680 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 68439 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 68530 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 68800 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 68663 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 67351 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 70531 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 69216 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 69077 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 515058007000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 2256882 # Categorize read packet sizes
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
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system.physmem.readPktSize::8 0 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # categorize write packet sizes
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system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.writePktSize::2 0 # categorize write packet sizes
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system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::5 0 # categorize write packet sizes
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system.physmem.writePktSize::6 1103400 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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system.physmem.rdQLenPdf::0 1580398 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 450395 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 158442 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 66982 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 24 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 45630 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 47618 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 47927 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 47968 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 47973 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 47974 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 47974 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 47974 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 47974 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 47974 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 47974 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 47974 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 47974 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 47974 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 47974 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 47974 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 47974 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 47974 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 47974 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 47974 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 47974 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 47973 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 47973 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 2344 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 356 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 47 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.totQLat 27231628654 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 103251704654 # Sum of mem lat for all requests
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system.physmem.totBusLat 9024980000 # Total cycles spent in databus access
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system.physmem.totBankLat 66995096000 # Total cycles spent in bank access
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system.physmem.avgQLat 12069.45 # Average queueing delay per request
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system.physmem.avgBankLat 29693.18 # Average bank access latency per request
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system.physmem.avgBusLat 4000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 45762.63 # Average memory access latency
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system.physmem.avgRdBW 280.44 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 137.11 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 280.44 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 137.11 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 2.61 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.20 # Average read queue length over time
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system.physmem.avgWrQLen 11.32 # Average write queue length over time
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system.physmem.readRowHits 919391 # Number of row buffer hits during reads
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system.physmem.writeRowHits 189315 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 40.75 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 17.16 # Row buffer hit rate for writes
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system.physmem.avgGap 153278.21 # Average gap between requests
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 46 # Number of system calls
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system.cpu.numCycles 1030116121 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 307748972 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 253170818 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 16168830 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 178836343 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 162524431 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 18394581 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 234 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 302711500 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 2208582342 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 307748972 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 180919012 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 439713036 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 91477277 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 153604124 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 69 # Number of stall cycles due to pending traps
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system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR
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system.cpu.fetch.CacheLines 292882660 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 6106896 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 969047070 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.529561 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.216174 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 529334144 54.62% 54.62% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 25043926 2.58% 57.21% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 39264186 4.05% 61.26% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 48337631 4.99% 66.25% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 43062270 4.44% 70.69% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 47882627 4.94% 75.63% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 39313310 4.06% 79.69% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 19335068 2.00% 81.69% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 177473908 18.31% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 969047070 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.298752 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 2.144013 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 334775915 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 131820236 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 409429631 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 20003640 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 73017648 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 46459880 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 721 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 2395467722 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 2521 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 73017648 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 358478616 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 61310545 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 17059 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 404218624 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 72004578 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 2331266224 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 128849 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 5208113 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 58805545 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers
|
|
system.cpu.rename.RenamedOperands 2308002536 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 10761064902 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 10761060796 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 4106 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 1706320018 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 601682518 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 1074 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 1071 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 160130696 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 634128265 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 221560674 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 87711423 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 69100091 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 2223438682 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 1093 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 2032725138 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 5162970 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 495697928 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 1172411676 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 912 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 969047070 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 2.097654 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.906175 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 282916763 29.20% 29.20% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 152378116 15.72% 44.92% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 162831122 16.80% 61.72% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 119917560 12.37% 74.10% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 126106053 13.01% 87.11% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 74105592 7.65% 94.76% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 38169342 3.94% 98.70% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 10016302 1.03% 99.73% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 2606220 0.27% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 969047070 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 856823 3.47% 3.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 4485 0.02% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 18914760 76.65% 80.14% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 4900553 19.86% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 1244244744 61.21% 61.21% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 933049 0.05% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 31 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 15 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.26% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 593617066 29.20% 90.46% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 193930151 9.54% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 2032725138 # Type of FU issued
|
|
system.cpu.iq.rate 1.973297 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 24676621 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.012140 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 5064336479 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 2719325477 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1969225475 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 458 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 784 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 183 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 2057401528 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 231 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 63678179 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 148201485 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 301622 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 191452 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 46713618 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 3827005 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 73017648 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 27244100 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 1491546 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 2223439933 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 6134188 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 634128265 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 221560674 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1025 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 470403 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 82153 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 191452 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 8679785 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 10261943 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 18941728 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 2001081478 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 578449212 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 31643660 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 158 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 769422153 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 239265351 # Number of branches executed
|
|
system.cpu.iew.exec_stores 190972941 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.942579 # Inst execution rate
|
|
system.cpu.iew.wb_sent 1978131551 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 1969225658 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 1302526017 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 2074719324 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.911654 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.627808 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 500462812 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 181 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 16168149 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 896029423 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.923010 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.718948 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 406862083 45.41% 45.41% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 193059933 21.55% 66.95% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 73977423 8.26% 75.21% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 35390708 3.95% 79.16% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 18895903 2.11% 81.27% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 30453376 3.40% 84.67% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 19841212 2.21% 86.88% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 11401039 1.27% 88.15% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 106147746 11.85% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 896029423 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 1544563096 # Number of instructions committed
|
|
system.cpu.commit.committedOps 1723073908 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 660773836 # Number of memory references committed
|
|
system.cpu.commit.loads 485926780 # Number of loads committed
|
|
system.cpu.commit.membars 62 # Number of memory barriers committed
|
|
system.cpu.commit.branches 213462437 # Number of branches committed
|
|
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 1536941885 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 106147746 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 3013417798 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 4520246386 # The number of ROB writes
|
|
system.cpu.timesIdled 1016810 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 61069051 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 1544563078 # Number of Instructions Simulated
|
|
system.cpu.committedOps 1723073890 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 1544563078 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.666930 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.666930 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.499407 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.499407 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 10019536016 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 1949927429 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 198 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 204 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 2950890294 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 146 # number of misc regfile writes
|
|
system.cpu.icache.replacements 21 # number of replacements
|
|
system.cpu.icache.tagsinuse 635.874030 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 292881421 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 787 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 372149.200762 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 635.874030 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.310485 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.310485 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 292881421 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 292881421 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 292881421 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 292881421 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 292881421 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 292881421 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1239 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1239 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1239 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1239 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1239 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1239 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 62929999 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 62929999 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 62929999 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 62929999 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 62929999 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 62929999 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 292882660 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 292882660 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 292882660 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 292882660 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 292882660 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 292882660 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50790.959645 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 50790.959645 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 50790.959645 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 50790.959645 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 50790.959645 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 50790.959645 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 213 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 71 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 452 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 452 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 452 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 452 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 452 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 452 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 787 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 787 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 787 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 787 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 787 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 787 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42672499 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 42672499 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42672499 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 42672499 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42672499 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 42672499 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54221.726811 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54221.726811 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54221.726811 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 54221.726811 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54221.726811 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 54221.726811 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 9616996 # number of replacements
|
|
system.cpu.dcache.tagsinuse 4088.070177 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 662383558 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 9621092 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 68.847025 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 3431633000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 4088.070177 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.998064 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.998064 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 495328808 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 495328808 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 167054576 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 167054576 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 102 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 102 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 72 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 72 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 662383384 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 662383384 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 662383384 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 662383384 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 11493898 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 11493898 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 5531471 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 5531471 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 17025369 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 17025369 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 17025369 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 17025369 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 300469698500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 300469698500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 217116494201 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 217116494201 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 190500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 190500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 517586192701 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 517586192701 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 517586192701 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 517586192701 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 506822706 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 506822706 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 105 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 105 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 72 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 72 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 679408753 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 679408753 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 679408753 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 679408753 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022678 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.022678 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032051 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.032051 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.028571 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.028571 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.025059 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.025059 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.025059 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.025059 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26141.670867 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 26141.670867 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39251.131245 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 39251.131245 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63500 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63500 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30400.879576 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 30400.879576 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 30400.879576 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 30400.879576 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 19937535 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 989836 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 1174592 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 64547 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.974009 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 15.335120 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 3785750 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 3785750 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3766794 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 3766794 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3637483 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 3637483 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 7404277 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 7404277 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 7404277 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 7404277 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7727104 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 7727104 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893988 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1893988 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 9621092 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 9621092 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 9621092 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 9621092 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171327843500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 171327843500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71936813831 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 71936813831 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 243264657331 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 243264657331 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 243264657331 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 243264657331 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015246 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015246 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010974 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014161 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.014161 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014161 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.014161 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22172.322710 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22172.322710 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37981.662941 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37981.662941 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25284.516283 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25284.516283 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25284.516283 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 25284.516283 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 2224194 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 31538.307180 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 9258938 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 2253968 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 4.107839 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 20485728502 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 14439.228019 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 20.648477 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 17078.430684 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.440650 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.000630 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.521192 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.962473 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 30 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 6299217 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 6299247 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 3785750 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 3785750 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 1065742 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 1065742 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 30 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 7364959 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 7364989 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 30 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 7364959 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 7364989 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 757 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 1427887 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 1428644 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 828246 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 828246 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 757 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 2256133 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 2256890 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 757 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 2256133 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 2256890 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41571500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 98780136000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 98821707500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 58846759000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 58846759000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 41571500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 157626895000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 157668466500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 41571500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 157626895000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 157668466500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 787 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 7727104 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 7727891 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 3785750 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 3785750 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893988 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1893988 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 787 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 9621092 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 9621879 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 787 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 9621092 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 9621879 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.961881 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184789 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.184869 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.437303 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.437303 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.961881 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.234499 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.234558 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961881 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.234499 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.234558 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54916.116248 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69179.238973 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69171.681329 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71049.855961 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71049.855961 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54916.116248 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69865.958700 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 69860.944264 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54916.116248 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69865.958700 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 69860.944264 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 1103400 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 1103400 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 755 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1427881 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 1428636 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 828246 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 828246 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 755 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 2256127 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 2256882 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 755 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 2256127 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 2256882 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31971694 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 80731453067 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80763424761 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48402066091 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48402066091 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31971694 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 129133519158 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 129165490852 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31971694 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 129133519158 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 129165490852 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959339 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184789 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184868 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437303 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437303 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959339 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.234498 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.234557 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959339 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.234498 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.234557 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42346.614570 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56539.342611 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56531.842093 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58439.239177 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58439.239177 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42346.614570 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57236.812980 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57231.831727 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42346.614570 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57236.812980 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57231.831727 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|