10b70d5452
This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
842 lines
96 KiB
Plaintext
842 lines
96 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000013 # Number of seconds simulated
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sim_ticks 13414500 # Number of ticks simulated
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final_tick 13414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 64991 # Simulator instruction rate (inst/s)
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host_op_rate 81070 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 189628588 # Simulator tick rate (ticks/s)
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host_mem_usage 230428 # Number of bytes of host memory used
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host_seconds 0.07 # Real time elapsed on the host
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sim_insts 4596 # Number of instructions simulated
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sim_ops 5734 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory
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system.physmem.bytes_read::total 25600 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 400 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1326325991 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 582056730 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1908382720 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1326325991 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1326325991 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1326325991 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 582056730 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1908382720 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 401 # Total number of read requests seen
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system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 401 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 25600 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 25600 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 44 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 45 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 11 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 24 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 26 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 16 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 16 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 13356500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 401 # Categorize read packet sizes
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
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system.physmem.readPktSize::8 0 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # categorize write packet sizes
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system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.writePktSize::2 0 # categorize write packet sizes
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system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::5 0 # categorize write packet sizes
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system.physmem.writePktSize::6 0 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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system.physmem.rdQLenPdf::0 202 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 47 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.totQLat 2497399 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 10737399 # Sum of mem lat for all requests
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system.physmem.totBusLat 1604000 # Total cycles spent in databus access
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system.physmem.totBankLat 6636000 # Total cycles spent in bank access
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system.physmem.avgQLat 6227.93 # Average queueing delay per request
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system.physmem.avgBankLat 16548.63 # Average bank access latency per request
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system.physmem.avgBusLat 4000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 26776.56 # Average memory access latency
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system.physmem.avgRdBW 1908.38 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 1908.38 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 11.93 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.80 # Average read queue length over time
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system.physmem.avgWrQLen 0.00 # Average write queue length over time
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system.physmem.readRowHits 326 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 81.30 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 33307.98 # Average gap between requests
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 13 # Number of system calls
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system.cpu.numCycles 26830 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 2508 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 1799 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 498 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 1974 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 704 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 266 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 7071 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 12196 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 2508 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 970 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 2652 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 1649 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 2420 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 7 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 1943 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 295 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 13279 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.153249 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.570575 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 10627 80.03% 80.03% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 220 1.66% 81.69% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 202 1.52% 83.21% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 225 1.69% 84.90% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 209 1.57% 86.47% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 282 2.12% 88.60% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 101 0.76% 89.36% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 141 1.06% 90.42% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 1272 9.58% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 13279 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.093477 # Number of branch fetches per cycle
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system.cpu.fetch.rate 0.454566 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 7059 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 2739 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 2440 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 72 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 969 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 383 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 13357 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 554 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 969 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 7319 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 464 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 2037 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 2245 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 245 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 12559 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 194 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RenamedOperands 12597 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 57182 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 56886 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 296 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 6916 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 49 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 46 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 809 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 2771 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 1606 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 40 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 11289 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 54 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 8896 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 98 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 5254 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 14761 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 13279 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.669930 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.363134 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 9645 72.63% 72.63% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 1397 10.52% 83.15% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 791 5.96% 89.11% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 553 4.16% 93.28% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 448 3.37% 96.65% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 269 2.03% 98.67% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 121 0.91% 99.59% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 45 0.34% 99.92% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 10 0.08% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 13279 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 4 1.86% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 140 65.12% 66.98% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 71 33.02% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 5371 60.38% 60.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 2303 25.89% 86.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 1212 13.62% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 8896 # Type of FU issued
|
|
system.cpu.iq.rate 0.331569 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 215 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.024168 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 31348 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 16565 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 8055 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 9091 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 59 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1570 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 667 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 969 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 273 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 11344 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 97 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 2771 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 1606 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 41 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 15 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 286 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 387 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 8505 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 2110 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 391 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 1 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 3284 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 1437 # Number of branches executed
|
|
system.cpu.iew.exec_stores 1174 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.316996 # Inst execution rate
|
|
system.cpu.iew.wb_sent 8217 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 8071 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 3897 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 7827 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.300820 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.497892 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 5615 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 12311 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.465762 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.295726 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 10015 81.35% 81.35% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 1085 8.81% 90.16% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 395 3.21% 93.37% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 260 2.11% 95.48% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 181 1.47% 96.95% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 168 1.36% 98.32% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 52 0.42% 98.74% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 37 0.30% 99.04% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 118 0.96% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 12311 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 4596 # Number of instructions committed
|
|
system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 2140 # Number of memory references committed
|
|
system.cpu.commit.loads 1201 # Number of loads committed
|
|
system.cpu.commit.membars 12 # Number of memory barriers committed
|
|
system.cpu.commit.branches 1008 # Number of branches committed
|
|
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 4980 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 82 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 118 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 23385 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 23680 # The number of ROB writes
|
|
system.cpu.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 13551 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 4596 # Number of Instructions Simulated
|
|
system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 4596 # Number of Instructions Simulated
|
|
system.cpu.cpi 5.837685 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 5.837685 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.171301 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.171301 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 39120 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 7969 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
|
system.cpu.misc_regfile_reads 15172 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 26 # number of misc regfile writes
|
|
system.cpu.icache.replacements 4 # number of replacements
|
|
system.cpu.icache.tagsinuse 148.334500 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 1570 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 298 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 5.268456 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 148.334500 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.072429 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.072429 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 1570 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 1570 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 1570 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 1570 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 1570 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 1570 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 373 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 373 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 373 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 373 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 373 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 373 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17664000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 17664000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 17664000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 17664000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 17664000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 17664000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 1943 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 1943 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 1943 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 1943 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 1943 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 1943 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.191971 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.191971 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.191971 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.191971 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.191971 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.191971 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47356.568365 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 47356.568365 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 47356.568365 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 47356.568365 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 47356.568365 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 47356.568365 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 75 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 75 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 75 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 75 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 298 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 298 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 298 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 298 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 298 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 298 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14464500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 14464500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14464500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 14464500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14464500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 14464500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153371 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.153371 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.153371 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48538.590604 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48538.590604 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48538.590604 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 48538.590604 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48538.590604 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 48538.590604 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
system.cpu.dcache.tagsinuse 86.306986 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 2349 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 15.979592 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 86.306986 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.021071 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.021071 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 1728 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 1728 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 596 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 596 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 2324 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 2324 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 2324 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 2324 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 201 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 201 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 317 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 317 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 518 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 518 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 518 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 518 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8747500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 8747500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 15091000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 15091000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 23838500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 23838500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 23838500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 23838500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 1929 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 1929 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 2842 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 2842 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 2842 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 2842 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.104199 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.104199 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.347207 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.347207 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.182266 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.182266 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.182266 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.182266 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43519.900498 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 43519.900498 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47605.678233 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 47605.678233 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 46020.270270 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 46020.270270 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 46020.270270 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 46020.270270 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 95 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 95 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 275 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 275 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 370 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 370 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 370 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 370 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4906000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4906000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2418500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2418500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7324500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 7324500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7324500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 7324500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054951 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054951 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052076 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.052076 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052076 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.052076 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46283.018868 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46283.018868 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57583.333333 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57583.333333 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49489.864865 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 49489.864865 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49489.864865 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 49489.864865 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 186.094427 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 41 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.114525 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 140.048248 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 46.046179 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.004274 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.001405 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 21 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 41 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 41 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 41 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 363 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 405 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 405 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13965500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4578500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 18544000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2375500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 2375500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 13965500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 6954000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 20919500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 13965500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 6954000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 20919500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 298 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 404 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 298 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 446 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 298 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 446 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932886 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.801887 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.898515 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932886 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.858108 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.908072 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932886 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.858108 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.908072 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50235.611511 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53864.705882 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 51085.399449 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56559.523810 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56559.523810 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50235.611511 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54755.905512 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 51653.086420 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50235.611511 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54755.905512 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 51653.086420 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10474409 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3438066 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13912475 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1855540 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1855540 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10474409 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5293606 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 15768015 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10474409 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5293606 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 15768015 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.888614 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.831081 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.899103 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.831081 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.899103 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37677.730216 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42445.259259 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38753.412256 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 44179.523810 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 44179.523810 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37677.730216 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43037.447154 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39321.733167 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37677.730216 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43037.447154 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39321.733167 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|