This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
591 lines
68 KiB
Text
591 lines
68 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000019 # Number of seconds simulated
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sim_ticks 18578000 # Number of ticks simulated
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final_tick 18578000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 97793 # Simulator instruction rate (inst/s)
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host_op_rate 97754 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 312246493 # Simulator tick rate (ticks/s)
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host_mem_usage 216964 # Number of bytes of host memory used
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host_seconds 0.06 # Real time elapsed on the host
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sim_insts 5814 # Number of instructions simulated
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sim_ops 5814 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
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system.physmem.bytes_read::total 29120 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 20288 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 20288 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 455 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1092044354 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 475401012 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1567445365 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1092044354 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1092044354 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1092044354 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 475401012 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1567445365 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 455 # Total number of read requests seen
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system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 455 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 29120 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 29120 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 60 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 27 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 22 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 53 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 5 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 31 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 19 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 20 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 15 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 16 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 39 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 50 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 28 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 18503000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 455 # Categorize read packet sizes
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
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system.physmem.readPktSize::8 0 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # categorize write packet sizes
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system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.writePktSize::2 0 # categorize write packet sizes
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system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::5 0 # categorize write packet sizes
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system.physmem.writePktSize::6 0 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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system.physmem.rdQLenPdf::0 292 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.totQLat 2353954 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 12657954 # Sum of mem lat for all requests
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system.physmem.totBusLat 1820000 # Total cycles spent in databus access
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system.physmem.totBankLat 8484000 # Total cycles spent in bank access
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system.physmem.avgQLat 5173.53 # Average queueing delay per request
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system.physmem.avgBankLat 18646.15 # Average bank access latency per request
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system.physmem.avgBusLat 4000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 27819.68 # Average memory access latency
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system.physmem.avgRdBW 1567.45 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 1567.45 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 9.80 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.68 # Average read queue length over time
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system.physmem.avgWrQLen 0.00 # Average write queue length over time
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system.physmem.readRowHits 357 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 78.46 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 40665.93 # Average gap between requests
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 8 # Number of system calls
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system.cpu.numCycles 37157 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.branch_predictor.lookups 1146 # Number of BP lookups
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system.cpu.branch_predictor.condPredicted 844 # Number of conditional branches predicted
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system.cpu.branch_predictor.condIncorrect 605 # Number of conditional branches incorrect
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system.cpu.branch_predictor.BTBLookups 861 # Number of BTB lookups
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system.cpu.branch_predictor.BTBHits 300 # Number of BTB hits
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system.cpu.branch_predictor.usedRAS 86 # Number of times the RAS was used to get a target.
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system.cpu.branch_predictor.RASInCorrect 32 # Number of incorrect RAS predictions.
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system.cpu.branch_predictor.BTBHitPct 34.843206 # BTB Hit Percentage
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system.cpu.branch_predictor.predictedTaken 393 # Number of Branches Predicted As Taken (True).
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system.cpu.branch_predictor.predictedNotTaken 753 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileReads 5127 # Number of Reads from Int. Register File
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system.cpu.regfile_manager.intRegFileWrites 3396 # Number of Writes to Int. Register File
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system.cpu.regfile_manager.intRegFileAccesses 8523 # Total Accesses (Read+Write) to the Int. Register File
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system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File
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system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File
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system.cpu.regfile_manager.regForwards 1290 # Number of Registers Read Through Forwarding Logic
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system.cpu.agen_unit.agens 2235 # Number of Address Generations
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system.cpu.execution_unit.predictedTakenIncorrect 260 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.execution_unit.predictedNotTakenIncorrect 336 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.execution_unit.mispredicted 596 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.predicted 319 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.mispredictPct 65.136612 # Percentage of Incorrect Branches Predicts
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system.cpu.execution_unit.executions 3144 # Number of Instructions Executed.
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system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed
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system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed
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system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.threadCycles 9465 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
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system.cpu.timesIdled 477 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu.idleCycles 31782 # Number of cycles cpu's stages were not processed
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system.cpu.runCycles 5375 # Number of cycles cpu stages are processed.
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system.cpu.activity 14.465646 # Percentage of cycles cpu is active
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system.cpu.comLoads 1163 # Number of Load instructions committed
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system.cpu.comStores 925 # Number of Store instructions committed
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system.cpu.comBranches 915 # Number of Branches instructions committed
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system.cpu.comNops 657 # Number of Nop instructions committed
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system.cpu.comNonSpec 10 # Number of Non-Speculative instructions committed
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system.cpu.comInts 2144 # Number of Integer instructions committed
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system.cpu.comFloats 0 # Number of Floating Point instructions committed
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system.cpu.committedInsts 5814 # Number of Instructions committed (Per-Thread)
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system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread)
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system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
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system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total)
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system.cpu.cpi 6.390953 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.smt_cpi nan # CPI: Total SMT-CPI
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system.cpu.cpi_total 6.390953 # CPI: Total CPI of All Threads
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system.cpu.ipc 0.156471 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.smt_ipc nan # IPC: Total SMT-IPC
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system.cpu.ipc_total 0.156471 # IPC: Total IPC of All Threads
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system.cpu.stage0.idleCycles 33517 # Number of cycles 0 instructions are processed.
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system.cpu.stage0.runCycles 3640 # Number of cycles 1+ instructions are processed.
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system.cpu.stage0.utilization 9.796270 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.idleCycles 34336 # Number of cycles 0 instructions are processed.
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system.cpu.stage1.runCycles 2821 # Number of cycles 1+ instructions are processed.
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system.cpu.stage1.utilization 7.592109 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage2.idleCycles 34391 # Number of cycles 0 instructions are processed.
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system.cpu.stage2.runCycles 2766 # Number of cycles 1+ instructions are processed.
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system.cpu.stage2.utilization 7.444089 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage3.idleCycles 35931 # Number of cycles 0 instructions are processed.
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system.cpu.stage3.runCycles 1226 # Number of cycles 1+ instructions are processed.
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system.cpu.stage3.utilization 3.299513 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage4.idleCycles 34254 # Number of cycles 0 instructions are processed.
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system.cpu.stage4.runCycles 2903 # Number of cycles 1+ instructions are processed.
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system.cpu.stage4.utilization 7.812794 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.icache.replacements 13 # number of replacements
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system.cpu.icache.tagsinuse 149.857420 # Cycle average of tags in use
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system.cpu.icache.total_refs 410 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 1.285266 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 149.857420 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.073173 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.073173 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 410 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 410 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 410 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 410 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 410 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 410 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 346 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 346 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 346 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 346 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 346 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 346 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 18065500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 18065500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 18065500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 18065500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 18065500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 18065500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 756 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 756 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 756 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 756 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 756 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 756 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.457672 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.457672 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.457672 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.457672 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.457672 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.457672 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52212.427746 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 52212.427746 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52212.427746 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 52212.427746 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52212.427746 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 52212.427746 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 27 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 27 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 27 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 27 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 319 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 319 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 319 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16466000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 16466000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16466000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 16466000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16466000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 16466000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.421958 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.421958 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.421958 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.421958 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.421958 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.421958 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51617.554859 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51617.554859 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51617.554859 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 51617.554859 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51617.554859 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 51617.554859 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
system.cpu.dcache.tagsinuse 89.860913 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 1644 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 11.913043 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 89.860913 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.021939 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.021939 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 1070 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 1070 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 574 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 574 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 1644 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 1644 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 1644 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 1644 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 93 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 93 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 351 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 351 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 444 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 444 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 444 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 444 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5589000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 5589000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 14658500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 14658500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 20247500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 20247500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 20247500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 20247500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 2088 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079966 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.079966 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.379459 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.379459 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.212644 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.212644 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.212644 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.212644 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60096.774194 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 60096.774194 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41762.108262 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 41762.108262 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45602.477477 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 45602.477477 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 45602.477477 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 45602.477477 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 99 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 99 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 300 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 300 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 306 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 306 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 306 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 306 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5155000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5155000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2618500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2618500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7773500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 7773500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7773500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 7773500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59252.873563 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59252.873563 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51343.137255 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51343.137255 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56329.710145 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 56329.710145 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56329.710145 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 56329.710145 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 207.494837 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 151.607312 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 55.887525 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.004627 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.001706 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.006332 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 317 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 404 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 317 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 455 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 455 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16120500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5061500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 21182000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2564500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 2564500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 16120500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 7626000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 23746500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 16120500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 7626000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 23746500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 319 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 457 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 319 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 457 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993730 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.995074 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993730 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.995624 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50853.312303 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58178.160920 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52430.693069 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50284.313725 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50284.313725 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50853.312303 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55260.869565 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 52190.109890 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50853.312303 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55260.869565 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 52190.109890 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 317 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 404 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 317 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 455 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12117017 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3982094 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16099111 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1929572 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1929572 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12117017 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5911666 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 18028683 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12117017 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5911666 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 18028683 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38224.028391 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45771.195402 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39849.284653 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37834.745098 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37834.745098 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38224.028391 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42838.159420 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39623.479121 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38224.028391 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42838.159420 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39623.479121 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|