gem5/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000003                       # Number of seconds simulated
sim_ticks                                     2695000                       # Number of ticks simulated
final_tick                                    2695000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  88081                       # Simulator instruction rate (inst/s)
host_op_rate                                   103121                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               51657705                       # Simulator tick rate (ticks/s)
host_mem_usage                                 292672                       # Number of bytes of host memory used
host_seconds                                     0.05                       # Real time elapsed on the host
sim_insts                                        4592                       # Number of instructions simulated
sim_ops                                          5378                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             18420                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data              4491                       # Number of bytes read from this memory
system.physmem.bytes_read::total                22911                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        18420                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           18420                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data           3648                       # Number of bytes written to this memory
system.physmem.bytes_written::total              3648                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               4605                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               1003                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  5608                       # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data               924                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                  924                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst           6834879406                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data           1666419295                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              8501298701                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst      6834879406                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total         6834879406                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data          1353617811                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total             1353617811                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst          6834879406                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data          3020037106                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             9854916512                       # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0                       # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.checker.dtb.walker.walks                 0                       # Table walker walks requested
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
system.cpu.checker.dtb.read_hits                    0                       # DTB read hits
system.cpu.checker.dtb.read_misses                  0                       # DTB read misses
system.cpu.checker.dtb.write_hits                   0                       # DTB write hits
system.cpu.checker.dtb.write_misses                 0                       # DTB write misses
system.cpu.checker.dtb.flush_tlb                    0                       # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid               0                       # Number of times TLB was flushed by ASID
system.cpu.checker.dtb.flush_entries                0                       # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.dtb.prefetch_faults              0                       # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.dtb.read_accesses                0                       # DTB read accesses
system.cpu.checker.dtb.write_accesses               0                       # DTB write accesses
system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
system.cpu.checker.dtb.hits                         0                       # DTB hits
system.cpu.checker.dtb.misses                       0                       # DTB misses
system.cpu.checker.dtb.accesses                     0                       # DTB accesses
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.checker.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.checker.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.checker.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.checker.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.checker.istage2_mmu.stage2_tlb.hits            0                       # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.checker.itb.walker.walks                 0                       # Table walker walks requested
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.itb.inst_hits                    0                       # ITB inst hits
system.cpu.checker.itb.inst_misses                  0                       # ITB inst misses
system.cpu.checker.itb.read_hits                    0                       # DTB read hits
system.cpu.checker.itb.read_misses                  0                       # DTB read misses
system.cpu.checker.itb.write_hits                   0                       # DTB write hits
system.cpu.checker.itb.write_misses                 0                       # DTB write misses
system.cpu.checker.itb.flush_tlb                    0                       # Number of times complete TLB was flushed
system.cpu.checker.itb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid               0                       # Number of times TLB was flushed by ASID
system.cpu.checker.itb.flush_entries                0                       # Number of entries that have been flushed from TLB
system.cpu.checker.itb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults              0                       # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults                0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
system.cpu.checker.itb.inst_accesses                0                       # ITB inst accesses
system.cpu.checker.itb.hits                         0                       # DTB hits
system.cpu.checker.itb.misses                       0                       # DTB misses
system.cpu.checker.itb.accesses                     0                       # DTB accesses
system.cpu.workload.num_syscalls                   13                       # Number of system calls
system.cpu.checker.numCycles                        0                       # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.numCycles                             5391                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                        4592                       # Number of instructions committed
system.cpu.committedOps                          5378                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses                  4624                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
system.cpu.num_func_calls                         203                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts          722                       # number of instructions that are conditional controls
system.cpu.num_int_insts                         4624                       # number of integer instructions
system.cpu.num_fp_insts                            16                       # number of float instructions
system.cpu.num_int_register_reads                7607                       # number of times the integer registers were read
system.cpu.num_int_register_writes               2728                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_cc_register_reads                16175                       # number of times the CC registers were read
system.cpu.num_cc_register_writes                2432                       # number of times the CC registers were written
system.cpu.num_mem_refs                          1965                       # number of memory refs
system.cpu.num_load_insts                        1027                       # Number of load instructions
system.cpu.num_store_insts                        938                       # Number of store instructions
system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
system.cpu.num_busy_cycles                5390.998000                       # Number of busy cycles
system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
system.cpu.Branches                              1008                       # Number of branches fetched
system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
system.cpu.op_class::IntAlu                      3419     63.42%     63.42% # Class of executed instruction
system.cpu.op_class::IntMult                        4      0.07%     63.49% # Class of executed instruction
system.cpu.op_class::IntDiv                         0      0.00%     63.49% # Class of executed instruction
system.cpu.op_class::FloatAdd                       0      0.00%     63.49% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     63.49% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     63.49% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     63.49% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     63.49% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     63.49% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     63.49% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     63.49% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     63.49% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     63.49% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     63.49% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     63.49% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     63.49% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     63.49% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     63.49% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     63.49% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     63.49% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     63.49% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     63.49% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                   0      0.00%     63.49% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                   0      0.00%     63.49% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     63.49% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc                  3      0.06%     63.55% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     63.55% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     63.55% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     63.55% # Class of executed instruction
system.cpu.op_class::MemRead                     1027     19.05%     82.60% # Class of executed instruction
system.cpu.op_class::MemWrite                     938     17.40%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                       5391                       # Class of executed instruction
system.membus.trans_dist::ReadReq                5597                       # Transaction distribution
system.membus.trans_dist::ReadResp               5608                       # Transaction distribution
system.membus.trans_dist::WriteReq                913                       # Transaction distribution
system.membus.trans_dist::WriteResp               913                       # Transaction distribution
system.membus.trans_dist::LoadLockedReq            11                       # Transaction distribution
system.membus.trans_dist::StoreCondReq             11                       # Transaction distribution
system.membus.trans_dist::StoreCondResp            11                       # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port         9210                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port         3854                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  13064                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port        18420                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port         8139                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   26559                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples              6532                       # Request fanout histogram
system.membus.snoop_fanout::mean             2.704991                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.456082                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::2                    1927     29.50%     29.50% # Request fanout histogram
system.membus.snoop_fanout::3                    4605     70.50%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               2                       # Request fanout histogram
system.membus.snoop_fanout::max_value               3                       # Request fanout histogram
system.membus.snoop_fanout::total                6532                       # Request fanout histogram

---------- End Simulation Statistics   ----------