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gem5/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini

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ARM: Add regression tests
2010-07-27 07:03:44 +02:00
[root]
type=Root
children=system
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
full_system=false
stats: update stats for cache occupancy and clock domain changes
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sim_quantum=0
Stats: Re update stats.
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time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
[system]
type=System
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
boot_osflags=a
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
cache_line_size=64
clk_domain=system.clk_domain
stats: update stats for cache occupancy and clock domain changes
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eventq_index=0
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
init_param=0
kernel=
load_addr_mask=1099511627775
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
mem_mode=atomic
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
mem_ranges=
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
memories=system.physmem
num_work_ids=16
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
readfile=
symbolfile=
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
system_port=system.membus.slave[0]
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.clk_domain]
type=SrcClockDomain
clock=1000
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage_domain=system.voltage_domain
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
[system.cpu]
type=AtomicSimpleCPU
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
children=dtb interrupts isa itb tracer workload
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
checker=Null
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
cpu_id=0
do_checkpoint_insts=true
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
do_quiesce=true
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
do_statistics_insts=true
dtb=system.cpu.dtb
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
fastmem=false
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
function_trace=false
function_trace_start=0
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
interrupts=system.cpu.interrupts
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
isa=system.cpu.isa
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
profile=0
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
progress_interval=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
simpoint_interval=100000000
simpoint_profile=false
simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
simulate_data_stalls=false
simulate_inst_stalls=false
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
switched_out=false
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
[system.cpu.dtb]
type=ArmTLB
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
children=walker
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
size=64
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
num_squash_per_cycle=2
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
sys=system
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
port=system.membus.slave[4]
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
[system.cpu.interrupts]
type=ArmInterrupts
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
[system.cpu.isa]
type=ArmISA
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
[system.cpu.itb]
type=ArmTLB
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
children=walker
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
size=64
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
num_squash_per_cycle=2
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
sys=system
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
port=system.membus.slave[3]
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
[system.cpu.tracer]
type=ExeTracer
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
egid=100
env=
errout=cerr
euid=100
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
executable=/dist/cpu2000/binaries/arm/linux/eon
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage_domain=system.voltage_domain
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
[system.membus]
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
type=CoherentBus
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
header_cycles=1
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system=system
tests: update reference config.ini files for previous cset Rename 'responder_set' to 'use_default_range'.
2010-08-17 14:06:22 +02:00
use_default_range=false
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
width=8
master=system.physmem.port
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
[system.physmem]
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
type=SimpleMemory
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
bandwidth=73.000000
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
conf_table_reported=true
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
in_addr_map=true
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
latency=30000
latency_var=0
null=false
range=0:134217727
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
port=system.membus.master[0]
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.voltage_domain]
type=VoltageDomain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage=1.000000
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