2012-09-21 17:48:13 +02:00
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/*
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2015-07-03 16:14:45 +02:00
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* Copyright (c) 2010-2015 ARM Limited
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2012-09-21 17:48:13 +02:00
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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2013-08-19 09:52:30 +02:00
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* Copyright (c) 2013 Amin Farmahini-Farahani
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* All rights reserved.
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*
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2012-09-21 17:48:13 +02:00
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andreas Hansson
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* Ani Udipi
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2013-11-01 16:56:20 +01:00
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* Neha Agarwal
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2014-12-23 15:31:18 +01:00
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* Omar Naji
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2012-09-21 17:48:13 +02:00
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*/
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2013-11-01 16:56:20 +01:00
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#include "base/bitfield.hh"
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2014-03-23 16:12:12 +01:00
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#include "base/trace.hh"
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2012-09-21 17:48:13 +02:00
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#include "debug/DRAM.hh"
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2014-06-30 19:56:03 +02:00
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#include "debug/DRAMPower.hh"
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2014-05-10 00:58:48 +02:00
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#include "debug/DRAMState.hh"
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2014-03-23 16:12:12 +01:00
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#include "debug/Drain.hh"
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#include "mem/dram_ctrl.hh"
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2013-07-18 14:31:16 +02:00
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#include "sim/system.hh"
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2012-09-21 17:48:13 +02:00
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using namespace std;
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2014-07-29 18:22:44 +02:00
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using namespace Data;
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2012-09-21 17:48:13 +02:00
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2014-03-23 16:12:12 +01:00
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DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) :
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2012-09-21 17:48:13 +02:00
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AbstractMemory(p),
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2014-12-23 15:31:18 +01:00
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port(name() + ".port", *this), isTimingMode(false),
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2012-09-21 17:48:13 +02:00
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retryRdReq(false), retryWrReq(false),
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2014-05-10 00:58:48 +02:00
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busState(READ),
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2014-12-23 15:31:18 +01:00
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nextReqEvent(this), respondEvent(this),
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2014-05-10 00:58:48 +02:00
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drainManager(NULL),
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2014-10-21 00:03:52 +02:00
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deviceSize(p->device_size),
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2013-08-19 09:52:30 +02:00
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deviceBusWidth(p->device_bus_width), burstLength(p->burst_length),
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deviceRowBufferSize(p->device_rowbuffer_size),
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devicesPerRank(p->devices_per_rank),
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burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8),
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rowBufferSize(devicesPerRank * deviceRowBufferSize),
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2014-03-23 16:12:01 +01:00
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columnsPerRowBuffer(rowBufferSize / burstSize),
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2015-01-20 14:11:55 +01:00
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columnsPerStripe(range.interleaved() ? range.granularity() / burstSize : 1),
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2012-09-21 17:48:13 +02:00
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ranksPerChannel(p->ranks_per_channel),
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2014-09-20 23:18:21 +02:00
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bankGroupsPerRank(p->bank_groups_per_rank),
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bankGroupArch(p->bank_groups_per_rank > 0),
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2013-03-01 19:20:22 +01:00
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banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0),
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2012-09-21 17:48:13 +02:00
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readBufferSize(p->read_buffer_size),
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writeBufferSize(p->write_buffer_size),
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2014-03-23 16:12:01 +01:00
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writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0),
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writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0),
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2014-03-23 16:12:14 +01:00
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minWritesPerSwitch(p->min_writes_per_switch),
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writesThisTime(0), readsThisTime(0),
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2014-09-20 23:17:57 +02:00
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tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST),
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2014-09-20 23:18:21 +02:00
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tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS),
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tWR(p->tWR), tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD),
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tRRD_L(p->tRRD_L), tXAW(p->tXAW), activationLimit(p->activation_limit),
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2012-09-21 17:48:13 +02:00
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memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping),
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pageMgmt(p->page_policy),
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2014-03-23 16:12:03 +01:00
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maxAccessesPerRow(p->max_accesses_per_row),
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2013-05-30 18:54:12 +02:00
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frontendLatency(p->static_frontend_latency),
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backendLatency(p->static_backend_latency),
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2014-12-23 15:31:18 +01:00
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busBusyUntil(0), prevArrival(0),
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nextReqTime(0), activeRank(0), timeStampOffset(0)
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2012-09-21 17:48:13 +02:00
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{
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2014-12-23 15:31:18 +01:00
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// sanity check the ranks since we rely on bit slicing for the
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// address decoding
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fatal_if(!isPowerOf2(ranksPerChannel), "DRAM rank count of %d is not "
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"allowed, must be a power of two\n", ranksPerChannel);
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2015-07-03 16:14:45 +02:00
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fatal_if(!isPowerOf2(burstSize), "DRAM burst size %d is not allowed, "
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"must be a power of two\n", burstSize);
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2014-07-29 18:22:44 +02:00
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for (int i = 0; i < ranksPerChannel; i++) {
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2014-12-23 15:31:18 +01:00
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Rank* rank = new Rank(*this, p);
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ranks.push_back(rank);
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2014-07-29 18:22:44 +02:00
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2014-12-23 15:31:18 +01:00
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rank->actTicks.resize(activationLimit, 0);
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rank->banks.resize(banksPerRank);
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rank->rank = i;
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2012-09-21 17:48:13 +02:00
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2014-06-30 19:56:02 +02:00
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for (int b = 0; b < banksPerRank; b++) {
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2014-12-23 15:31:18 +01:00
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rank->banks[b].bank = b;
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2014-12-02 12:07:32 +01:00
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// GDDR addressing of banks to BG is linear.
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// Here we assume that all DRAM generations address bank groups as
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// follows:
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2014-09-20 23:18:21 +02:00
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if (bankGroupArch) {
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// Simply assign lower bits to bank group in order to
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// rotate across bank groups as banks are incremented
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// e.g. with 4 banks per bank group and 16 banks total:
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// banks 0,4,8,12 are in bank group 0
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// banks 1,5,9,13 are in bank group 1
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// banks 2,6,10,14 are in bank group 2
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// banks 3,7,11,15 are in bank group 3
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2014-12-23 15:31:18 +01:00
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rank->banks[b].bankgr = b % bankGroupsPerRank;
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2014-09-20 23:18:21 +02:00
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} else {
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// No bank groups; simply assign to bank number
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2014-12-23 15:31:18 +01:00
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rank->banks[b].bankgr = b;
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2014-09-20 23:18:21 +02:00
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}
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2014-06-30 19:56:02 +02:00
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}
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}
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2014-03-23 16:12:01 +01:00
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// perform a basic check of the write thresholds
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if (p->write_low_thresh_perc >= p->write_high_thresh_perc)
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fatal("Write buffer low threshold %d must be smaller than the "
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"high threshold %d\n", p->write_low_thresh_perc,
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p->write_high_thresh_perc);
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2012-09-21 17:48:13 +02:00
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// determine the rows per bank by looking at the total capacity
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2013-03-01 19:20:24 +01:00
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uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size());
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2012-09-21 17:48:13 +02:00
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2014-10-21 00:03:52 +02:00
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// determine the dram actual capacity from the DRAM config in Mbytes
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uint64_t deviceCapacity = deviceSize / (1024 * 1024) * devicesPerRank *
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ranksPerChannel;
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// if actual DRAM size does not match memory capacity in system warn!
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if (deviceCapacity != capacity / (1024 * 1024))
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warn("DRAM device capacity (%d Mbytes) does not match the "
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"address range assigned (%d Mbytes)\n", deviceCapacity,
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capacity / (1024 * 1024));
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2012-09-21 17:48:13 +02:00
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DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity,
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AbstractMemory::size());
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2013-08-19 09:52:30 +02:00
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DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n",
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rowBufferSize, columnsPerRowBuffer);
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rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel);
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2012-09-21 17:48:13 +02:00
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2014-05-10 00:58:48 +02:00
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// some basic sanity checks
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if (tREFI <= tRP || tREFI <= tRFC) {
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fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n",
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tREFI, tRP, tRFC);
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}
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2014-09-20 23:18:21 +02:00
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// basic bank group architecture checks ->
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if (bankGroupArch) {
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// must have at least one bank per bank group
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if (bankGroupsPerRank > banksPerRank) {
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fatal("banks per rank (%d) must be equal to or larger than "
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"banks groups per rank (%d)\n",
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banksPerRank, bankGroupsPerRank);
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}
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// must have same number of banks in each bank group
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if ((banksPerRank % bankGroupsPerRank) != 0) {
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fatal("Banks per rank (%d) must be evenly divisible by bank groups "
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"per rank (%d) for equal banks per bank group\n",
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banksPerRank, bankGroupsPerRank);
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}
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// tCCD_L should be greater than minimal, back-to-back burst delay
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if (tCCD_L <= tBURST) {
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fatal("tCCD_L (%d) should be larger than tBURST (%d) when "
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"bank groups per rank (%d) is greater than 1\n",
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tCCD_L, tBURST, bankGroupsPerRank);
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}
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// tRRD_L is greater than minimal, same bank group ACT-to-ACT delay
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2014-12-02 12:07:32 +01:00
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// some datasheets might specify it equal to tRRD
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if (tRRD_L < tRRD) {
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2014-09-20 23:18:21 +02:00
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fatal("tRRD_L (%d) should be larger than tRRD (%d) when "
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"bank groups per rank (%d) is greater than 1\n",
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tRRD_L, tRRD, bankGroupsPerRank);
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}
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}
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2012-09-21 17:48:13 +02:00
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}
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2014-03-23 16:12:01 +01:00
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void
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2014-03-23 16:12:12 +01:00
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DRAMCtrl::init()
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2014-03-23 16:12:01 +01:00
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{
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2014-10-16 11:49:43 +02:00
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AbstractMemory::init();
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if (!port.isConnected()) {
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2014-03-23 16:12:12 +01:00
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fatal("DRAMCtrl %s is unconnected!\n", name());
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2014-03-23 16:12:01 +01:00
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} else {
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port.sendRangeChange();
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}
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2015-01-20 14:11:55 +01:00
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// a bit of sanity checks on the interleaving, save it for here to
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// ensure that the system pointer is initialised
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if (range.interleaved()) {
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if (channels != range.stripes())
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fatal("%s has %d interleaved address stripes but %d channel(s)\n",
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name(), range.stripes(), channels);
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if (addrMapping == Enums::RoRaBaChCo) {
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if (rowBufferSize != range.granularity()) {
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fatal("Channel interleaving of %s doesn't match RoRaBaChCo "
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"address map\n", name());
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}
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} else if (addrMapping == Enums::RoRaBaCoCh ||
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addrMapping == Enums::RoCoRaBaCh) {
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// for the interleavings with channel bits in the bottom,
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// if the system uses a channel striping granularity that
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// is larger than the DRAM burst size, then map the
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// sequential accesses within a stripe to a number of
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// columns in the DRAM, effectively placing some of the
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// lower-order column bits as the least-significant bits
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// of the address (above the ones denoting the burst size)
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assert(columnsPerStripe >= 1);
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// channel striping has to be done at a granularity that
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// is equal or larger to a cache line
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if (system()->cacheLineSize() > range.granularity()) {
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fatal("Channel interleaving of %s must be at least as large "
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"as the cache line size\n", name());
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}
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// ...and equal or smaller than the row-buffer size
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if (rowBufferSize < range.granularity()) {
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fatal("Channel interleaving of %s must be at most as large "
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"as the row-buffer size\n", name());
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}
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// this is essentially the check above, so just to be sure
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assert(columnsPerStripe <= columnsPerRowBuffer);
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}
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}
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2014-03-23 16:12:01 +01:00
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}
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2012-09-21 17:48:13 +02:00
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void
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2014-03-23 16:12:12 +01:00
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DRAMCtrl::startup()
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2012-09-21 17:48:13 +02:00
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{
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2014-12-23 15:31:18 +01:00
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// remember the memory system mode of operation
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isTimingMode = system()->isTimingMode();
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2014-12-23 15:31:18 +01:00
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2014-12-23 15:31:18 +01:00
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if (isTimingMode) {
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// timestamp offset should be in clock cycles for DRAMPower
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timeStampOffset = divCeil(curTick(), tCK);
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// update the start tick for the precharge accounting to the
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// current tick
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for (auto r : ranks) {
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r->startup(curTick() + tREFI - tRP);
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}
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2014-03-23 16:12:06 +01:00
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2014-12-23 15:31:18 +01:00
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// shift the bus busy time sufficiently far ahead that we never
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// have to worry about negative values when computing the time for
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// the next request, this will add an insignificant bubble at the
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// start of simulation
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busBusyUntil = curTick() + tRP + tRCD + tCL;
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}
|
2012-09-21 17:48:13 +02:00
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}
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Tick
|
2014-03-23 16:12:12 +01:00
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DRAMCtrl::recvAtomic(PacketPtr pkt)
|
2012-09-21 17:48:13 +02:00
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{
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DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr());
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// do the actual memory access and turn the packet into a response
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access(pkt);
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|
|
|
|
|
|
Tick latency = 0;
|
|
|
|
if (!pkt->memInhibitAsserted() && pkt->hasData()) {
|
|
|
|
// this value is not supposed to be accurate, just enough to
|
|
|
|
// keep things going, mimic a closed page
|
|
|
|
latency = tRP + tRCD + tCL;
|
|
|
|
}
|
|
|
|
return latency;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::readQueueFull(unsigned int neededEntries) const
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
2013-08-19 09:52:30 +02:00
|
|
|
DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n",
|
|
|
|
readBufferSize, readQueue.size() + respQueue.size(),
|
|
|
|
neededEntries);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
return
|
|
|
|
(readQueue.size() + respQueue.size() + neededEntries) > readBufferSize;
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::writeQueueFull(unsigned int neededEntries) const
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
2013-08-19 09:52:30 +02:00
|
|
|
DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n",
|
|
|
|
writeBufferSize, writeQueue.size(), neededEntries);
|
|
|
|
return (writeQueue.size() + neededEntries) > writeBufferSize;
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::DRAMPacket*
|
|
|
|
DRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size,
|
2014-03-23 16:12:06 +01:00
|
|
|
bool isRead)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
2013-04-22 19:20:34 +02:00
|
|
|
// decode the address based on the address mapping scheme, with
|
2014-03-23 16:11:53 +01:00
|
|
|
// Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and
|
|
|
|
// channel, respectively
|
2012-09-21 17:48:13 +02:00
|
|
|
uint8_t rank;
|
2013-11-01 16:56:20 +01:00
|
|
|
uint8_t bank;
|
2014-06-30 19:56:01 +02:00
|
|
|
// use a 64-bit unsigned during the computations as the row is
|
|
|
|
// always the top bits, and check before creating the DRAMPacket
|
|
|
|
uint64_t row;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2014-08-26 16:12:45 +02:00
|
|
|
// truncate the address to a DRAM burst, which makes it unique to
|
|
|
|
// a specific column, row, bank, rank and channel
|
2013-08-19 09:52:30 +02:00
|
|
|
Addr addr = dramPktAddr / burstSize;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-01-31 13:49:18 +01:00
|
|
|
// we have removed the lowest order address bits that denote the
|
2013-08-19 09:52:30 +02:00
|
|
|
// position within the column
|
2014-03-23 16:11:53 +01:00
|
|
|
if (addrMapping == Enums::RoRaBaChCo) {
|
2013-01-31 13:49:18 +01:00
|
|
|
// the lowest order bits denote the column to ensure that
|
|
|
|
// sequential cache lines occupy the same row
|
2013-08-19 09:52:30 +02:00
|
|
|
addr = addr / columnsPerRowBuffer;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-04-22 19:20:34 +02:00
|
|
|
// take out the channel part of the address
|
|
|
|
addr = addr / channels;
|
|
|
|
|
|
|
|
// after the channel bits, get the bank bits to interleave
|
|
|
|
// over the banks
|
|
|
|
bank = addr % banksPerRank;
|
|
|
|
addr = addr / banksPerRank;
|
|
|
|
|
|
|
|
// after the bank, we get the rank bits which thus interleaves
|
|
|
|
// over the ranks
|
|
|
|
rank = addr % ranksPerChannel;
|
|
|
|
addr = addr / ranksPerChannel;
|
|
|
|
|
|
|
|
// lastly, get the row bits
|
|
|
|
row = addr % rowsPerBank;
|
|
|
|
addr = addr / rowsPerBank;
|
2014-03-23 16:11:53 +01:00
|
|
|
} else if (addrMapping == Enums::RoRaBaCoCh) {
|
2014-08-26 16:12:45 +02:00
|
|
|
// take out the lower-order column bits
|
|
|
|
addr = addr / columnsPerStripe;
|
|
|
|
|
2013-04-22 19:20:34 +02:00
|
|
|
// take out the channel part of the address
|
2013-03-01 19:20:22 +01:00
|
|
|
addr = addr / channels;
|
|
|
|
|
2014-08-26 16:12:45 +02:00
|
|
|
// next, the higher-order column bites
|
|
|
|
addr = addr / (columnsPerRowBuffer / columnsPerStripe);
|
2013-04-22 19:20:34 +02:00
|
|
|
|
|
|
|
// after the column bits, we get the bank bits to interleave
|
2013-01-31 13:49:18 +01:00
|
|
|
// over the banks
|
2012-09-21 17:48:13 +02:00
|
|
|
bank = addr % banksPerRank;
|
|
|
|
addr = addr / banksPerRank;
|
|
|
|
|
2013-01-31 13:49:18 +01:00
|
|
|
// after the bank, we get the rank bits which thus interleaves
|
|
|
|
// over the ranks
|
2012-09-21 17:48:13 +02:00
|
|
|
rank = addr % ranksPerChannel;
|
|
|
|
addr = addr / ranksPerChannel;
|
|
|
|
|
2013-01-31 13:49:18 +01:00
|
|
|
// lastly, get the row bits
|
2012-09-21 17:48:13 +02:00
|
|
|
row = addr % rowsPerBank;
|
|
|
|
addr = addr / rowsPerBank;
|
2014-03-23 16:11:53 +01:00
|
|
|
} else if (addrMapping == Enums::RoCoRaBaCh) {
|
2013-01-31 13:49:18 +01:00
|
|
|
// optimise for closed page mode and utilise maximum
|
|
|
|
// parallelism of the DRAM (at the cost of power)
|
|
|
|
|
2014-08-26 16:12:45 +02:00
|
|
|
// take out the lower-order column bits
|
|
|
|
addr = addr / columnsPerStripe;
|
|
|
|
|
2013-03-01 19:20:22 +01:00
|
|
|
// take out the channel part of the address, not that this has
|
|
|
|
// to match with how accesses are interleaved between the
|
|
|
|
// controllers in the address mapping
|
|
|
|
addr = addr / channels;
|
|
|
|
|
2013-01-31 13:49:18 +01:00
|
|
|
// start with the bank bits, as this provides the maximum
|
|
|
|
// opportunity for parallelism between requests
|
2012-09-21 17:48:13 +02:00
|
|
|
bank = addr % banksPerRank;
|
|
|
|
addr = addr / banksPerRank;
|
|
|
|
|
2013-01-31 13:49:18 +01:00
|
|
|
// next get the rank bits
|
2012-09-21 17:48:13 +02:00
|
|
|
rank = addr % ranksPerChannel;
|
|
|
|
addr = addr / ranksPerChannel;
|
|
|
|
|
2014-08-26 16:12:45 +02:00
|
|
|
// next, the higher-order column bites
|
|
|
|
addr = addr / (columnsPerRowBuffer / columnsPerStripe);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-01-31 13:49:18 +01:00
|
|
|
// lastly, get the row bits
|
2012-09-21 17:48:13 +02:00
|
|
|
row = addr % rowsPerBank;
|
|
|
|
addr = addr / rowsPerBank;
|
|
|
|
} else
|
|
|
|
panic("Unknown address mapping policy chosen!");
|
|
|
|
|
|
|
|
assert(rank < ranksPerChannel);
|
|
|
|
assert(bank < banksPerRank);
|
|
|
|
assert(row < rowsPerBank);
|
2014-06-30 19:56:01 +02:00
|
|
|
assert(row < Bank::NO_ROW);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n",
|
2013-08-19 09:52:30 +02:00
|
|
|
dramPktAddr, rank, bank, row);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
// create the corresponding DRAM packet with the entry time and
|
2013-03-01 19:20:24 +01:00
|
|
|
// ready time set to the current tick, the latter will be updated
|
|
|
|
// later
|
2013-11-01 16:56:20 +01:00
|
|
|
uint16_t bank_id = banksPerRank * rank + bank;
|
|
|
|
return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr,
|
2014-12-23 15:31:18 +01:00
|
|
|
size, ranks[rank]->banks[bank], *ranks[rank]);
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
// only add to the read queue here. whenever the request is
|
|
|
|
// eventually done, set the readyTime, and call schedule()
|
|
|
|
assert(!pkt->isWrite());
|
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
assert(pktCount != 0);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
// if the request size is larger than burst size, the pkt is split into
|
|
|
|
// multiple DRAM packets
|
|
|
|
// Note if the pkt starting address is not aligened to burst size, the
|
|
|
|
// address of first DRAM packet is kept unaliged. Subsequent DRAM packets
|
|
|
|
// are aligned to burst size boundaries. This is to ensure we accurately
|
|
|
|
// check read packets against packets in write queue.
|
|
|
|
Addr addr = pkt->getAddr();
|
|
|
|
unsigned pktsServicedByWrQ = 0;
|
|
|
|
BurstHelper* burst_helper = NULL;
|
|
|
|
for (int cnt = 0; cnt < pktCount; ++cnt) {
|
|
|
|
unsigned size = std::min((addr | (burstSize - 1)) + 1,
|
|
|
|
pkt->getAddr() + pkt->getSize()) - addr;
|
|
|
|
readPktSize[ceilLog2(size)]++;
|
|
|
|
readBursts++;
|
|
|
|
|
|
|
|
// First check write buffer to see if the data is already at
|
|
|
|
// the controller
|
|
|
|
bool foundInWrQ = false;
|
2015-07-03 16:14:45 +02:00
|
|
|
Addr burst_addr = burstAlign(addr);
|
|
|
|
// if the burst address is not present then there is no need
|
|
|
|
// looking any further
|
|
|
|
if (isInWriteQueue.find(burst_addr) != isInWriteQueue.end()) {
|
|
|
|
for (const auto& p : writeQueue) {
|
|
|
|
// check if the read is subsumed in the write queue
|
|
|
|
// packet we are looking at
|
|
|
|
if (p->addr <= addr && (addr + size) <= (p->addr + p->size)) {
|
|
|
|
foundInWrQ = true;
|
|
|
|
servicedByWrQ++;
|
|
|
|
pktsServicedByWrQ++;
|
|
|
|
DPRINTF(DRAM, "Read to addr %lld with size %d serviced by "
|
|
|
|
"write queue\n", addr, size);
|
|
|
|
bytesReadWrQ += burstSize;
|
|
|
|
break;
|
|
|
|
}
|
2013-08-19 09:52:30 +02:00
|
|
|
}
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
// If not found in the write q, make a DRAM packet and
|
|
|
|
// push it onto the read queue
|
|
|
|
if (!foundInWrQ) {
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
// Make the burst helper for split packets
|
|
|
|
if (pktCount > 1 && burst_helper == NULL) {
|
|
|
|
DPRINTF(DRAM, "Read to addr %lld translates to %d "
|
|
|
|
"dram requests\n", pkt->getAddr(), pktCount);
|
|
|
|
burst_helper = new BurstHelper(pktCount);
|
|
|
|
}
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-11-01 16:56:19 +01:00
|
|
|
DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true);
|
2013-08-19 09:52:30 +02:00
|
|
|
dram_pkt->burstHelper = burst_helper;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
assert(!readQueueFull(1));
|
|
|
|
rdQLenPdf[readQueue.size() + respQueue.size()]++;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
DPRINTF(DRAM, "Adding to read queue\n");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
readQueue.push_back(dram_pkt);
|
|
|
|
|
|
|
|
// Update stats
|
|
|
|
avgRdQLen = readQueue.size() + respQueue.size();
|
|
|
|
}
|
|
|
|
|
|
|
|
// Starting address of next dram pkt (aligend to burstSize boundary)
|
|
|
|
addr = (addr | (burstSize - 1)) + 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
// If all packets are serviced by write queue, we send the repsonse back
|
|
|
|
if (pktsServicedByWrQ == pktCount) {
|
|
|
|
accessAndRespond(pkt, frontendLatency);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Update how many split packets are serviced by write queue
|
|
|
|
if (burst_helper != NULL)
|
|
|
|
burst_helper->burstsServiced = pktsServicedByWrQ;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// If we are not already scheduled to get a request out of the
|
|
|
|
// queue, do so now
|
|
|
|
if (!nextReqEvent.scheduled()) {
|
2013-03-01 19:20:24 +01:00
|
|
|
DPRINTF(DRAM, "Request scheduled immediately\n");
|
|
|
|
schedule(nextReqEvent, curTick());
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
// only add to the write queue here. whenever the request is
|
|
|
|
// eventually done, set the readyTime, and call schedule()
|
|
|
|
assert(pkt->isWrite());
|
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
// if the request size is larger than burst size, the pkt is split into
|
|
|
|
// multiple DRAM packets
|
|
|
|
Addr addr = pkt->getAddr();
|
|
|
|
for (int cnt = 0; cnt < pktCount; ++cnt) {
|
|
|
|
unsigned size = std::min((addr | (burstSize - 1)) + 1,
|
|
|
|
pkt->getAddr() + pkt->getSize()) - addr;
|
|
|
|
writePktSize[ceilLog2(size)]++;
|
|
|
|
writeBursts++;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-08-19 09:52:31 +02:00
|
|
|
// see if we can merge with an existing item in the write
|
2015-07-03 16:14:45 +02:00
|
|
|
// queue and keep track of whether we have merged or not
|
|
|
|
bool merged = isInWriteQueue.find(burstAlign(addr)) !=
|
|
|
|
isInWriteQueue.end();
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-08-19 09:52:31 +02:00
|
|
|
// if the item was not merged we need to create a new write
|
|
|
|
// and enqueue it
|
|
|
|
if (!merged) {
|
2013-11-01 16:56:19 +01:00
|
|
|
DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-08-19 09:52:31 +02:00
|
|
|
assert(writeQueue.size() < writeBufferSize);
|
|
|
|
wrQLenPdf[writeQueue.size()]++;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-08-19 09:52:31 +02:00
|
|
|
DPRINTF(DRAM, "Adding to write queue\n");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-08-19 09:52:31 +02:00
|
|
|
writeQueue.push_back(dram_pkt);
|
2015-07-03 16:14:45 +02:00
|
|
|
isInWriteQueue.insert(burstAlign(addr));
|
|
|
|
assert(writeQueue.size() == isInWriteQueue.size());
|
2013-08-19 09:52:30 +02:00
|
|
|
|
2013-08-19 09:52:31 +02:00
|
|
|
// Update stats
|
|
|
|
avgWrQLen = writeQueue.size();
|
2013-11-01 16:56:31 +01:00
|
|
|
} else {
|
2015-07-03 16:14:45 +02:00
|
|
|
DPRINTF(DRAM, "Merging write burst with existing queue entry\n");
|
|
|
|
|
2013-11-01 16:56:31 +01:00
|
|
|
// keep track of the fact that this burst effectively
|
|
|
|
// disappeared as it was merged with an existing one
|
|
|
|
mergedWrBursts++;
|
2013-08-19 09:52:31 +02:00
|
|
|
}
|
2013-08-19 09:52:30 +02:00
|
|
|
|
|
|
|
// Starting address of next dram pkt (aligend to burstSize boundary)
|
|
|
|
addr = (addr | (burstSize - 1)) + 1;
|
|
|
|
}
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
// we do not wait for the writes to be send to the actual memory,
|
|
|
|
// but instead take responsibility for the consistency here and
|
|
|
|
// snoop the write queue for any upcoming reads
|
2013-08-19 09:52:30 +02:00
|
|
|
// @todo, if a pkt size is larger than burst size, we might need a
|
|
|
|
// different front end latency
|
2013-05-30 18:54:12 +02:00
|
|
|
accessAndRespond(pkt, frontendLatency);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// If we are not already scheduled to get a request out of the
|
|
|
|
// queue, do so now
|
|
|
|
if (!nextReqEvent.scheduled()) {
|
|
|
|
DPRINTF(DRAM, "Request scheduled immediately\n");
|
|
|
|
schedule(nextReqEvent, curTick());
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::printQs() const {
|
2012-09-21 17:48:13 +02:00
|
|
|
DPRINTF(DRAM, "===READ QUEUE===\n\n");
|
2013-08-19 09:52:32 +02:00
|
|
|
for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) {
|
2012-09-21 17:48:13 +02:00
|
|
|
DPRINTF(DRAM, "Read %lu\n", (*i)->addr);
|
|
|
|
}
|
|
|
|
DPRINTF(DRAM, "\n===RESP QUEUE===\n\n");
|
2013-08-19 09:52:32 +02:00
|
|
|
for (auto i = respQueue.begin() ; i != respQueue.end() ; ++i) {
|
2012-09-21 17:48:13 +02:00
|
|
|
DPRINTF(DRAM, "Response %lu\n", (*i)->addr);
|
|
|
|
}
|
|
|
|
DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n");
|
2013-08-19 09:52:32 +02:00
|
|
|
for (auto i = writeQueue.begin() ; i != writeQueue.end() ; ++i) {
|
2012-09-21 17:48:13 +02:00
|
|
|
DPRINTF(DRAM, "Write %lu\n", (*i)->addr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::recvTimingReq(PacketPtr pkt)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
2012-11-02 17:50:16 +01:00
|
|
|
/// @todo temporary hack to deal with memory corruption issues until
|
|
|
|
/// 4-phase transactions are complete
|
|
|
|
for (int x = 0; x < pendingDelete.size(); x++)
|
|
|
|
delete pendingDelete[x];
|
|
|
|
pendingDelete.clear();
|
|
|
|
|
2012-09-21 17:48:13 +02:00
|
|
|
// This is where we enter from the outside world
|
2013-03-01 19:20:24 +01:00
|
|
|
DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n",
|
2013-08-19 09:52:30 +02:00
|
|
|
pkt->cmdString(), pkt->getAddr(), pkt->getSize());
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2015-07-03 16:14:37 +02:00
|
|
|
// simply drop inhibited packets and clean evictions
|
|
|
|
if (pkt->memInhibitAsserted() ||
|
|
|
|
pkt->cmd == MemCmd::CleanEvict) {
|
|
|
|
DPRINTF(DRAM, "Inhibited packet or clean evict -- Dropping it now\n");
|
2013-03-01 19:20:24 +01:00
|
|
|
pendingDelete.push_back(pkt);
|
|
|
|
return true;
|
|
|
|
}
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
// Calc avg gap between requests
|
|
|
|
if (prevArrival != 0) {
|
|
|
|
totGap += curTick() - prevArrival;
|
|
|
|
}
|
|
|
|
prevArrival = curTick();
|
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
|
|
|
|
// Find out how many dram packets a pkt translates to
|
|
|
|
// If the burst size is equal or larger than the pkt size, then a pkt
|
|
|
|
// translates to only one dram packet. Otherwise, a pkt translates to
|
|
|
|
// multiple dram packets
|
2012-09-21 17:48:13 +02:00
|
|
|
unsigned size = pkt->getSize();
|
2013-08-19 09:52:30 +02:00
|
|
|
unsigned offset = pkt->getAddr() & (burstSize - 1);
|
|
|
|
unsigned int dram_pkt_count = divCeil(offset + size, burstSize);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
// check local buffers and do not accept if full
|
|
|
|
if (pkt->isRead()) {
|
2013-03-01 19:20:24 +01:00
|
|
|
assert(size != 0);
|
2013-08-19 09:52:30 +02:00
|
|
|
if (readQueueFull(dram_pkt_count)) {
|
2013-03-01 19:20:24 +01:00
|
|
|
DPRINTF(DRAM, "Read queue full, not accepting\n");
|
2012-09-21 17:48:13 +02:00
|
|
|
// remember that we have to retry this port
|
|
|
|
retryRdReq = true;
|
|
|
|
numRdRetry++;
|
|
|
|
return false;
|
|
|
|
} else {
|
2013-08-19 09:52:30 +02:00
|
|
|
addToReadQueue(pkt, dram_pkt_count);
|
2012-09-21 17:48:13 +02:00
|
|
|
readReqs++;
|
2013-11-01 16:56:31 +01:00
|
|
|
bytesReadSys += size;
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
} else if (pkt->isWrite()) {
|
2013-03-01 19:20:24 +01:00
|
|
|
assert(size != 0);
|
2013-08-19 09:52:30 +02:00
|
|
|
if (writeQueueFull(dram_pkt_count)) {
|
2013-03-01 19:20:24 +01:00
|
|
|
DPRINTF(DRAM, "Write queue full, not accepting\n");
|
2012-09-21 17:48:13 +02:00
|
|
|
// remember that we have to retry this port
|
|
|
|
retryWrReq = true;
|
|
|
|
numWrRetry++;
|
|
|
|
return false;
|
|
|
|
} else {
|
2013-08-19 09:52:30 +02:00
|
|
|
addToWriteQueue(pkt, dram_pkt_count);
|
2012-09-21 17:48:13 +02:00
|
|
|
writeReqs++;
|
2013-11-01 16:56:31 +01:00
|
|
|
bytesWrittenSys += size;
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
DPRINTF(DRAM,"Neither read nor write, ignore timing\n");
|
|
|
|
neitherReadNorWrite++;
|
2013-05-30 18:54:12 +02:00
|
|
|
accessAndRespond(pkt, 1);
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::processRespondEvent()
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
DPRINTF(DRAM,
|
|
|
|
"processRespondEvent(): Some req has reached its readyTime\n");
|
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
DRAMPacket* dram_pkt = respQueue.front();
|
|
|
|
|
|
|
|
if (dram_pkt->burstHelper) {
|
|
|
|
// it is a split packet
|
|
|
|
dram_pkt->burstHelper->burstsServiced++;
|
|
|
|
if (dram_pkt->burstHelper->burstsServiced ==
|
2014-03-23 16:12:06 +01:00
|
|
|
dram_pkt->burstHelper->burstCount) {
|
2013-08-19 09:52:30 +02:00
|
|
|
// we have now serviced all children packets of a system packet
|
|
|
|
// so we can now respond to the requester
|
|
|
|
// @todo we probably want to have a different front end and back
|
|
|
|
// end latency for split packets
|
|
|
|
accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency);
|
|
|
|
delete dram_pkt->burstHelper;
|
|
|
|
dram_pkt->burstHelper = NULL;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
// it is not a split packet
|
|
|
|
accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency);
|
|
|
|
}
|
|
|
|
|
|
|
|
delete respQueue.front();
|
|
|
|
respQueue.pop_front();
|
|
|
|
|
|
|
|
if (!respQueue.empty()) {
|
|
|
|
assert(respQueue.front()->readyTime >= curTick());
|
|
|
|
assert(!respondEvent.scheduled());
|
|
|
|
schedule(respondEvent, respQueue.front()->readyTime);
|
|
|
|
} else {
|
|
|
|
// if there is nothing left in any queue, signal a drain
|
|
|
|
if (writeQueue.empty() && readQueue.empty() &&
|
|
|
|
drainManager) {
|
2014-10-30 05:18:26 +01:00
|
|
|
DPRINTF(Drain, "DRAM controller done draining\n");
|
2013-08-19 09:52:30 +02:00
|
|
|
drainManager->signalDrainDone();
|
|
|
|
drainManager = NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// We have made a location in the queue available at this point,
|
|
|
|
// so if there is a read that was forced to wait, retry now
|
|
|
|
if (retryRdReq) {
|
|
|
|
retryRdReq = false;
|
2015-03-02 10:00:35 +01:00
|
|
|
port.sendRetryReq();
|
2013-08-19 09:52:30 +02:00
|
|
|
}
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
2014-12-23 15:31:18 +01:00
|
|
|
bool
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
DRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue, Tick extra_col_delay)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
2014-05-10 00:58:48 +02:00
|
|
|
// This method does the arbitration between requests. The chosen
|
|
|
|
// packet is simply moved to the head of the queue. The other
|
|
|
|
// methods know that this is the place to look. For example, with
|
|
|
|
// FCFS, this method does nothing
|
|
|
|
assert(!queue.empty());
|
|
|
|
|
2014-12-23 15:31:18 +01:00
|
|
|
// bool to indicate if a packet to an available rank is found
|
|
|
|
bool found_packet = false;
|
2014-05-10 00:58:48 +02:00
|
|
|
if (queue.size() == 1) {
|
2014-12-23 15:31:18 +01:00
|
|
|
DRAMPacket* dram_pkt = queue.front();
|
|
|
|
// available rank corresponds to state refresh idle
|
|
|
|
if (ranks[dram_pkt->rank]->isAvailable()) {
|
|
|
|
found_packet = true;
|
|
|
|
DPRINTF(DRAM, "Single request, going to a free rank\n");
|
|
|
|
} else {
|
|
|
|
DPRINTF(DRAM, "Single request, going to a busy rank\n");
|
|
|
|
}
|
|
|
|
return found_packet;
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
if (memSchedPolicy == Enums::fcfs) {
|
2014-12-23 15:31:18 +01:00
|
|
|
// check if there is a packet going to a free rank
|
|
|
|
for(auto i = queue.begin(); i != queue.end() ; ++i) {
|
|
|
|
DRAMPacket* dram_pkt = *i;
|
|
|
|
if (ranks[dram_pkt->rank]->isAvailable()) {
|
|
|
|
queue.erase(i);
|
|
|
|
queue.push_front(dram_pkt);
|
|
|
|
found_packet = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2012-09-21 17:48:13 +02:00
|
|
|
} else if (memSchedPolicy == Enums::frfcfs) {
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
found_packet = reorderQueue(queue, extra_col_delay);
|
2012-09-21 17:48:13 +02:00
|
|
|
} else
|
|
|
|
panic("No scheduling policy chosen\n");
|
2014-12-23 15:31:18 +01:00
|
|
|
return found_packet;
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
2014-12-23 15:31:18 +01:00
|
|
|
bool
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
DRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue, Tick extra_col_delay)
|
2013-11-01 16:56:27 +01:00
|
|
|
{
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
// Only determine this if needed
|
2013-11-01 16:56:27 +01:00
|
|
|
uint64_t earliest_banks = 0;
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
bool hidden_bank_prep = false;
|
2013-11-01 16:56:27 +01:00
|
|
|
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
// search for seamless row hits first, if no seamless row hit is
|
|
|
|
// found then determine if there are other packets that can be issued
|
|
|
|
// without incurring additional bus delay due to bank timing
|
|
|
|
// Will select closed rows first to enable more open row possibilies
|
|
|
|
// in future selections
|
|
|
|
bool found_hidden_bank = false;
|
|
|
|
|
|
|
|
// remember if we found a row hit, not seamless, but bank prepped
|
|
|
|
// and ready
|
|
|
|
bool found_prepped_pkt = false;
|
|
|
|
|
|
|
|
// if we have no row hit, prepped or not, and no seamless packet,
|
|
|
|
// just go for the earliest possible
|
2013-11-01 16:56:27 +01:00
|
|
|
bool found_earliest_pkt = false;
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
|
2014-12-23 15:31:18 +01:00
|
|
|
auto selected_pkt_it = queue.end();
|
2013-11-01 16:56:27 +01:00
|
|
|
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
// time we need to issue a column command to be seamless
|
|
|
|
const Tick min_col_at = std::max(busBusyUntil - tCL + extra_col_delay,
|
|
|
|
curTick());
|
|
|
|
|
2013-11-01 16:56:27 +01:00
|
|
|
for (auto i = queue.begin(); i != queue.end() ; ++i) {
|
|
|
|
DRAMPacket* dram_pkt = *i;
|
|
|
|
const Bank& bank = dram_pkt->bankRef;
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
|
|
|
|
// check if rank is available, if not, jump to the next packet
|
2014-12-23 15:31:18 +01:00
|
|
|
if (dram_pkt->rankRef.isAvailable()) {
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
// check if it is a row hit
|
2014-12-23 15:31:18 +01:00
|
|
|
if (bank.openRow == dram_pkt->row) {
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
// no additional rank-to-rank or same bank-group
|
|
|
|
// delays, or we switched read/write and might as well
|
|
|
|
// go for the row hit
|
|
|
|
if (bank.colAllowedAt <= min_col_at) {
|
|
|
|
// FCFS within the hits, giving priority to
|
|
|
|
// commands that can issue seamlessly, without
|
|
|
|
// additional delay, such as same rank accesses
|
|
|
|
// and/or different bank-group accesses
|
|
|
|
DPRINTF(DRAM, "Seamless row buffer hit\n");
|
2014-12-23 15:31:18 +01:00
|
|
|
selected_pkt_it = i;
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
// no need to look through the remaining queue entries
|
2014-12-23 15:31:18 +01:00
|
|
|
break;
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
} else if (!found_hidden_bank && !found_prepped_pkt) {
|
|
|
|
// if we did not find a packet to a closed row that can
|
|
|
|
// issue the bank commands without incurring delay, and
|
|
|
|
// did not yet find a packet to a prepped row, remember
|
|
|
|
// the current one
|
2014-12-23 15:31:18 +01:00
|
|
|
selected_pkt_it = i;
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
found_prepped_pkt = true;
|
|
|
|
DPRINTF(DRAM, "Prepped row buffer hit\n");
|
2014-12-23 15:31:18 +01:00
|
|
|
}
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
} else if (!found_earliest_pkt) {
|
|
|
|
// if we have not initialised the bank status, do it
|
|
|
|
// now, and only once per scheduling decisions
|
|
|
|
if (earliest_banks == 0) {
|
|
|
|
// determine entries with earliest bank delay
|
|
|
|
pair<uint64_t, bool> bankStatus =
|
|
|
|
minBankPrep(queue, min_col_at);
|
|
|
|
earliest_banks = bankStatus.first;
|
|
|
|
hidden_bank_prep = bankStatus.second;
|
|
|
|
}
|
|
|
|
|
|
|
|
// bank is amongst first available banks
|
|
|
|
// minBankPrep will give priority to packets that can
|
|
|
|
// issue seamlessly
|
|
|
|
if (bits(earliest_banks, dram_pkt->bankId, dram_pkt->bankId)) {
|
2014-12-23 15:31:18 +01:00
|
|
|
found_earliest_pkt = true;
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
found_hidden_bank = hidden_bank_prep;
|
|
|
|
|
|
|
|
// give priority to packets that can issue
|
|
|
|
// bank commands 'behind the scenes'
|
|
|
|
// any additional delay if any will be due to
|
|
|
|
// col-to-col command requirements
|
|
|
|
if (hidden_bank_prep || !found_prepped_pkt)
|
|
|
|
selected_pkt_it = i;
|
2014-12-23 15:31:18 +01:00
|
|
|
}
|
2013-11-01 16:56:27 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-12-23 15:31:18 +01:00
|
|
|
if (selected_pkt_it != queue.end()) {
|
|
|
|
DRAMPacket* selected_pkt = *selected_pkt_it;
|
|
|
|
queue.erase(selected_pkt_it);
|
|
|
|
queue.push_front(selected_pkt);
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
return true;
|
2014-12-23 15:31:18 +01:00
|
|
|
}
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
|
|
|
|
return false;
|
2013-11-01 16:56:27 +01:00
|
|
|
}
|
|
|
|
|
2012-09-21 17:48:13 +02:00
|
|
|
void
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr());
|
|
|
|
|
|
|
|
bool needsResponse = pkt->needsResponse();
|
|
|
|
// do the actual memory access which also turns the packet into a
|
|
|
|
// response
|
|
|
|
access(pkt);
|
|
|
|
|
|
|
|
// turn packet around to go back to requester if response expected
|
|
|
|
if (needsResponse) {
|
|
|
|
// access already turned the packet into a response
|
|
|
|
assert(pkt->isResponse());
|
2015-03-02 10:00:48 +01:00
|
|
|
// response_time consumes the static latency and is charged also
|
|
|
|
// with headerDelay that takes into account the delay provided by
|
|
|
|
// the xbar and also the payloadDelay that takes into account the
|
|
|
|
// number of data beats.
|
|
|
|
Tick response_time = curTick() + static_latency + pkt->headerDelay +
|
|
|
|
pkt->payloadDelay;
|
|
|
|
// Here we reset the timing of the packet before sending it out.
|
2015-02-11 16:23:47 +01:00
|
|
|
pkt->headerDelay = pkt->payloadDelay = 0;
|
2013-02-19 11:56:06 +01:00
|
|
|
|
2013-05-30 18:54:12 +02:00
|
|
|
// queue the packet in the response queue to be sent out after
|
|
|
|
// the static latency has passed
|
2015-03-02 10:00:48 +01:00
|
|
|
port.schedTimingResp(pkt, response_time);
|
2012-09-21 17:48:13 +02:00
|
|
|
} else {
|
2013-03-18 10:22:45 +01:00
|
|
|
// @todo the packet is going to be deleted, and the DRAMPacket
|
|
|
|
// is still having a pointer to it
|
|
|
|
pendingDelete.push_back(pkt);
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
DPRINTF(DRAM, "Done\n");
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2013-01-31 13:49:14 +01:00
|
|
|
void
|
2014-12-23 15:31:18 +01:00
|
|
|
DRAMCtrl::activateBank(Rank& rank_ref, Bank& bank_ref,
|
|
|
|
Tick act_tick, uint32_t row)
|
2013-01-31 13:49:14 +01:00
|
|
|
{
|
2014-12-23 15:31:18 +01:00
|
|
|
assert(rank_ref.actTicks.size() == activationLimit);
|
2013-01-31 13:49:14 +01:00
|
|
|
|
|
|
|
DPRINTF(DRAM, "Activate at tick %d\n", act_tick);
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// update the open row
|
2014-12-23 15:31:18 +01:00
|
|
|
assert(bank_ref.openRow == Bank::NO_ROW);
|
|
|
|
bank_ref.openRow = row;
|
2014-05-10 00:58:48 +02:00
|
|
|
|
|
|
|
// start counting anew, this covers both the case when we
|
|
|
|
// auto-precharged, and when this access is forced to
|
|
|
|
// precharge
|
2014-12-23 15:31:18 +01:00
|
|
|
bank_ref.bytesAccessed = 0;
|
|
|
|
bank_ref.rowAccesses = 0;
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-12-23 15:31:18 +01:00
|
|
|
++rank_ref.numBanksActive;
|
|
|
|
assert(rank_ref.numBanksActive <= banksPerRank);
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-06-30 19:56:03 +02:00
|
|
|
DPRINTF(DRAM, "Activate bank %d, rank %d at tick %lld, now got %d active\n",
|
2014-12-23 15:31:18 +01:00
|
|
|
bank_ref.bank, rank_ref.rank, act_tick,
|
|
|
|
ranks[rank_ref.rank]->numBanksActive);
|
2014-06-30 19:56:03 +02:00
|
|
|
|
2014-12-23 15:31:18 +01:00
|
|
|
rank_ref.power.powerlib.doCommand(MemCommand::ACT, bank_ref.bank,
|
|
|
|
divCeil(act_tick, tCK) -
|
|
|
|
timeStampOffset);
|
2014-07-29 18:22:44 +02:00
|
|
|
|
|
|
|
DPRINTF(DRAMPower, "%llu,ACT,%d,%d\n", divCeil(act_tick, tCK) -
|
2014-12-23 15:31:18 +01:00
|
|
|
timeStampOffset, bank_ref.bank, rank_ref.rank);
|
2013-11-01 16:56:28 +01:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// The next access has to respect tRAS for this bank
|
2014-12-23 15:31:18 +01:00
|
|
|
bank_ref.preAllowedAt = act_tick + tRAS;
|
2014-05-10 00:58:48 +02:00
|
|
|
|
|
|
|
// Respect the row-to-column command delay
|
2014-12-23 15:31:18 +01:00
|
|
|
bank_ref.colAllowedAt = std::max(act_tick + tRCD, bank_ref.colAllowedAt);
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2013-11-01 16:56:24 +01:00
|
|
|
// start by enforcing tRRD
|
|
|
|
for(int i = 0; i < banksPerRank; i++) {
|
2014-05-10 00:58:48 +02:00
|
|
|
// next activate to any bank in this rank must not happen
|
|
|
|
// before tRRD
|
2014-12-23 15:31:18 +01:00
|
|
|
if (bankGroupArch && (bank_ref.bankgr == rank_ref.banks[i].bankgr)) {
|
2014-09-20 23:18:21 +02:00
|
|
|
// bank group architecture requires longer delays between
|
|
|
|
// ACT commands within the same bank group. Use tRRD_L
|
|
|
|
// in this case
|
2014-12-23 15:31:18 +01:00
|
|
|
rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD_L,
|
|
|
|
rank_ref.banks[i].actAllowedAt);
|
2014-09-20 23:18:21 +02:00
|
|
|
} else {
|
|
|
|
// use shorter tRRD value when either
|
|
|
|
// 1) bank group architecture is not supportted
|
|
|
|
// 2) bank is in a different bank group
|
2014-12-23 15:31:18 +01:00
|
|
|
rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD,
|
|
|
|
rank_ref.banks[i].actAllowedAt);
|
2014-09-20 23:18:21 +02:00
|
|
|
}
|
2013-11-01 16:56:24 +01:00
|
|
|
}
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2013-11-01 16:56:24 +01:00
|
|
|
// next, we deal with tXAW, if the activation limit is disabled
|
2014-10-21 00:03:55 +02:00
|
|
|
// then we directly schedule an activate power event
|
2014-12-23 15:31:18 +01:00
|
|
|
if (!rank_ref.actTicks.empty()) {
|
2014-10-21 00:03:55 +02:00
|
|
|
// sanity check
|
2014-12-23 15:31:18 +01:00
|
|
|
if (rank_ref.actTicks.back() &&
|
|
|
|
(act_tick - rank_ref.actTicks.back()) < tXAW) {
|
2014-10-21 00:03:55 +02:00
|
|
|
panic("Got %d activates in window %d (%llu - %llu) which "
|
|
|
|
"is smaller than %llu\n", activationLimit, act_tick -
|
2014-12-23 15:31:18 +01:00
|
|
|
rank_ref.actTicks.back(), act_tick,
|
|
|
|
rank_ref.actTicks.back(), tXAW);
|
2014-10-21 00:03:55 +02:00
|
|
|
}
|
2013-01-31 13:49:14 +01:00
|
|
|
|
2014-10-21 00:03:55 +02:00
|
|
|
// shift the times used for the book keeping, the last element
|
|
|
|
// (highest index) is the oldest one and hence the lowest value
|
2014-12-23 15:31:18 +01:00
|
|
|
rank_ref.actTicks.pop_back();
|
2014-10-21 00:03:55 +02:00
|
|
|
|
|
|
|
// record an new activation (in the future)
|
2014-12-23 15:31:18 +01:00
|
|
|
rank_ref.actTicks.push_front(act_tick);
|
2014-10-21 00:03:55 +02:00
|
|
|
|
|
|
|
// cannot activate more than X times in time window tXAW, push the
|
|
|
|
// next one (the X + 1'st activate) to be tXAW away from the
|
|
|
|
// oldest in our window of X
|
2014-12-23 15:31:18 +01:00
|
|
|
if (rank_ref.actTicks.back() &&
|
|
|
|
(act_tick - rank_ref.actTicks.back()) < tXAW) {
|
2014-10-21 00:03:55 +02:00
|
|
|
DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate "
|
|
|
|
"no earlier than %llu\n", activationLimit,
|
2014-12-23 15:31:18 +01:00
|
|
|
rank_ref.actTicks.back() + tXAW);
|
2013-01-31 13:49:14 +01:00
|
|
|
for(int j = 0; j < banksPerRank; j++)
|
|
|
|
// next activate must not happen before end of window
|
2014-12-23 15:31:18 +01:00
|
|
|
rank_ref.banks[j].actAllowedAt =
|
|
|
|
std::max(rank_ref.actTicks.back() + tXAW,
|
|
|
|
rank_ref.banks[j].actAllowedAt);
|
2014-10-21 00:03:55 +02:00
|
|
|
}
|
2013-01-31 13:49:14 +01:00
|
|
|
}
|
2014-05-10 00:58:48 +02:00
|
|
|
|
|
|
|
// at the point when this activate takes place, make sure we
|
|
|
|
// transition to the active power state
|
2014-12-23 15:31:18 +01:00
|
|
|
if (!rank_ref.activateEvent.scheduled())
|
|
|
|
schedule(rank_ref.activateEvent, act_tick);
|
|
|
|
else if (rank_ref.activateEvent.when() > act_tick)
|
2014-05-10 00:58:48 +02:00
|
|
|
// move it sooner in time
|
2014-12-23 15:31:18 +01:00
|
|
|
reschedule(rank_ref.activateEvent, act_tick);
|
2013-01-31 13:49:14 +01:00
|
|
|
}
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
void
|
2014-12-23 15:31:18 +01:00
|
|
|
DRAMCtrl::prechargeBank(Rank& rank_ref, Bank& bank, Tick pre_at, bool trace)
|
2014-05-10 00:58:48 +02:00
|
|
|
{
|
|
|
|
// make sure the bank has an open row
|
|
|
|
assert(bank.openRow != Bank::NO_ROW);
|
|
|
|
|
|
|
|
// sample the bytes per activate here since we are closing
|
|
|
|
// the page
|
|
|
|
bytesPerActivate.sample(bank.bytesAccessed);
|
|
|
|
|
|
|
|
bank.openRow = Bank::NO_ROW;
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// no precharge allowed before this one
|
|
|
|
bank.preAllowedAt = pre_at;
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
Tick pre_done_at = pre_at + tRP;
|
|
|
|
|
|
|
|
bank.actAllowedAt = std::max(bank.actAllowedAt, pre_done_at);
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-12-23 15:31:18 +01:00
|
|
|
assert(rank_ref.numBanksActive != 0);
|
|
|
|
--rank_ref.numBanksActive;
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-06-30 19:56:03 +02:00
|
|
|
DPRINTF(DRAM, "Precharging bank %d, rank %d at tick %lld, now got "
|
2014-12-23 15:31:18 +01:00
|
|
|
"%d active\n", bank.bank, rank_ref.rank, pre_at,
|
|
|
|
rank_ref.numBanksActive);
|
2014-06-30 19:56:03 +02:00
|
|
|
|
2014-07-29 18:22:44 +02:00
|
|
|
if (trace) {
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-12-23 15:31:18 +01:00
|
|
|
rank_ref.power.powerlib.doCommand(MemCommand::PRE, bank.bank,
|
2014-07-29 18:22:44 +02:00
|
|
|
divCeil(pre_at, tCK) -
|
|
|
|
timeStampOffset);
|
|
|
|
DPRINTF(DRAMPower, "%llu,PRE,%d,%d\n", divCeil(pre_at, tCK) -
|
2014-12-23 15:31:18 +01:00
|
|
|
timeStampOffset, bank.bank, rank_ref.rank);
|
2014-07-29 18:22:44 +02:00
|
|
|
}
|
2014-05-10 00:58:48 +02:00
|
|
|
// if we look at the current number of active banks we might be
|
|
|
|
// tempted to think the DRAM is now idle, however this can be
|
|
|
|
// undone by an activate that is scheduled to happen before we
|
|
|
|
// would have reached the idle state, so schedule an event and
|
|
|
|
// rather check once we actually make it to the point in time when
|
|
|
|
// the (last) precharge takes place
|
2014-12-23 15:31:18 +01:00
|
|
|
if (!rank_ref.prechargeEvent.scheduled())
|
|
|
|
schedule(rank_ref.prechargeEvent, pre_done_at);
|
|
|
|
else if (rank_ref.prechargeEvent.when() < pre_done_at)
|
|
|
|
reschedule(rank_ref.prechargeEvent, pre_done_at);
|
2014-05-10 00:58:48 +02:00
|
|
|
}
|
|
|
|
|
2012-09-21 17:48:13 +02:00
|
|
|
void
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n",
|
|
|
|
dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row);
|
|
|
|
|
2014-12-23 15:31:18 +01:00
|
|
|
// get the rank
|
|
|
|
Rank& rank = dram_pkt->rankRef;
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// get the bank
|
|
|
|
Bank& bank = dram_pkt->bankRef;
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// for the state we need to track if it is a row hit or not
|
|
|
|
bool row_hit = true;
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// respect any constraints on the command (e.g. tRCD or tCCD)
|
|
|
|
Tick cmd_at = std::max(bank.colAllowedAt, curTick());
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// Determine the access latency and update the bank state
|
|
|
|
if (bank.openRow == dram_pkt->row) {
|
|
|
|
// nothing to do
|
2014-05-10 00:58:48 +02:00
|
|
|
} else {
|
2014-05-10 00:58:48 +02:00
|
|
|
row_hit = false;
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// If there is a page open, precharge it.
|
|
|
|
if (bank.openRow != Bank::NO_ROW) {
|
2014-12-23 15:31:18 +01:00
|
|
|
prechargeBank(rank, bank, std::max(bank.preAllowedAt, curTick()));
|
2013-01-31 13:49:14 +01:00
|
|
|
}
|
2013-11-01 16:56:26 +01:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// next we need to account for the delay in activating the
|
|
|
|
// page
|
|
|
|
Tick act_tick = std::max(bank.actAllowedAt, curTick());
|
2014-03-23 16:12:03 +01:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// Record the activation and deal with all the global timing
|
|
|
|
// constraints caused be a new activation (tRRD and tXAW)
|
2014-12-23 15:31:18 +01:00
|
|
|
activateBank(rank, bank, act_tick, dram_pkt->row);
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// issue the command as early as possible
|
|
|
|
cmd_at = bank.colAllowedAt;
|
2014-05-10 00:58:48 +02:00
|
|
|
}
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// we need to wait until the bus is available before we can issue
|
|
|
|
// the command
|
|
|
|
cmd_at = std::max(cmd_at, busBusyUntil - tCL);
|
|
|
|
|
|
|
|
// update the packet ready time
|
|
|
|
dram_pkt->readyTime = cmd_at + tCL + tBURST;
|
|
|
|
|
|
|
|
// only one burst can use the bus at any one point in time
|
|
|
|
assert(dram_pkt->readyTime - busBusyUntil >= tBURST);
|
|
|
|
|
2014-09-20 23:18:21 +02:00
|
|
|
// update the time for the next read/write burst for each
|
|
|
|
// bank (add a max with tCCD/tCCD_L here)
|
|
|
|
Tick cmd_dly;
|
|
|
|
for(int j = 0; j < ranksPerChannel; j++) {
|
|
|
|
for(int i = 0; i < banksPerRank; i++) {
|
|
|
|
// next burst to same bank group in this rank must not happen
|
|
|
|
// before tCCD_L. Different bank group timing requirement is
|
|
|
|
// tBURST; Add tCS for different ranks
|
|
|
|
if (dram_pkt->rank == j) {
|
2014-12-23 15:31:18 +01:00
|
|
|
if (bankGroupArch &&
|
|
|
|
(bank.bankgr == ranks[j]->banks[i].bankgr)) {
|
2014-09-20 23:18:21 +02:00
|
|
|
// bank group architecture requires longer delays between
|
|
|
|
// RD/WR burst commands to the same bank group.
|
|
|
|
// Use tCCD_L in this case
|
|
|
|
cmd_dly = tCCD_L;
|
|
|
|
} else {
|
|
|
|
// use tBURST (equivalent to tCCD_S), the shorter
|
|
|
|
// cas-to-cas delay value, when either:
|
|
|
|
// 1) bank group architecture is not supportted
|
|
|
|
// 2) bank is in a different bank group
|
|
|
|
cmd_dly = tBURST;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
// different rank is by default in a different bank group
|
|
|
|
// use tBURST (equivalent to tCCD_S), which is the shorter
|
|
|
|
// cas-to-cas delay in this case
|
|
|
|
// Add tCS to account for rank-to-rank bus delay requirements
|
|
|
|
cmd_dly = tBURST + tCS;
|
|
|
|
}
|
2014-12-23 15:31:18 +01:00
|
|
|
ranks[j]->banks[i].colAllowedAt = std::max(cmd_at + cmd_dly,
|
|
|
|
ranks[j]->banks[i].colAllowedAt);
|
2014-09-20 23:18:21 +02:00
|
|
|
}
|
|
|
|
}
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-09-20 23:17:57 +02:00
|
|
|
// Save rank of current access
|
|
|
|
activeRank = dram_pkt->rank;
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// If this is a write, we also need to respect the write recovery
|
|
|
|
// time before a precharge, in the case of a read, respect the
|
|
|
|
// read to precharge constraint
|
|
|
|
bank.preAllowedAt = std::max(bank.preAllowedAt,
|
|
|
|
dram_pkt->isRead ? cmd_at + tRTP :
|
|
|
|
dram_pkt->readyTime + tWR);
|
2014-03-23 16:12:05 +01:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// increment the bytes accessed and the accesses per row
|
|
|
|
bank.bytesAccessed += burstSize;
|
|
|
|
++bank.rowAccesses;
|
|
|
|
|
|
|
|
// if we reached the max, then issue with an auto-precharge
|
|
|
|
bool auto_precharge = pageMgmt == Enums::close ||
|
|
|
|
bank.rowAccesses == maxAccessesPerRow;
|
|
|
|
|
|
|
|
// if we did not hit the limit, we might still want to
|
|
|
|
// auto-precharge
|
|
|
|
if (!auto_precharge &&
|
|
|
|
(pageMgmt == Enums::open_adaptive ||
|
|
|
|
pageMgmt == Enums::close_adaptive)) {
|
|
|
|
// a twist on the open and close page policies:
|
|
|
|
// 1) open_adaptive page policy does not blindly keep the
|
|
|
|
// page open, but close it if there are no row hits, and there
|
|
|
|
// are bank conflicts in the queue
|
|
|
|
// 2) close_adaptive page policy does not blindly close the
|
|
|
|
// page, but closes it only if there are no row hits in the queue.
|
|
|
|
// In this case, only force an auto precharge when there
|
|
|
|
// are no same page hits in the queue
|
|
|
|
bool got_more_hits = false;
|
|
|
|
bool got_bank_conflict = false;
|
|
|
|
|
|
|
|
// either look at the read queue or write queue
|
|
|
|
const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue :
|
|
|
|
writeQueue;
|
|
|
|
auto p = queue.begin();
|
|
|
|
// make sure we are not considering the packet that we are
|
|
|
|
// currently dealing with (which is the head of the queue)
|
|
|
|
++p;
|
|
|
|
|
2015-04-30 05:35:22 +02:00
|
|
|
// keep on looking until we find a hit or reach the end of the queue
|
|
|
|
// 1) if a hit is found, then both open and close adaptive policies keep
|
|
|
|
// the page open
|
|
|
|
// 2) if no hit is found, got_bank_conflict is set to true if a bank
|
|
|
|
// conflict request is waiting in the queue
|
|
|
|
while (!got_more_hits && p != queue.end()) {
|
2014-05-10 00:58:48 +02:00
|
|
|
bool same_rank_bank = (dram_pkt->rank == (*p)->rank) &&
|
|
|
|
(dram_pkt->bank == (*p)->bank);
|
|
|
|
bool same_row = dram_pkt->row == (*p)->row;
|
|
|
|
got_more_hits |= same_rank_bank && same_row;
|
|
|
|
got_bank_conflict |= same_rank_bank && !same_row;
|
|
|
|
++p;
|
2013-11-01 16:56:26 +01:00
|
|
|
}
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// auto pre-charge when either
|
|
|
|
// 1) open_adaptive policy, we have not got any more hits, and
|
|
|
|
// have a bank conflict
|
|
|
|
// 2) close_adaptive policy and we have not got any more hits
|
|
|
|
auto_precharge = !got_more_hits &&
|
|
|
|
(got_bank_conflict || pageMgmt == Enums::close_adaptive);
|
|
|
|
}
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-06-30 19:56:03 +02:00
|
|
|
// DRAMPower trace command to be written
|
|
|
|
std::string mem_cmd = dram_pkt->isRead ? "RD" : "WR";
|
|
|
|
|
2014-07-29 18:22:44 +02:00
|
|
|
// MemCommand required for DRAMPower library
|
|
|
|
MemCommand::cmds command = (mem_cmd == "RD") ? MemCommand::RD :
|
|
|
|
MemCommand::WR;
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// if this access should use auto-precharge, then we are
|
|
|
|
// closing the row
|
|
|
|
if (auto_precharge) {
|
2014-07-29 18:22:44 +02:00
|
|
|
// if auto-precharge push a PRE command at the correct tick to the
|
|
|
|
// list used by DRAMPower library to calculate power
|
2014-12-23 15:31:18 +01:00
|
|
|
prechargeBank(rank, bank, std::max(curTick(), bank.preAllowedAt));
|
2013-11-01 16:56:16 +01:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId);
|
|
|
|
}
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2012-09-21 17:48:13 +02:00
|
|
|
// Update bus state
|
|
|
|
busBusyUntil = dram_pkt->readyTime;
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
DPRINTF(DRAM, "Access to %lld, ready at %lld bus busy until %lld.\n",
|
|
|
|
dram_pkt->addr, dram_pkt->readyTime, busBusyUntil);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2014-12-23 15:31:18 +01:00
|
|
|
dram_pkt->rankRef.power.powerlib.doCommand(command, dram_pkt->bank,
|
2014-07-29 18:22:44 +02:00
|
|
|
divCeil(cmd_at, tCK) -
|
|
|
|
timeStampOffset);
|
|
|
|
|
|
|
|
DPRINTF(DRAMPower, "%llu,%s,%d,%d\n", divCeil(cmd_at, tCK) -
|
|
|
|
timeStampOffset, mem_cmd, dram_pkt->bank, dram_pkt->rank);
|
2014-06-30 19:56:03 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// Update the minimum timing between the requests, this is a
|
|
|
|
// conservative estimate of when we have to schedule the next
|
|
|
|
// request to not introduce any unecessary bubbles. In most cases
|
|
|
|
// we will wake up sooner than we have to.
|
|
|
|
nextReqTime = busBusyUntil - (tRP + tRCD + tCL);
|
2013-11-01 16:56:25 +01:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// Update the stats and schedule the next request
|
2013-11-01 16:56:31 +01:00
|
|
|
if (dram_pkt->isRead) {
|
2014-03-23 16:12:14 +01:00
|
|
|
++readsThisTime;
|
2014-05-10 00:58:48 +02:00
|
|
|
if (row_hit)
|
2013-11-01 16:56:31 +01:00
|
|
|
readRowHits++;
|
|
|
|
bytesReadDRAM += burstSize;
|
|
|
|
perBankRdBursts[dram_pkt->bankId]++;
|
2014-05-10 00:58:48 +02:00
|
|
|
|
|
|
|
// Update latency stats
|
|
|
|
totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime;
|
|
|
|
totBusLat += tBURST;
|
2014-05-10 00:58:48 +02:00
|
|
|
totQLat += cmd_at - dram_pkt->entryTime;
|
2013-11-01 16:56:31 +01:00
|
|
|
} else {
|
2014-03-23 16:12:14 +01:00
|
|
|
++writesThisTime;
|
2014-05-10 00:58:48 +02:00
|
|
|
if (row_hit)
|
2013-11-01 16:56:31 +01:00
|
|
|
writeRowHits++;
|
|
|
|
bytesWritten += burstSize;
|
|
|
|
perBankWrBursts[dram_pkt->bankId]++;
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2014-05-10 00:58:48 +02:00
|
|
|
DRAMCtrl::processNextReqEvent()
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
2014-12-23 15:31:18 +01:00
|
|
|
int busyRanks = 0;
|
|
|
|
for (auto r : ranks) {
|
|
|
|
if (!r->isAvailable()) {
|
|
|
|
// rank is busy refreshing
|
|
|
|
busyRanks++;
|
|
|
|
|
|
|
|
// let the rank know that if it was waiting to drain, it
|
|
|
|
// is now done and ready to proceed
|
|
|
|
r->checkDrainDone();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (busyRanks == ranksPerChannel) {
|
|
|
|
// if all ranks are refreshing wait for them to finish
|
|
|
|
// and stall this state machine without taking any further
|
|
|
|
// action, and do not schedule a new nextReqEvent
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2014-09-20 23:17:57 +02:00
|
|
|
// pre-emptively set to false. Overwrite if in READ_TO_WRITE
|
|
|
|
// or WRITE_TO_READ state
|
|
|
|
bool switched_cmd_type = false;
|
2014-05-10 00:58:48 +02:00
|
|
|
if (busState == READ_TO_WRITE) {
|
|
|
|
DPRINTF(DRAM, "Switching to writes after %d reads with %d reads "
|
|
|
|
"waiting\n", readsThisTime, readQueue.size());
|
|
|
|
|
|
|
|
// sample and reset the read-related stats as we are now
|
|
|
|
// transitioning to writes, and all reads are done
|
|
|
|
rdPerTurnAround.sample(readsThisTime);
|
|
|
|
readsThisTime = 0;
|
|
|
|
|
|
|
|
// now proceed to do the actual writes
|
|
|
|
busState = WRITE;
|
2014-09-20 23:17:57 +02:00
|
|
|
switched_cmd_type = true;
|
2014-05-10 00:58:48 +02:00
|
|
|
} else if (busState == WRITE_TO_READ) {
|
|
|
|
DPRINTF(DRAM, "Switching to reads after %d writes with %d writes "
|
|
|
|
"waiting\n", writesThisTime, writeQueue.size());
|
|
|
|
|
|
|
|
wrPerTurnAround.sample(writesThisTime);
|
|
|
|
writesThisTime = 0;
|
|
|
|
|
|
|
|
busState = READ;
|
2014-09-20 23:17:57 +02:00
|
|
|
switched_cmd_type = true;
|
2014-05-10 00:58:48 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
// when we get here it is either a read or a write
|
|
|
|
if (busState == READ) {
|
|
|
|
|
|
|
|
// track if we should switch or not
|
|
|
|
bool switch_to_writes = false;
|
|
|
|
|
|
|
|
if (readQueue.empty()) {
|
|
|
|
// In the case there is no read request to go next,
|
|
|
|
// trigger writes if we have passed the low threshold (or
|
|
|
|
// if we are draining)
|
|
|
|
if (!writeQueue.empty() &&
|
|
|
|
(drainManager || writeQueue.size() > writeLowThreshold)) {
|
|
|
|
|
|
|
|
switch_to_writes = true;
|
|
|
|
} else {
|
|
|
|
// check if we are drained
|
|
|
|
if (respQueue.empty () && drainManager) {
|
2014-10-30 05:18:26 +01:00
|
|
|
DPRINTF(Drain, "DRAM controller done draining\n");
|
2014-05-10 00:58:48 +02:00
|
|
|
drainManager->signalDrainDone();
|
|
|
|
drainManager = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
// nothing to do, not even any point in scheduling an
|
|
|
|
// event for the next request
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
} else {
|
2014-12-23 15:31:18 +01:00
|
|
|
// bool to check if there is a read to a free rank
|
|
|
|
bool found_read = false;
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// Figure out which read request goes next, and move it to the
|
|
|
|
// front of the read queue
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
// If we are changing command type, incorporate the minimum
|
|
|
|
// bus turnaround delay which will be tCS (different rank) case
|
|
|
|
found_read = chooseNext(readQueue,
|
|
|
|
switched_cmd_type ? tCS : 0);
|
2014-12-23 15:31:18 +01:00
|
|
|
|
|
|
|
// if no read to an available rank is found then return
|
|
|
|
// at this point. There could be writes to the available ranks
|
|
|
|
// which are above the required threshold. However, to
|
|
|
|
// avoid adding more complexity to the code, return and wait
|
|
|
|
// for a refresh event to kick things into action again.
|
|
|
|
if (!found_read)
|
|
|
|
return;
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
DRAMPacket* dram_pkt = readQueue.front();
|
2014-12-23 15:31:18 +01:00
|
|
|
assert(dram_pkt->rankRef.isAvailable());
|
2014-09-20 23:17:57 +02:00
|
|
|
// here we get a bit creative and shift the bus busy time not
|
|
|
|
// just the tWTR, but also a CAS latency to capture the fact
|
|
|
|
// that we are allowed to prepare a new bank, but not issue a
|
|
|
|
// read command until after tWTR, in essence we capture a
|
|
|
|
// bubble on the data bus that is tWTR + tCL
|
2014-09-20 23:18:21 +02:00
|
|
|
if (switched_cmd_type && dram_pkt->rank == activeRank) {
|
|
|
|
busBusyUntil += tWTR + tCL;
|
2014-09-20 23:17:57 +02:00
|
|
|
}
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
doDRAMAccess(dram_pkt);
|
2014-05-10 00:58:48 +02:00
|
|
|
|
|
|
|
// At this point we're done dealing with the request
|
2014-05-10 00:58:48 +02:00
|
|
|
readQueue.pop_front();
|
|
|
|
|
|
|
|
// sanity check
|
|
|
|
assert(dram_pkt->size <= burstSize);
|
|
|
|
assert(dram_pkt->readyTime >= curTick());
|
|
|
|
|
|
|
|
// Insert into response queue. It will be sent back to the
|
|
|
|
// requestor at its readyTime
|
|
|
|
if (respQueue.empty()) {
|
|
|
|
assert(!respondEvent.scheduled());
|
|
|
|
schedule(respondEvent, dram_pkt->readyTime);
|
|
|
|
} else {
|
|
|
|
assert(respQueue.back()->readyTime <= dram_pkt->readyTime);
|
|
|
|
assert(respondEvent.scheduled());
|
|
|
|
}
|
|
|
|
|
|
|
|
respQueue.push_back(dram_pkt);
|
2014-05-10 00:58:48 +02:00
|
|
|
|
|
|
|
// we have so many writes that we have to transition
|
|
|
|
if (writeQueue.size() > writeHighThreshold) {
|
|
|
|
switch_to_writes = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// switching to writes, either because the read queue is empty
|
|
|
|
// and the writes have passed the low threshold (or we are
|
|
|
|
// draining), or because the writes hit the hight threshold
|
|
|
|
if (switch_to_writes) {
|
|
|
|
// transition to writing
|
|
|
|
busState = READ_TO_WRITE;
|
|
|
|
}
|
2012-11-08 10:25:06 +01:00
|
|
|
} else {
|
2014-12-23 15:31:18 +01:00
|
|
|
// bool to check if write to free rank is found
|
|
|
|
bool found_write = false;
|
|
|
|
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
// If we are changing command type, incorporate the minimum
|
|
|
|
// bus turnaround delay
|
|
|
|
found_write = chooseNext(writeQueue,
|
|
|
|
switched_cmd_type ? std::min(tRTW, tCS) : 0);
|
2014-12-23 15:31:18 +01:00
|
|
|
|
|
|
|
// if no writes to an available rank are found then return.
|
|
|
|
// There could be reads to the available ranks. However, to avoid
|
|
|
|
// adding more complexity to the code, return at this point and wait
|
|
|
|
// for a refresh event to kick things into action again.
|
|
|
|
if (!found_write)
|
|
|
|
return;
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
DRAMPacket* dram_pkt = writeQueue.front();
|
2014-12-23 15:31:18 +01:00
|
|
|
assert(dram_pkt->rankRef.isAvailable());
|
2014-05-10 00:58:48 +02:00
|
|
|
// sanity check
|
|
|
|
assert(dram_pkt->size <= burstSize);
|
2014-09-20 23:17:57 +02:00
|
|
|
|
2014-09-20 23:18:21 +02:00
|
|
|
// add a bubble to the data bus, as defined by the
|
|
|
|
// tRTW when access is to the same rank as previous burst
|
|
|
|
// Different rank timing is handled with tCS, which is
|
|
|
|
// applied to colAllowedAt
|
|
|
|
if (switched_cmd_type && dram_pkt->rank == activeRank) {
|
|
|
|
busBusyUntil += tRTW;
|
2014-09-20 23:17:57 +02:00
|
|
|
}
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
doDRAMAccess(dram_pkt);
|
|
|
|
|
|
|
|
writeQueue.pop_front();
|
2015-07-03 16:14:45 +02:00
|
|
|
isInWriteQueue.erase(burstAlign(dram_pkt->addr));
|
2014-05-10 00:58:48 +02:00
|
|
|
delete dram_pkt;
|
|
|
|
|
|
|
|
// If we emptied the write queue, or got sufficiently below the
|
|
|
|
// threshold (using the minWritesPerSwitch as the hysteresis) and
|
|
|
|
// are not draining, or we have reads waiting and have done enough
|
|
|
|
// writes, then switch to reads.
|
|
|
|
if (writeQueue.empty() ||
|
|
|
|
(writeQueue.size() + minWritesPerSwitch < writeLowThreshold &&
|
|
|
|
!drainManager) ||
|
|
|
|
(!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) {
|
|
|
|
// turn the bus back around for reads again
|
|
|
|
busState = WRITE_TO_READ;
|
|
|
|
|
|
|
|
// note that the we switch back to reads also in the idle
|
|
|
|
// case, which eventually will check for any draining and
|
|
|
|
// also pause any further scheduling if there is really
|
|
|
|
// nothing to do
|
|
|
|
}
|
|
|
|
}
|
2014-12-23 15:31:18 +01:00
|
|
|
// It is possible that a refresh to another rank kicks things back into
|
|
|
|
// action before reaching this point.
|
|
|
|
if (!nextReqEvent.scheduled())
|
|
|
|
schedule(nextReqEvent, std::max(nextReqTime, curTick()));
|
2014-05-10 00:58:48 +02:00
|
|
|
|
|
|
|
// If there is space available and we have writes waiting then let
|
|
|
|
// them retry. This is done here to ensure that the retry does not
|
|
|
|
// cause a nextReqEvent to be scheduled before we do so as part of
|
|
|
|
// the next request processing
|
|
|
|
if (retryWrReq && writeQueue.size() < writeBufferSize) {
|
|
|
|
retryWrReq = false;
|
2015-03-02 10:00:35 +01:00
|
|
|
port.sendRetryReq();
|
2012-11-08 10:25:06 +01:00
|
|
|
}
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
pair<uint64_t, bool>
|
2014-09-20 23:17:57 +02:00
|
|
|
DRAMCtrl::minBankPrep(const deque<DRAMPacket*>& queue,
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
Tick min_col_at) const
|
2013-11-01 16:56:20 +01:00
|
|
|
{
|
|
|
|
uint64_t bank_mask = 0;
|
2014-05-10 00:58:48 +02:00
|
|
|
Tick min_act_at = MaxTick;
|
2013-11-01 16:56:20 +01:00
|
|
|
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
// latest Tick for which ACT can occur without incurring additoinal
|
|
|
|
// delay on the data bus
|
|
|
|
const Tick hidden_act_max = std::max(min_col_at - tRCD, curTick());
|
|
|
|
|
|
|
|
// Flag condition when burst can issue back-to-back with previous burst
|
|
|
|
bool found_seamless_bank = false;
|
2014-09-20 23:17:57 +02:00
|
|
|
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
// Flag condition when bank can be opened without incurring additional
|
|
|
|
// delay on the data bus
|
|
|
|
bool hidden_bank_prep = false;
|
2014-09-20 23:17:57 +02:00
|
|
|
|
|
|
|
// determine if we have queued transactions targetting the
|
2013-11-01 16:56:20 +01:00
|
|
|
// bank in question
|
|
|
|
vector<bool> got_waiting(ranksPerChannel * banksPerRank, false);
|
2014-12-23 15:31:18 +01:00
|
|
|
for (const auto& p : queue) {
|
|
|
|
if(p->rankRef.isAvailable())
|
|
|
|
got_waiting[p->bankId] = true;
|
2013-11-01 16:56:20 +01:00
|
|
|
}
|
|
|
|
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
// Find command with optimal bank timing
|
|
|
|
// Will prioritize commands that can issue seamlessly.
|
2013-11-01 16:56:20 +01:00
|
|
|
for (int i = 0; i < ranksPerChannel; i++) {
|
|
|
|
for (int j = 0; j < banksPerRank; j++) {
|
2014-12-23 15:31:18 +01:00
|
|
|
uint16_t bank_id = i * banksPerRank + j;
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2013-11-01 16:56:20 +01:00
|
|
|
// if we have waiting requests for the bank, and it is
|
|
|
|
// amongst the first available, update the mask
|
2014-05-10 00:58:48 +02:00
|
|
|
if (got_waiting[bank_id]) {
|
2014-12-23 15:31:18 +01:00
|
|
|
// make sure this rank is not currently refreshing.
|
|
|
|
assert(ranks[i]->isAvailable());
|
2014-05-10 00:58:48 +02:00
|
|
|
// simplistic approximation of when the bank can issue
|
|
|
|
// an activate, ignoring any rank-to-rank switching
|
2014-09-20 23:17:57 +02:00
|
|
|
// cost in this calculation
|
2014-12-23 15:31:18 +01:00
|
|
|
Tick act_at = ranks[i]->banks[j].openRow == Bank::NO_ROW ?
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
std::max(ranks[i]->banks[j].actAllowedAt, curTick()) :
|
2014-12-23 15:31:18 +01:00
|
|
|
std::max(ranks[i]->banks[j].preAllowedAt, curTick()) + tRP;
|
2014-05-10 00:58:48 +02:00
|
|
|
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
// When is the earliest the R/W burst can issue?
|
|
|
|
Tick col_at = std::max(ranks[i]->banks[j].colAllowedAt,
|
|
|
|
act_at + tRCD);
|
|
|
|
|
|
|
|
// bank can issue burst back-to-back (seamlessly) with
|
|
|
|
// previous burst
|
|
|
|
bool new_seamless_bank = col_at <= min_col_at;
|
|
|
|
|
|
|
|
// if we found a new seamless bank or we have no
|
|
|
|
// seamless banks, and got a bank with an earlier
|
|
|
|
// activate time, it should be added to the bit mask
|
|
|
|
if (new_seamless_bank ||
|
|
|
|
(!found_seamless_bank && act_at <= min_act_at)) {
|
|
|
|
// if we did not have a seamless bank before, and
|
|
|
|
// we do now, reset the bank mask, also reset it
|
|
|
|
// if we have not yet found a seamless bank and
|
|
|
|
// the activate time is smaller than what we have
|
|
|
|
// seen so far
|
|
|
|
if (!found_seamless_bank &&
|
|
|
|
(new_seamless_bank || act_at < min_act_at)) {
|
|
|
|
bank_mask = 0;
|
2014-09-20 23:17:57 +02:00
|
|
|
}
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
|
|
|
|
found_seamless_bank |= new_seamless_bank;
|
|
|
|
|
|
|
|
// ACT can occur 'behind the scenes'
|
|
|
|
hidden_bank_prep = act_at <= hidden_act_max;
|
|
|
|
|
|
|
|
// set the bit corresponding to the available bank
|
|
|
|
replaceBits(bank_mask, bank_id, bank_id, 1);
|
|
|
|
min_act_at = act_at;
|
2014-05-10 00:58:48 +02:00
|
|
|
}
|
2013-11-01 16:56:20 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2014-05-10 00:58:48 +02:00
|
|
|
|
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
2015-07-03 16:14:46 +02:00
|
|
|
return make_pair(bank_mask, hidden_bank_prep);
|
2013-11-01 16:56:20 +01:00
|
|
|
}
|
|
|
|
|
2014-12-23 15:31:18 +01:00
|
|
|
DRAMCtrl::Rank::Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p)
|
|
|
|
: EventManager(&_memory), memory(_memory),
|
|
|
|
pwrStateTrans(PWR_IDLE), pwrState(PWR_IDLE), pwrStateTick(0),
|
|
|
|
refreshState(REF_IDLE), refreshDueAt(0),
|
|
|
|
power(_p, false), numBanksActive(0),
|
|
|
|
activateEvent(*this), prechargeEvent(*this),
|
|
|
|
refreshEvent(*this), powerEvent(*this)
|
|
|
|
{ }
|
|
|
|
|
|
|
|
void
|
|
|
|
DRAMCtrl::Rank::startup(Tick ref_tick)
|
|
|
|
{
|
|
|
|
assert(ref_tick > curTick());
|
|
|
|
|
|
|
|
pwrStateTick = curTick();
|
|
|
|
|
|
|
|
// kick off the refresh, and give ourselves enough time to
|
|
|
|
// precharge
|
|
|
|
schedule(refreshEvent, ref_tick);
|
|
|
|
}
|
|
|
|
|
2014-12-23 15:31:18 +01:00
|
|
|
void
|
|
|
|
DRAMCtrl::Rank::suspend()
|
|
|
|
{
|
|
|
|
deschedule(refreshEvent);
|
|
|
|
}
|
|
|
|
|
2014-12-23 15:31:18 +01:00
|
|
|
void
|
|
|
|
DRAMCtrl::Rank::checkDrainDone()
|
|
|
|
{
|
|
|
|
// if this rank was waiting to drain it is now able to proceed to
|
|
|
|
// precharge
|
|
|
|
if (refreshState == REF_DRAIN) {
|
|
|
|
DPRINTF(DRAM, "Refresh drain done, now precharging\n");
|
|
|
|
|
|
|
|
refreshState = REF_PRE;
|
|
|
|
|
|
|
|
// hand control back to the refresh event loop
|
|
|
|
schedule(refreshEvent, curTick());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
DRAMCtrl::Rank::processActivateEvent()
|
|
|
|
{
|
|
|
|
// we should transition to the active state as soon as any bank is active
|
|
|
|
if (pwrState != PWR_ACT)
|
|
|
|
// note that at this point numBanksActive could be back at
|
|
|
|
// zero again due to a precharge scheduled in the future
|
|
|
|
schedulePowerEvent(PWR_ACT, curTick());
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
DRAMCtrl::Rank::processPrechargeEvent()
|
|
|
|
{
|
|
|
|
// if we reached zero, then special conditions apply as we track
|
|
|
|
// if all banks are precharged for the power models
|
|
|
|
if (numBanksActive == 0) {
|
|
|
|
// we should transition to the idle state when the last bank
|
|
|
|
// is precharged
|
|
|
|
schedulePowerEvent(PWR_IDLE, curTick());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-09-21 17:48:13 +02:00
|
|
|
void
|
2014-12-23 15:31:18 +01:00
|
|
|
DRAMCtrl::Rank::processRefreshEvent()
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
2014-05-10 00:58:48 +02:00
|
|
|
// when first preparing the refresh, remember when it was due
|
|
|
|
if (refreshState == REF_IDLE) {
|
|
|
|
// remember when the refresh is due
|
|
|
|
refreshDueAt = curTick();
|
|
|
|
|
|
|
|
// proceed to drain
|
|
|
|
refreshState = REF_DRAIN;
|
|
|
|
|
|
|
|
DPRINTF(DRAM, "Refresh due\n");
|
|
|
|
}
|
|
|
|
|
2014-12-23 15:31:18 +01:00
|
|
|
// let any scheduled read or write to the same rank go ahead,
|
|
|
|
// after which it will
|
2014-05-10 00:58:48 +02:00
|
|
|
// hand control back to this event loop
|
|
|
|
if (refreshState == REF_DRAIN) {
|
2014-12-23 15:31:18 +01:00
|
|
|
// if a request is at the moment being handled and this request is
|
|
|
|
// accessing the current rank then wait for it to finish
|
|
|
|
if ((rank == memory.activeRank)
|
|
|
|
&& (memory.nextReqEvent.scheduled())) {
|
2014-05-10 00:58:48 +02:00
|
|
|
// hand control over to the request loop until it is
|
|
|
|
// evaluated next
|
|
|
|
DPRINTF(DRAM, "Refresh awaiting draining\n");
|
|
|
|
|
|
|
|
return;
|
|
|
|
} else {
|
|
|
|
refreshState = REF_PRE;
|
|
|
|
}
|
|
|
|
}
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// at this point, ensure that all banks are precharged
|
|
|
|
if (refreshState == REF_PRE) {
|
2014-05-10 00:58:48 +02:00
|
|
|
// precharge any active bank if we are not already in the idle
|
|
|
|
// state
|
|
|
|
if (pwrState != PWR_IDLE) {
|
2014-05-10 00:58:48 +02:00
|
|
|
// at the moment, we use a precharge all even if there is
|
|
|
|
// only a single bank open
|
2014-05-10 00:58:48 +02:00
|
|
|
DPRINTF(DRAM, "Precharging all\n");
|
2014-05-10 00:58:48 +02:00
|
|
|
|
|
|
|
// first determine when we can precharge
|
|
|
|
Tick pre_at = curTick();
|
2014-12-23 15:31:18 +01:00
|
|
|
|
|
|
|
for (auto &b : banks) {
|
|
|
|
// respect both causality and any existing bank
|
|
|
|
// constraints, some banks could already have a
|
|
|
|
// (auto) precharge scheduled
|
|
|
|
pre_at = std::max(b.preAllowedAt, pre_at);
|
2014-05-10 00:58:48 +02:00
|
|
|
}
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-12-23 15:31:18 +01:00
|
|
|
// make sure all banks per rank are precharged, and for those that
|
2014-05-10 00:58:48 +02:00
|
|
|
// already are, update their availability
|
2014-12-23 15:31:18 +01:00
|
|
|
Tick act_allowed_at = pre_at + memory.tRP;
|
|
|
|
|
|
|
|
for (auto &b : banks) {
|
|
|
|
if (b.openRow != Bank::NO_ROW) {
|
|
|
|
memory.prechargeBank(*this, b, pre_at, false);
|
|
|
|
} else {
|
|
|
|
b.actAllowedAt = std::max(b.actAllowedAt, act_allowed_at);
|
|
|
|
b.preAllowedAt = std::max(b.preAllowedAt, pre_at);
|
2014-05-10 00:58:48 +02:00
|
|
|
}
|
2014-12-23 15:31:18 +01:00
|
|
|
}
|
2014-06-30 19:56:03 +02:00
|
|
|
|
2014-12-23 15:31:18 +01:00
|
|
|
// precharge all banks in rank
|
|
|
|
power.powerlib.doCommand(MemCommand::PREA, 0,
|
|
|
|
divCeil(pre_at, memory.tCK) -
|
|
|
|
memory.timeStampOffset);
|
2014-07-29 18:22:44 +02:00
|
|
|
|
2014-12-23 15:31:18 +01:00
|
|
|
DPRINTF(DRAMPower, "%llu,PREA,0,%d\n",
|
|
|
|
divCeil(pre_at, memory.tCK) -
|
|
|
|
memory.timeStampOffset, rank);
|
2014-05-10 00:58:48 +02:00
|
|
|
} else {
|
|
|
|
DPRINTF(DRAM, "All banks already precharged, starting refresh\n");
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// go ahead and kick the power state machine into gear if
|
|
|
|
// we are already idle
|
|
|
|
schedulePowerEvent(PWR_REF, curTick());
|
|
|
|
}
|
2014-05-10 00:58:48 +02:00
|
|
|
|
|
|
|
refreshState = REF_RUN;
|
2014-05-10 00:58:48 +02:00
|
|
|
assert(numBanksActive == 0);
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// wait for all banks to be precharged, at which point the
|
|
|
|
// power state machine will transition to the idle state, and
|
|
|
|
// automatically move to a refresh, at that point it will also
|
|
|
|
// call this method to get the refresh event loop going again
|
2014-05-10 00:58:48 +02:00
|
|
|
return;
|
|
|
|
}
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// last but not least we perform the actual refresh
|
|
|
|
if (refreshState == REF_RUN) {
|
|
|
|
// should never get here with any banks active
|
|
|
|
assert(numBanksActive == 0);
|
2014-05-10 00:58:48 +02:00
|
|
|
assert(pwrState == PWR_REF);
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-12-23 15:31:18 +01:00
|
|
|
Tick ref_done_at = curTick() + memory.tRFC;
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-12-23 15:31:18 +01:00
|
|
|
for (auto &b : banks) {
|
|
|
|
b.actAllowedAt = ref_done_at;
|
2014-05-10 00:58:48 +02:00
|
|
|
}
|
|
|
|
|
2014-12-23 15:31:18 +01:00
|
|
|
// at the moment this affects all ranks
|
|
|
|
power.powerlib.doCommand(MemCommand::REF, 0,
|
|
|
|
divCeil(curTick(), memory.tCK) -
|
|
|
|
memory.timeStampOffset);
|
|
|
|
|
|
|
|
// at the moment sort the list of commands and update the counters
|
|
|
|
// for DRAMPower libray when doing a refresh
|
|
|
|
sort(power.powerlib.cmdList.begin(),
|
|
|
|
power.powerlib.cmdList.end(), DRAMCtrl::sortTime);
|
|
|
|
|
|
|
|
// update the counters for DRAMPower, passing false to
|
|
|
|
// indicate that this is not the last command in the
|
|
|
|
// list. DRAMPower requires this information for the
|
|
|
|
// correct calculation of the background energy at the end
|
|
|
|
// of the simulation. Ideally we would want to call this
|
|
|
|
// function with true once at the end of the
|
|
|
|
// simulation. However, the discarded energy is extremly
|
|
|
|
// small and does not effect the final results.
|
|
|
|
power.powerlib.updateCounters(false);
|
|
|
|
|
|
|
|
// call the energy function
|
|
|
|
power.powerlib.calcEnergy();
|
|
|
|
|
|
|
|
// Update the stats
|
|
|
|
updatePowerStats();
|
|
|
|
|
|
|
|
DPRINTF(DRAMPower, "%llu,REF,0,%d\n", divCeil(curTick(), memory.tCK) -
|
|
|
|
memory.timeStampOffset, rank);
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// make sure we did not wait so long that we cannot make up
|
|
|
|
// for it
|
2014-12-23 15:31:18 +01:00
|
|
|
if (refreshDueAt + memory.tREFI < ref_done_at) {
|
2014-05-10 00:58:48 +02:00
|
|
|
fatal("Refresh was delayed so long we cannot catch up\n");
|
2013-11-01 16:56:28 +01:00
|
|
|
}
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// compensate for the delay in actually performing the refresh
|
|
|
|
// when scheduling the next one
|
2014-12-23 15:31:18 +01:00
|
|
|
schedule(refreshEvent, refreshDueAt + memory.tREFI - memory.tRP);
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
assert(!powerEvent.scheduled());
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// move to the idle power state once the refresh is done, this
|
|
|
|
// will also move the refresh state machine to the refresh
|
|
|
|
// idle state
|
2014-05-10 00:58:48 +02:00
|
|
|
schedulePowerEvent(PWR_IDLE, ref_done_at);
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
DPRINTF(DRAMState, "Refresh done at %llu and next refresh at %llu\n",
|
2014-12-23 15:31:18 +01:00
|
|
|
ref_done_at, refreshDueAt + memory.tREFI);
|
2014-05-10 00:58:48 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2014-12-23 15:31:18 +01:00
|
|
|
DRAMCtrl::Rank::schedulePowerEvent(PowerState pwr_state, Tick tick)
|
2014-05-10 00:58:48 +02:00
|
|
|
{
|
|
|
|
// respect causality
|
|
|
|
assert(tick >= curTick());
|
|
|
|
|
|
|
|
if (!powerEvent.scheduled()) {
|
|
|
|
DPRINTF(DRAMState, "Scheduling power event at %llu to state %d\n",
|
|
|
|
tick, pwr_state);
|
|
|
|
|
|
|
|
// insert the new transition
|
|
|
|
pwrStateTrans = pwr_state;
|
|
|
|
|
|
|
|
schedule(powerEvent, tick);
|
|
|
|
} else {
|
|
|
|
panic("Scheduled power event at %llu to state %d, "
|
|
|
|
"with scheduled event at %llu to %d\n", tick, pwr_state,
|
|
|
|
powerEvent.when(), pwrStateTrans);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2014-12-23 15:31:18 +01:00
|
|
|
DRAMCtrl::Rank::processPowerEvent()
|
2014-05-10 00:58:48 +02:00
|
|
|
{
|
|
|
|
// remember where we were, and for how long
|
|
|
|
Tick duration = curTick() - pwrStateTick;
|
|
|
|
PowerState prev_state = pwrState;
|
|
|
|
|
|
|
|
// update the accounting
|
|
|
|
pwrStateTime[prev_state] += duration;
|
|
|
|
|
|
|
|
pwrState = pwrStateTrans;
|
|
|
|
pwrStateTick = curTick();
|
|
|
|
|
|
|
|
if (pwrState == PWR_IDLE) {
|
|
|
|
DPRINTF(DRAMState, "All banks precharged\n");
|
|
|
|
|
|
|
|
// if we were refreshing, make sure we start scheduling requests again
|
|
|
|
if (prev_state == PWR_REF) {
|
|
|
|
DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration);
|
|
|
|
assert(pwrState == PWR_IDLE);
|
|
|
|
|
|
|
|
// kick things into action again
|
|
|
|
refreshState = REF_IDLE;
|
2014-12-23 15:31:18 +01:00
|
|
|
// a request event could be already scheduled by the state
|
|
|
|
// machine of the other rank
|
|
|
|
if (!memory.nextReqEvent.scheduled())
|
|
|
|
schedule(memory.nextReqEvent, curTick());
|
2014-05-10 00:58:48 +02:00
|
|
|
} else {
|
|
|
|
assert(prev_state == PWR_ACT);
|
|
|
|
|
|
|
|
// if we have a pending refresh, and are now moving to
|
|
|
|
// the idle state, direclty transition to a refresh
|
|
|
|
if (refreshState == REF_RUN) {
|
|
|
|
// there should be nothing waiting at this point
|
|
|
|
assert(!powerEvent.scheduled());
|
|
|
|
|
|
|
|
// update the state in zero time and proceed below
|
|
|
|
pwrState = PWR_REF;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// we transition to the refresh state, let the refresh state
|
|
|
|
// machine know of this state update and let it deal with the
|
|
|
|
// scheduling of the next power state transition as well as the
|
|
|
|
// following refresh
|
|
|
|
if (pwrState == PWR_REF) {
|
|
|
|
DPRINTF(DRAMState, "Refreshing\n");
|
|
|
|
// kick the refresh event loop into action again, and that
|
|
|
|
// in turn will schedule a transition to the idle power
|
|
|
|
// state once the refresh is done
|
|
|
|
assert(refreshState == REF_RUN);
|
|
|
|
processRefreshEvent();
|
2014-05-10 00:58:48 +02:00
|
|
|
}
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
2014-07-29 18:22:44 +02:00
|
|
|
void
|
2014-12-23 15:31:18 +01:00
|
|
|
DRAMCtrl::Rank::updatePowerStats()
|
2014-07-29 18:22:44 +02:00
|
|
|
{
|
|
|
|
// Get the energy and power from DRAMPower
|
|
|
|
Data::MemoryPowerModel::Energy energy =
|
2014-12-23 15:31:18 +01:00
|
|
|
power.powerlib.getEnergy();
|
|
|
|
Data::MemoryPowerModel::Power rank_power =
|
|
|
|
power.powerlib.getPower();
|
|
|
|
|
|
|
|
actEnergy = energy.act_energy * memory.devicesPerRank;
|
|
|
|
preEnergy = energy.pre_energy * memory.devicesPerRank;
|
|
|
|
readEnergy = energy.read_energy * memory.devicesPerRank;
|
|
|
|
writeEnergy = energy.write_energy * memory.devicesPerRank;
|
|
|
|
refreshEnergy = energy.ref_energy * memory.devicesPerRank;
|
|
|
|
actBackEnergy = energy.act_stdby_energy * memory.devicesPerRank;
|
|
|
|
preBackEnergy = energy.pre_stdby_energy * memory.devicesPerRank;
|
|
|
|
totalEnergy = energy.total_energy * memory.devicesPerRank;
|
|
|
|
averagePower = rank_power.average_power * memory.devicesPerRank;
|
2014-07-29 18:22:44 +02:00
|
|
|
}
|
|
|
|
|
2014-12-23 15:31:18 +01:00
|
|
|
void
|
|
|
|
DRAMCtrl::Rank::regStats()
|
|
|
|
{
|
|
|
|
using namespace Stats;
|
|
|
|
|
|
|
|
pwrStateTime
|
|
|
|
.init(5)
|
|
|
|
.name(name() + ".memoryStateTime")
|
|
|
|
.desc("Time in different power states");
|
|
|
|
pwrStateTime.subname(0, "IDLE");
|
|
|
|
pwrStateTime.subname(1, "REF");
|
|
|
|
pwrStateTime.subname(2, "PRE_PDN");
|
|
|
|
pwrStateTime.subname(3, "ACT");
|
|
|
|
pwrStateTime.subname(4, "ACT_PDN");
|
|
|
|
|
|
|
|
actEnergy
|
|
|
|
.name(name() + ".actEnergy")
|
|
|
|
.desc("Energy for activate commands per rank (pJ)");
|
|
|
|
|
|
|
|
preEnergy
|
|
|
|
.name(name() + ".preEnergy")
|
|
|
|
.desc("Energy for precharge commands per rank (pJ)");
|
|
|
|
|
|
|
|
readEnergy
|
|
|
|
.name(name() + ".readEnergy")
|
|
|
|
.desc("Energy for read commands per rank (pJ)");
|
|
|
|
|
|
|
|
writeEnergy
|
|
|
|
.name(name() + ".writeEnergy")
|
|
|
|
.desc("Energy for write commands per rank (pJ)");
|
|
|
|
|
|
|
|
refreshEnergy
|
|
|
|
.name(name() + ".refreshEnergy")
|
|
|
|
.desc("Energy for refresh commands per rank (pJ)");
|
|
|
|
|
|
|
|
actBackEnergy
|
|
|
|
.name(name() + ".actBackEnergy")
|
|
|
|
.desc("Energy for active background per rank (pJ)");
|
|
|
|
|
|
|
|
preBackEnergy
|
|
|
|
.name(name() + ".preBackEnergy")
|
|
|
|
.desc("Energy for precharge background per rank (pJ)");
|
|
|
|
|
|
|
|
totalEnergy
|
|
|
|
.name(name() + ".totalEnergy")
|
|
|
|
.desc("Total energy per rank (pJ)");
|
|
|
|
|
|
|
|
averagePower
|
|
|
|
.name(name() + ".averagePower")
|
|
|
|
.desc("Core power per rank (mW)");
|
|
|
|
}
|
2012-09-21 17:48:13 +02:00
|
|
|
void
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::regStats()
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
using namespace Stats;
|
|
|
|
|
|
|
|
AbstractMemory::regStats();
|
|
|
|
|
2014-12-23 15:31:18 +01:00
|
|
|
for (auto r : ranks) {
|
|
|
|
r->regStats();
|
|
|
|
}
|
|
|
|
|
2012-09-21 17:48:13 +02:00
|
|
|
readReqs
|
|
|
|
.name(name() + ".readReqs")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Number of read requests accepted");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
writeReqs
|
|
|
|
.name(name() + ".writeReqs")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Number of write requests accepted");
|
2013-08-19 09:52:30 +02:00
|
|
|
|
|
|
|
readBursts
|
|
|
|
.name(name() + ".readBursts")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Number of DRAM read bursts, "
|
|
|
|
"including those serviced by the write queue");
|
2013-08-19 09:52:30 +02:00
|
|
|
|
|
|
|
writeBursts
|
|
|
|
.name(name() + ".writeBursts")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Number of DRAM write bursts, "
|
|
|
|
"including those merged in the write queue");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
servicedByWrQ
|
|
|
|
.name(name() + ".servicedByWrQ")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Number of DRAM read bursts serviced by the write queue");
|
|
|
|
|
|
|
|
mergedWrBursts
|
|
|
|
.name(name() + ".mergedWrBursts")
|
|
|
|
.desc("Number of DRAM write bursts merged with an existing one");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
neitherReadNorWrite
|
2013-11-01 16:56:31 +01:00
|
|
|
.name(name() + ".neitherReadNorWriteReqs")
|
|
|
|
.desc("Number of requests that are neither read nor write");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-11-01 16:56:31 +01:00
|
|
|
perBankRdBursts
|
2012-09-21 17:48:13 +02:00
|
|
|
.init(banksPerRank * ranksPerChannel)
|
2013-11-01 16:56:31 +01:00
|
|
|
.name(name() + ".perBankRdBursts")
|
|
|
|
.desc("Per bank write bursts");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-11-01 16:56:31 +01:00
|
|
|
perBankWrBursts
|
2012-09-21 17:48:13 +02:00
|
|
|
.init(banksPerRank * ranksPerChannel)
|
2013-11-01 16:56:31 +01:00
|
|
|
.name(name() + ".perBankWrBursts")
|
|
|
|
.desc("Per bank write bursts");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
avgRdQLen
|
|
|
|
.name(name() + ".avgRdQLen")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Average read queue length when enqueuing")
|
2012-09-21 17:48:13 +02:00
|
|
|
.precision(2);
|
|
|
|
|
|
|
|
avgWrQLen
|
|
|
|
.name(name() + ".avgWrQLen")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Average write queue length when enqueuing")
|
2012-09-21 17:48:13 +02:00
|
|
|
.precision(2);
|
|
|
|
|
|
|
|
totQLat
|
|
|
|
.name(name() + ".totQLat")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Total ticks spent queuing");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
totBusLat
|
|
|
|
.name(name() + ".totBusLat")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Total ticks spent in databus transfers");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
totMemAccLat
|
|
|
|
.name(name() + ".totMemAccLat")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Total ticks spent from burst creation until serviced "
|
|
|
|
"by the DRAM");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
avgQLat
|
|
|
|
.name(name() + ".avgQLat")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Average queueing delay per DRAM burst")
|
2012-09-21 17:48:13 +02:00
|
|
|
.precision(2);
|
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
avgQLat = totQLat / (readBursts - servicedByWrQ);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
avgBusLat
|
|
|
|
.name(name() + ".avgBusLat")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Average bus latency per DRAM burst")
|
2012-09-21 17:48:13 +02:00
|
|
|
.precision(2);
|
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
avgBusLat = totBusLat / (readBursts - servicedByWrQ);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
avgMemAccLat
|
|
|
|
.name(name() + ".avgMemAccLat")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Average memory access latency per DRAM burst")
|
2012-09-21 17:48:13 +02:00
|
|
|
.precision(2);
|
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
numRdRetry
|
|
|
|
.name(name() + ".numRdRetry")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Number of times read queue was full causing retry");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
numWrRetry
|
|
|
|
.name(name() + ".numWrRetry")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Number of times write queue was full causing retry");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
readRowHits
|
|
|
|
.name(name() + ".readRowHits")
|
|
|
|
.desc("Number of row buffer hits during reads");
|
|
|
|
|
|
|
|
writeRowHits
|
|
|
|
.name(name() + ".writeRowHits")
|
|
|
|
.desc("Number of row buffer hits during writes");
|
|
|
|
|
|
|
|
readRowHitRate
|
|
|
|
.name(name() + ".readRowHitRate")
|
|
|
|
.desc("Row buffer hit rate for reads")
|
|
|
|
.precision(2);
|
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
writeRowHitRate
|
|
|
|
.name(name() + ".writeRowHitRate")
|
|
|
|
.desc("Row buffer hit rate for writes")
|
|
|
|
.precision(2);
|
|
|
|
|
2013-11-01 16:56:31 +01:00
|
|
|
writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
readPktSize
|
2013-08-19 09:52:30 +02:00
|
|
|
.init(ceilLog2(burstSize) + 1)
|
2012-09-21 17:48:13 +02:00
|
|
|
.name(name() + ".readPktSize")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Read request sizes (log2)");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
writePktSize
|
2013-08-19 09:52:30 +02:00
|
|
|
.init(ceilLog2(burstSize) + 1)
|
2012-09-21 17:48:13 +02:00
|
|
|
.name(name() + ".writePktSize")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Write request sizes (log2)");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
rdQLenPdf
|
2013-03-01 19:20:24 +01:00
|
|
|
.init(readBufferSize)
|
2012-09-21 17:48:13 +02:00
|
|
|
.name(name() + ".rdQLenPdf")
|
|
|
|
.desc("What read queue length does an incoming req see");
|
|
|
|
|
|
|
|
wrQLenPdf
|
2013-03-01 19:20:24 +01:00
|
|
|
.init(writeBufferSize)
|
2012-09-21 17:48:13 +02:00
|
|
|
.name(name() + ".wrQLenPdf")
|
|
|
|
.desc("What write queue length does an incoming req see");
|
|
|
|
|
2013-05-30 18:54:13 +02:00
|
|
|
bytesPerActivate
|
2014-03-23 16:12:03 +01:00
|
|
|
.init(maxAccessesPerRow)
|
2013-05-30 18:54:13 +02:00
|
|
|
.name(name() + ".bytesPerActivate")
|
|
|
|
.desc("Bytes accessed per row activation")
|
|
|
|
.flags(nozero);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2014-03-23 16:12:14 +01:00
|
|
|
rdPerTurnAround
|
|
|
|
.init(readBufferSize)
|
|
|
|
.name(name() + ".rdPerTurnAround")
|
|
|
|
.desc("Reads before turning the bus around for writes")
|
|
|
|
.flags(nozero);
|
|
|
|
|
|
|
|
wrPerTurnAround
|
|
|
|
.init(writeBufferSize)
|
|
|
|
.name(name() + ".wrPerTurnAround")
|
|
|
|
.desc("Writes before turning the bus around for reads")
|
|
|
|
.flags(nozero);
|
|
|
|
|
2013-11-01 16:56:28 +01:00
|
|
|
bytesReadDRAM
|
|
|
|
.name(name() + ".bytesReadDRAM")
|
|
|
|
.desc("Total number of bytes read from DRAM");
|
|
|
|
|
|
|
|
bytesReadWrQ
|
|
|
|
.name(name() + ".bytesReadWrQ")
|
|
|
|
.desc("Total number of bytes read from write queue");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
bytesWritten
|
|
|
|
.name(name() + ".bytesWritten")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Total number of bytes written to DRAM");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-11-01 16:56:31 +01:00
|
|
|
bytesReadSys
|
|
|
|
.name(name() + ".bytesReadSys")
|
|
|
|
.desc("Total read bytes from the system interface side");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-11-01 16:56:31 +01:00
|
|
|
bytesWrittenSys
|
|
|
|
.name(name() + ".bytesWrittenSys")
|
|
|
|
.desc("Total written bytes from the system interface side");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
avgRdBW
|
|
|
|
.name(name() + ".avgRdBW")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Average DRAM read bandwidth in MiByte/s")
|
2012-09-21 17:48:13 +02:00
|
|
|
.precision(2);
|
|
|
|
|
2013-11-01 16:56:31 +01:00
|
|
|
avgRdBW = (bytesReadDRAM / 1000000) / simSeconds;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
avgWrBW
|
|
|
|
.name(name() + ".avgWrBW")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Average achieved write bandwidth in MiByte/s")
|
2012-09-21 17:48:13 +02:00
|
|
|
.precision(2);
|
|
|
|
|
|
|
|
avgWrBW = (bytesWritten / 1000000) / simSeconds;
|
|
|
|
|
2013-11-01 16:56:31 +01:00
|
|
|
avgRdBWSys
|
|
|
|
.name(name() + ".avgRdBWSys")
|
|
|
|
.desc("Average system read bandwidth in MiByte/s")
|
2012-09-21 17:48:13 +02:00
|
|
|
.precision(2);
|
|
|
|
|
2013-11-01 16:56:31 +01:00
|
|
|
avgRdBWSys = (bytesReadSys / 1000000) / simSeconds;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-11-01 16:56:31 +01:00
|
|
|
avgWrBWSys
|
|
|
|
.name(name() + ".avgWrBWSys")
|
|
|
|
.desc("Average system write bandwidth in MiByte/s")
|
2012-09-21 17:48:13 +02:00
|
|
|
.precision(2);
|
|
|
|
|
2013-11-01 16:56:31 +01:00
|
|
|
avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
peakBW
|
|
|
|
.name(name() + ".peakBW")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Theoretical peak bandwidth in MiByte/s")
|
2012-09-21 17:48:13 +02:00
|
|
|
.precision(2);
|
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
busUtil
|
|
|
|
.name(name() + ".busUtil")
|
|
|
|
.desc("Data bus utilization in percentage")
|
|
|
|
.precision(2);
|
|
|
|
busUtil = (avgRdBW + avgWrBW) / peakBW * 100;
|
|
|
|
|
|
|
|
totGap
|
|
|
|
.name(name() + ".totGap")
|
|
|
|
.desc("Total gap between requests");
|
|
|
|
|
|
|
|
avgGap
|
|
|
|
.name(name() + ".avgGap")
|
|
|
|
.desc("Average gap between requests")
|
|
|
|
.precision(2);
|
|
|
|
|
|
|
|
avgGap = totGap / (readReqs + writeReqs);
|
2013-11-01 16:56:28 +01:00
|
|
|
|
|
|
|
// Stats for DRAM Power calculation based on Micron datasheet
|
|
|
|
busUtilRead
|
|
|
|
.name(name() + ".busUtilRead")
|
|
|
|
.desc("Data bus utilization in percentage for reads")
|
|
|
|
.precision(2);
|
|
|
|
|
|
|
|
busUtilRead = avgRdBW / peakBW * 100;
|
|
|
|
|
|
|
|
busUtilWrite
|
|
|
|
.name(name() + ".busUtilWrite")
|
|
|
|
.desc("Data bus utilization in percentage for writes")
|
|
|
|
.precision(2);
|
|
|
|
|
|
|
|
busUtilWrite = avgWrBW / peakBW * 100;
|
|
|
|
|
|
|
|
pageHitRate
|
|
|
|
.name(name() + ".pageHitRate")
|
|
|
|
.desc("Row buffer hit rate, read and write combined")
|
|
|
|
.precision(2);
|
|
|
|
|
2013-11-01 16:56:31 +01:00
|
|
|
pageHitRate = (writeRowHits + readRowHits) /
|
|
|
|
(writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100;
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::recvFunctional(PacketPtr pkt)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
// rely on the abstract memory
|
|
|
|
functionalAccess(pkt);
|
|
|
|
}
|
|
|
|
|
2012-10-15 14:12:35 +02:00
|
|
|
BaseSlavePort&
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::getSlavePort(const string &if_name, PortID idx)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
if (if_name != "port") {
|
|
|
|
return MemObject::getSlavePort(if_name, idx);
|
|
|
|
} else {
|
|
|
|
return port;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned int
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::drain(DrainManager *dm)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
// if there is anything in any of our internal queues, keep track
|
|
|
|
// of that as well
|
2013-03-01 19:20:24 +01:00
|
|
|
if (!(writeQueue.empty() && readQueue.empty() &&
|
|
|
|
respQueue.empty())) {
|
2012-11-08 10:25:06 +01:00
|
|
|
DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d,"
|
2013-03-01 19:20:24 +01:00
|
|
|
" resp: %d\n", writeQueue.size(), readQueue.size(),
|
|
|
|
respQueue.size());
|
2012-11-02 17:32:01 +01:00
|
|
|
drainManager = dm;
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2012-11-08 10:25:06 +01:00
|
|
|
// the only part that is not drained automatically over time
|
2014-05-10 00:58:48 +02:00
|
|
|
// is the write queue, thus kick things into action if needed
|
|
|
|
if (!writeQueue.empty() && !nextReqEvent.scheduled()) {
|
|
|
|
schedule(nextReqEvent, curTick());
|
|
|
|
}
|
2015-07-07 10:51:04 +02:00
|
|
|
setDrainState(DrainState::Draining);
|
2015-07-07 10:51:05 +02:00
|
|
|
return 1;
|
|
|
|
} else {
|
2015-07-07 10:51:04 +02:00
|
|
|
setDrainState(DrainState::Drained);
|
2015-07-07 10:51:05 +02:00
|
|
|
return 0;
|
|
|
|
}
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
2014-12-23 15:31:18 +01:00
|
|
|
void
|
|
|
|
DRAMCtrl::drainResume()
|
|
|
|
{
|
|
|
|
if (!isTimingMode && system()->isTimingMode()) {
|
|
|
|
// if we switched to timing mode, kick things into action,
|
|
|
|
// and behave as if we restored from a checkpoint
|
|
|
|
startup();
|
|
|
|
} else if (isTimingMode && !system()->isTimingMode()) {
|
|
|
|
// if we switch from timing mode, stop the refresh events to
|
|
|
|
// not cause issues with KVM
|
|
|
|
for (auto r : ranks) {
|
|
|
|
r->suspend();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// update the mode
|
|
|
|
isTimingMode = system()->isTimingMode();
|
|
|
|
}
|
|
|
|
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory)
|
2012-09-21 17:48:13 +02:00
|
|
|
: QueuedSlavePort(name, &_memory, queue), queue(_memory, *this),
|
|
|
|
memory(_memory)
|
|
|
|
{ }
|
|
|
|
|
|
|
|
AddrRangeList
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::MemoryPort::getAddrRanges() const
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
AddrRangeList ranges;
|
|
|
|
ranges.push_back(memory.getAddrRange());
|
|
|
|
return ranges;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
pkt->pushLabel(memory.name());
|
|
|
|
|
|
|
|
if (!queue.checkFunctional(pkt)) {
|
|
|
|
// Default implementation of SimpleTimingPort::recvFunctional()
|
|
|
|
// calls recvAtomic() and throws away the latency; we can save a
|
|
|
|
// little here by just not calculating the latency.
|
|
|
|
memory.recvFunctional(pkt);
|
|
|
|
}
|
|
|
|
|
|
|
|
pkt->popLabel();
|
|
|
|
}
|
|
|
|
|
|
|
|
Tick
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
return memory.recvAtomic(pkt);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
// pass it to the memory controller
|
|
|
|
return memory.recvTimingReq(pkt);
|
|
|
|
}
|
|
|
|
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl*
|
|
|
|
DRAMCtrlParams::create()
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
2014-03-23 16:12:12 +01:00
|
|
|
return new DRAMCtrl(this);
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|