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DRAM: Introduce SimpleDRAM to capture a high-level controller

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This patch introduces a high-level model of a DRAM controller, with a
basic read/write buffer structure, a selectable and customisable
arbiter, a few address mapping options, and the basic DRAM timing
constraints. The parameters make it possible to turn this model into
any desired DDRx/LPDDRx/WideIOx memory controller.

The intention is not to be cycle accurate or capture every aspect of a
DDR DRAM interface, but rather to enable exploring of the high-level
knobs with a good simulation speed. Thus, contrary to e.g. DRAMSim
this module emphasizes simulation speed with a good-enough accuracy.

This module is merely a starting point, and there are plenty additions
and improvements to come. A notable addition is the support for
address-striping in the bus to enable a multi-channel DRAM
controller. Also note that there are still a few "todo's" in the code
base that will be addressed as we go along.

A follow-up patch will add basic performance regressions that use the
traffic generator to exercise a few well-defined corner cases.
This commit is contained in:
Andreas Hansson 2012-09-21 11:48:13 -04:00
parent efea870fce
commit 3b6a143ec5
4 changed files with 1876 additions and 0 deletions
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4
src/mem/SConscript
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@ -53,10 +53,12 @@ Source('se_translating_port_proxy.cc')
if env['TARGET_ISA'] != 'no':
SimObject('AbstractMemory.py')
SimObject('SimpleMemory.py')
SimObject('SimpleDRAM.py')
Source('abstract_mem.cc')
Source('simple_mem.cc')
Source('page_table.cc')
Source('physical.cc')
Source('simple_dram.cc')
DebugFlag('BaseBus')
DebugFlag('BusAddrRanges')
@ -67,6 +69,8 @@ CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus',
DebugFlag('Bridge')
DebugFlag('CommMonitor')
DebugFlag('DRAM')
DebugFlag('DRAMWR')
DebugFlag('LLSC')
DebugFlag('MMU')
DebugFlag('MemoryAccess')

130
src/mem/SimpleDRAM.py Normal file
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@ -0,0 +1,130 @@
# Copyright (c) 2012 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Andreas Hansson
# Ani Udipi
from m5.params import *
from AbstractMemory import *
# Enum for memory scheduling algorithms, currently First-Come
# First-Served and a First-Row Hit then First-Come First-Served
class MemSched(Enum): vals = ['fcfs', 'frfcfs']
# Enum for the address mapping, currently corresponding to either
# optimising for sequential accesses hitting in the open row, or
# striping across banks.
class AddrMap(Enum): vals = ['openmap', 'closemap']
# Enum for the page policy, either open or close.
class PageManage(Enum): vals = ['open', 'close']
# SimpleDRAM is a single-channel single-ported DRAM controller model
# that aims to model the most important system-level performance
# effects of a DRAM without getting into too much detail of the DRAM
# itself.
class SimpleDRAM(AbstractMemory):
type = 'SimpleDRAM'
# single-ported on the system interface side, instantiate with a
# bus in front of the controller for multiple ports
port = SlavePort("Slave port")
# the physical organisation of the DRAM
lines_per_rowbuffer = Param.Unsigned(64, "Row buffer size in cache lines")
ranks_per_channel = Param.Unsigned(2, "Number of ranks per channel")
banks_per_rank = Param.Unsigned(8, "Number of banks per rank")
# the basic configuration of the controller architecture
write_buffer_size = Param.Unsigned(32, "Number of read queue entries")
read_buffer_size = Param.Unsigned(32, "Number of write queue entries")
# threshold in percent for when to trigger writes and start
# emptying the write buffer as it starts to get full
write_thresh_perc = Param.Percent(70, "Threshold to trigger writes")
# scheduler, address map and page policy
mem_sched_policy = Param.MemSched('fcfs', "Memory scheduling policy")
addr_mapping = Param.AddrMap('openmap', "Address mapping policy")
page_policy = Param.PageManage('open', "Page closure management policy")
# timing behaviour and constraints - all in nanoseconds
# the amount of time in nanoseconds from issuing an activate command
# to the data being available in the row buffer for a read/write
tRCD = Param.Latency("14ns", "RAS to CAS delay")
# the time from issuing a read/write command to seeing the actual data
tCL = Param.Latency("14ns", "CAS latency")
# minimum time between a precharge and subsequent activate
tRP = Param.Latency("14ns", "Row precharge time")
# time to complete a burst transfer, typically the burst length
# divided by two due to the DDR bus, but by making it a parameter
# it is easier to also evaluate SDR memories like WideIO.
# This parameter has to account for bus width and burst length.
# Adjustment also necessary if cache line size is greater than
# data size read/written by one full burst.
tBURST = Param.Latency("4ns",
"Burst duration (for DDR burst length / 2 cycles)")
# time taken to complete one refresh cycle (N rows in all banks)
tRFC = Param.Latency("300ns", "Refresh cycle time")
# refresh command interval, how often a "ref" command needs
# to be sent. It is 7.8 us for a 64ms refresh requirement
tREFI = Param.Latency("7.8us", "Refresh command interval")
# write-to-read turn around penalty, assumed same as read-to-write
tWTR = Param.Latency("1ns", "Write to read switching time")
# Currently unimplemented, unused, deduced or rolled into other params
######################################################################
# the minimum amount of time between a row being activated, and
# precharged (de-activated)
# tRAS - assumed to be 3 * tRP
# tRC - assumed to be 4 * tRP
# burst length for an access derived from peerBlockSize
# @todo: Implement tFAW in the model
# minimum time window in which a maximum of four activates are
# allowed to take place
# tFAW = Param.Latency("30ns", "Four activation window")

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src/mem/simple_dram.hh Normal file
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@ -0,0 +1,478 @@
/*
* Copyright (c) 2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Andreas Hansson
* Ani Udipi
*/
/**
* @file
* SimpleDRAM declaration
*/
#ifndef __MEM_SIMPLE_DRAM_HH__
#define __MEM_SIMPLE_DRAM_HH__
#include "base/statistics.hh"
#include "enums/AddrMap.hh"
#include "enums/MemSched.hh"
#include "enums/PageManage.hh"
#include "mem/abstract_mem.hh"
#include "mem/qport.hh"
#include "params/SimpleDRAM.hh"
#include "sim/eventq.hh"
/**
* The simple DRAM is a basic single-channel memory controller aiming
* to mimic a high-level DRAM controller and the most important timing
* constraints associated with the DRAM. The focus is really on
* modelling the impact on the system rather than the DRAM itself,
* hence the focus is on the controller model and not on the
* memory. By adhering to the correct timing constraints, ultimately
* there is no need for a memory model in addition to the controller
* model.
*
* As a basic design principle, this controller is not cycle callable,
* but instead uses events to decide when new decisions can be made,
* when resources become available, when things are to be considered
* done, and when to send things back. Through these simple
* principles, we achieve a performant model that is not
* cycle-accurate, but enables us to evaluate the system impact of a
* wide range of memory technologies, and also collect statistics
* about the use of the memory.
*/
class SimpleDRAM : public AbstractMemory
{
private:
// For now, make use of a queued slave port to avoid dealing with
// flow control for the responses being sent back
class MemoryPort : public QueuedSlavePort
{
SlavePacketQueue queue;
SimpleDRAM& memory;
public:
MemoryPort(const std::string& name, SimpleDRAM& _memory);
protected:
Tick recvAtomic(PacketPtr pkt);
void recvFunctional(PacketPtr pkt);
bool recvTimingReq(PacketPtr);
virtual AddrRangeList getAddrRanges() const;
};
/**
* Our incoming port, for a multi-ported controller add a crossbar
* in front of it
*/
MemoryPort port;
/**
* Remember if we have to retry a request when available.
*/
bool retryRdReq;
bool retryWrReq;
/**
* Remember that a row buffer hit occured
*/
bool rowHitFlag;
/**
* Use this flag to shutoff reads, i.e. do not schedule any reads
* beyond those already done so that we can turn the bus around
* and do a few writes, or refresh, or whatever
*/
bool stopReads;
/**
* A basic class to track the bank state indirectly via
* times "freeAt" and "tRASDoneAt" and what page is currently open
*/
class Bank
{
public:
static const uint32_t INVALID_ROW = -1;
uint32_t openRow;
Tick freeAt;
Tick tRASDoneAt;
Bank() : openRow(INVALID_ROW), freeAt(0), tRASDoneAt(0)
{ }
};
/**
* A DRAM packet stores packets along with the timestamp of when
* the packet entered the queue, and also the decoded address.
*/
class DRAMPacket {
public:
/** When did request enter the controller */
const Tick entryTime;
/** When will request leave the controller */
Tick readyTime;
/** This comes from the outside world */
const PacketPtr pkt;
/** Will be populated by address decoder */
const uint8_t rank;
const uint16_t bank;
const uint16_t row;
const Addr addr;
Bank& bank_ref;
DRAMPacket(PacketPtr _pkt, uint8_t _rank,
uint16_t _bank, uint16_t _row, Addr _addr, Bank& _bank_ref)
: entryTime(curTick()), readyTime(curTick()),
pkt(_pkt), rank(_rank), bank(_bank), row(_row), addr(_addr),
bank_ref(_bank_ref)
{ }
};
/**
* Bunch of things requires to setup "events" in gem5
* When event "writeEvent" occurs for example, the method
* processWriteEvent is called; no parameters are allowed
* in these methods
*/
void processWriteEvent();
EventWrapper<SimpleDRAM, &SimpleDRAM::processWriteEvent> writeEvent;
void processRespondEvent();
EventWrapper<SimpleDRAM, &SimpleDRAM::processRespondEvent> respondEvent;
void processRefreshEvent();
EventWrapper<SimpleDRAM, &SimpleDRAM::processRefreshEvent> refreshEvent;
void processNextReqEvent();
EventWrapper<SimpleDRAM,&SimpleDRAM::processNextReqEvent> nextReqEvent;
/**
* Check if the read queue has room for more entries
*
* @return true if read queue is full, false otherwise
*/
bool readQueueFull() const;
/**
* Check if the write queue has room for more entries
*
* @return true if write queue is full, false otherwise
*/
bool writeQueueFull() const;
/**
* When a new read comes in, first check if the write q has a
* pending request to the same address.\ If not, decode the
* address to populate rank/bank/row, create a "dram_pkt", and
* push it to the back of the read queue.\ If this is the only
* read request in the system, schedule an event to start
* servicing it.
*
* @param pkt The request packet from the outside world
*/
void addToReadQueue(PacketPtr pkt);
/**
* Decode the incoming pkt, create a dram_pkt and push to the
* back of the write queue. \If the write q length is more than
* the threshold specified by the user, ie the queue is beginning
* to get full, stop reads, and start draining writes.
*
* @param pkt The request packet from the outside world
*/
void addToWriteQueue(PacketPtr pkt);
/**
* Actually do the DRAM access - figure out the latency it
* will take to service the req based on bank state, channel state etc
* and then update those states to account for this request.\ Based
* on this, update the packet's "readyTime" and move it to the
* response q from where it will eventually go back to the outside
* world.
*
* @param pkt The DRAM packet created from the outside world pkt
*/
void doDRAMAccess(DRAMPacket* dram_pkt);
/**
* Check when the channel is free to turnaround, add turnaround
* delay and schedule a whole bunch of writes.
*/
void triggerWrites();
/**
* When a packet reaches its "readyTime" in the response Q,
* use the "access()" method in AbstractMemory to actually
* create the response packet, and send it back to the outside
* world requestor.
*
* @param pkt The packet from the outside world
*/
void accessAndRespond(PacketPtr pkt);
/**
* Address decoder to figure out physical mapping onto ranks,
* banks, and rows.
*
* @param pkt The packet from the outside world
* @return A DRAMPacket pointer with the decoded information
*/
DRAMPacket* decodeAddr(PacketPtr pkt);
/**
* The memory schduler/arbiter - picks which request needs to
* go next, based on the specified policy such as fcfs or frfcfs
* and moves it to the head of the read queue
*
* @return True if a request was chosen, False if Q is empty
*/
bool chooseNextReq();
/**
* Calls chooseNextReq() to pick the right request, then calls
* doDRAMAccess on that request in order to actually service
* that request
*/
void scheduleNextReq();
/**
*Looks at the state of the banks, channels, row buffer hits etc
* to estimate how long a request will take to complete.
*
* @param dram_pkt The request for which we want to estimate latency
* @param inTime The tick at which you want to probe the memory
*
* @return A pair of ticks, one indicating how many ticks *after*
* inTime the request require, and the other indicating how
* much of that was just the bank access time, ignoring the
* ticks spent simply waiting for resources to become free
*/
std::pair<Tick, Tick> estimateLatency(DRAMPacket* dram_pkt, Tick inTime);
/**
* Move the request at the head of the read queue to the response
* queue, sorting by readyTime.\ If it is the only packet in the
* response queue, schedule a respond event to send it back to the
* outside world
*/
void moveToRespQ();
/**
* Scheduling policy within the write Q
*/
void chooseNextWrite();
/**
* Looking at all banks, determine the moment in time when they
* are all free.
*
* @return The tick when all banks are free
*/
Tick maxBankFreeAt() const;
void printParams() const;
void printQs() const;
/**
* The controller's main read and write queues
*/
std::list<DRAMPacket*> dramReadQueue;
std::list<DRAMPacket*> dramWriteQueue;
/**
* Response queue where read packets wait after we're done working
* with them, but it's not time to send the response yet.\ It is
* seperate mostly to keep the code clean and help with gem5 events,
* but for all logical purposes such as sizing the read queue, this
* and the main read queue need to be added together.
*/
std::list<DRAMPacket*> dramRespQueue;
/** If we need to drain, keep the drain event around until we're done
* here.
*/
Event *drainEvent;
/**
* Multi-dimensional vector of banks, first dimension is ranks,
* second is bank
*/
std::vector<std::vector<Bank> > banks;
/**
* The following are basic design parameters of the memory
* controller, and are initialized based on parameter values. The
* bytesPerCacheLine is based on the neighbouring port and thus
* determined outside the constructor. Similarly, the rowsPerBank
* is determined based on the capacity, number of ranks and banks,
* the cache line size, and the row buffer size.
*/
uint32_t bytesPerCacheLine;
const uint32_t linesPerRowBuffer;
const uint32_t ranksPerChannel;
const uint32_t banksPerRank;
uint32_t rowsPerBank;
const uint32_t readBufferSize;
const uint32_t writeBufferSize;
const double writeThresholdPerc;
uint32_t writeThreshold;
/**
* Basic memory timing parameters initialized based on parameter
* values.
*/
const Tick tWTR;
const Tick tBURST;
const Tick tRCD;
const Tick tCL;
const Tick tRP;
const Tick tRFC;
const Tick tREFI;
/**
* Memory controller configuration initialized based on parameter
* values.
*/
Enums::MemSched memSchedPolicy;
Enums::AddrMap addrMapping;
Enums::PageManage pageMgmt;
/**
* Till when has the main data bus been spoken for already?
*/
Tick busBusyUntil;
Tick prevdramaccess;
Tick writeStartTime;
Tick prevArrival;
int numReqs;
// All statistics that the model needs to capture
Stats::Scalar readReqs;
Stats::Scalar writeReqs;
Stats::Scalar cpuReqs;
Stats::Scalar bytesRead;
Stats::Scalar bytesWritten;
Stats::Scalar bytesConsumedRd;
Stats::Scalar bytesConsumedWr;
Stats::Scalar servicedByWrQ;
Stats::Scalar neitherReadNorWrite;
Stats::Vector perBankRdReqs;
Stats::Vector perBankWrReqs;
Stats::Scalar numRdRetry;
Stats::Scalar numWrRetry;
Stats::Scalar totGap;
Stats::Vector readPktSize;
Stats::Vector writePktSize;
Stats::Vector neitherPktSize;
Stats::Vector rdQLenPdf;
Stats::Vector wrQLenPdf;
// Latencies summed over all requests
Stats::Scalar totQLat;
Stats::Scalar totMemAccLat;
Stats::Scalar totBusLat;
Stats::Scalar totBankLat;
// Average latencies per request
Stats::Formula avgQLat;
Stats::Formula avgBankLat;
Stats::Formula avgBusLat;
Stats::Formula avgMemAccLat;
// Average bandwidth
Stats::Formula avgRdBW;
Stats::Formula avgWrBW;
Stats::Formula avgConsumedRdBW;
Stats::Formula avgConsumedWrBW;
Stats::Formula peakBW;
Stats::Formula busUtil;
// Average queue lengths
Stats::Average avgRdQLen;
Stats::Average avgWrQLen;
// Row hit count and rate
Stats::Scalar readRowHits;
Stats::Scalar writeRowHits;
Stats::Formula readRowHitRate;
Stats::Formula writeRowHitRate;
Stats::Formula avgGap;
public:
void regStats();
SimpleDRAM(const SimpleDRAMParams* p);
unsigned int drain(Event* de);
virtual SlavePort& getSlavePort(const std::string& if_name,
int idx = InvalidPortID);
virtual void init();
virtual void startup();
protected:
Tick recvAtomic(PacketPtr pkt);
void recvFunctional(PacketPtr pkt);
bool recvTimingReq(PacketPtr pkt);
};
#endif //__MEM_SIMPLE_DRAM_HH__