2012-09-21 17:48:13 +02:00
|
|
|
/*
|
2014-05-10 00:58:48 +02:00
|
|
|
* Copyright (c) 2010-2014 ARM Limited
|
2012-09-21 17:48:13 +02:00
|
|
|
* All rights reserved
|
|
|
|
*
|
|
|
|
* The license below extends only to copyright in the software and shall
|
|
|
|
* not be construed as granting a license to any other intellectual
|
|
|
|
* property including but not limited to intellectual property relating
|
|
|
|
* to a hardware implementation of the functionality of the software
|
|
|
|
* licensed hereunder. You may use the software subject to the license
|
|
|
|
* terms below provided that you ensure that this notice is replicated
|
|
|
|
* unmodified and in its entirety in all distributions of the software,
|
|
|
|
* modified or unmodified, in source code or in binary form.
|
|
|
|
*
|
2013-08-19 09:52:30 +02:00
|
|
|
* Copyright (c) 2013 Amin Farmahini-Farahani
|
|
|
|
* All rights reserved.
|
|
|
|
*
|
2012-09-21 17:48:13 +02:00
|
|
|
* Redistribution and use in source and binary forms, with or without
|
|
|
|
* modification, are permitted provided that the following conditions are
|
|
|
|
* met: redistributions of source code must retain the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer;
|
|
|
|
* redistributions in binary form must reproduce the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
|
|
* documentation and/or other materials provided with the distribution;
|
|
|
|
* neither the name of the copyright holders nor the names of its
|
|
|
|
* contributors may be used to endorse or promote products derived from
|
|
|
|
* this software without specific prior written permission.
|
|
|
|
*
|
|
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
|
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
|
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
|
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
*
|
|
|
|
* Authors: Andreas Hansson
|
|
|
|
* Ani Udipi
|
2013-11-01 16:56:20 +01:00
|
|
|
* Neha Agarwal
|
2012-09-21 17:48:13 +02:00
|
|
|
*/
|
|
|
|
|
2013-11-01 16:56:20 +01:00
|
|
|
#include "base/bitfield.hh"
|
2014-03-23 16:12:12 +01:00
|
|
|
#include "base/trace.hh"
|
2012-09-21 17:48:13 +02:00
|
|
|
#include "debug/DRAM.hh"
|
2014-06-30 19:56:03 +02:00
|
|
|
#include "debug/DRAMPower.hh"
|
2014-05-10 00:58:48 +02:00
|
|
|
#include "debug/DRAMState.hh"
|
2014-03-23 16:12:12 +01:00
|
|
|
#include "debug/Drain.hh"
|
|
|
|
#include "mem/dram_ctrl.hh"
|
2013-07-18 14:31:16 +02:00
|
|
|
#include "sim/system.hh"
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
using namespace std;
|
|
|
|
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) :
|
2012-09-21 17:48:13 +02:00
|
|
|
AbstractMemory(p),
|
|
|
|
port(name() + ".port", *this),
|
|
|
|
retryRdReq(false), retryWrReq(false),
|
2014-05-10 00:58:48 +02:00
|
|
|
busState(READ),
|
2014-05-10 00:58:48 +02:00
|
|
|
nextReqEvent(this), respondEvent(this), activateEvent(this),
|
|
|
|
prechargeEvent(this), refreshEvent(this), powerEvent(this),
|
|
|
|
drainManager(NULL),
|
2013-08-19 09:52:30 +02:00
|
|
|
deviceBusWidth(p->device_bus_width), burstLength(p->burst_length),
|
|
|
|
deviceRowBufferSize(p->device_rowbuffer_size),
|
|
|
|
devicesPerRank(p->devices_per_rank),
|
|
|
|
burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8),
|
|
|
|
rowBufferSize(devicesPerRank * deviceRowBufferSize),
|
2014-03-23 16:12:01 +01:00
|
|
|
columnsPerRowBuffer(rowBufferSize / burstSize),
|
2014-08-26 16:12:45 +02:00
|
|
|
columnsPerStripe(range.granularity() / burstSize),
|
2012-09-21 17:48:13 +02:00
|
|
|
ranksPerChannel(p->ranks_per_channel),
|
2013-03-01 19:20:22 +01:00
|
|
|
banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0),
|
2012-09-21 17:48:13 +02:00
|
|
|
readBufferSize(p->read_buffer_size),
|
|
|
|
writeBufferSize(p->write_buffer_size),
|
2014-03-23 16:12:01 +01:00
|
|
|
writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0),
|
|
|
|
writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0),
|
2014-03-23 16:12:14 +01:00
|
|
|
minWritesPerSwitch(p->min_writes_per_switch),
|
|
|
|
writesThisTime(0), readsThisTime(0),
|
2014-05-10 00:58:49 +02:00
|
|
|
tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tBURST(p->tBURST),
|
2014-05-10 00:58:48 +02:00
|
|
|
tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), tWR(p->tWR),
|
2014-05-10 00:58:48 +02:00
|
|
|
tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD),
|
2013-01-31 13:49:14 +01:00
|
|
|
tXAW(p->tXAW), activationLimit(p->activation_limit),
|
2012-09-21 17:48:13 +02:00
|
|
|
memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping),
|
|
|
|
pageMgmt(p->page_policy),
|
2014-03-23 16:12:03 +01:00
|
|
|
maxAccessesPerRow(p->max_accesses_per_row),
|
2013-05-30 18:54:12 +02:00
|
|
|
frontendLatency(p->static_frontend_latency),
|
|
|
|
backendLatency(p->static_backend_latency),
|
2014-05-10 00:58:48 +02:00
|
|
|
busBusyUntil(0), refreshDueAt(0), refreshState(REF_IDLE),
|
|
|
|
pwrStateTrans(PWR_IDLE), pwrState(PWR_IDLE), prevArrival(0),
|
|
|
|
nextReqTime(0), pwrStateTick(0), numBanksActive(0)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
// create the bank states based on the dimensions of the ranks and
|
|
|
|
// banks
|
|
|
|
banks.resize(ranksPerChannel);
|
2013-11-01 16:56:22 +01:00
|
|
|
actTicks.resize(ranksPerChannel);
|
2012-09-21 17:48:13 +02:00
|
|
|
for (size_t c = 0; c < ranksPerChannel; ++c) {
|
|
|
|
banks[c].resize(banksPerRank);
|
2013-11-01 16:56:22 +01:00
|
|
|
actTicks[c].resize(activationLimit, 0);
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
2014-06-30 19:56:02 +02:00
|
|
|
// set the bank indices
|
|
|
|
for (int r = 0; r < ranksPerChannel; r++) {
|
|
|
|
for (int b = 0; b < banksPerRank; b++) {
|
|
|
|
banks[r][b].rank = r;
|
|
|
|
banks[r][b].bank = b;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-03-23 16:12:01 +01:00
|
|
|
// perform a basic check of the write thresholds
|
|
|
|
if (p->write_low_thresh_perc >= p->write_high_thresh_perc)
|
|
|
|
fatal("Write buffer low threshold %d must be smaller than the "
|
|
|
|
"high threshold %d\n", p->write_low_thresh_perc,
|
|
|
|
p->write_high_thresh_perc);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
// determine the rows per bank by looking at the total capacity
|
2013-03-01 19:20:24 +01:00
|
|
|
uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size());
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity,
|
|
|
|
AbstractMemory::size());
|
2013-08-19 09:52:30 +02:00
|
|
|
|
|
|
|
DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n",
|
|
|
|
rowBufferSize, columnsPerRowBuffer);
|
|
|
|
|
|
|
|
rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2014-08-26 16:12:45 +02:00
|
|
|
// a bit of sanity checks on the interleaving
|
2013-03-01 19:20:22 +01:00
|
|
|
if (range.interleaved()) {
|
|
|
|
if (channels != range.stripes())
|
2014-03-23 16:12:06 +01:00
|
|
|
fatal("%s has %d interleaved address stripes but %d channel(s)\n",
|
2013-03-01 19:20:22 +01:00
|
|
|
name(), range.stripes(), channels);
|
|
|
|
|
2014-03-23 16:11:53 +01:00
|
|
|
if (addrMapping == Enums::RoRaBaChCo) {
|
2013-08-19 09:52:30 +02:00
|
|
|
if (rowBufferSize != range.granularity()) {
|
2014-08-26 16:12:45 +02:00
|
|
|
fatal("Channel interleaving of %s doesn't match RoRaBaChCo "
|
2014-03-23 16:11:53 +01:00
|
|
|
"address map\n", name());
|
2013-03-01 19:20:22 +01:00
|
|
|
}
|
2014-08-26 16:12:45 +02:00
|
|
|
} else if (addrMapping == Enums::RoRaBaCoCh ||
|
|
|
|
addrMapping == Enums::RoCoRaBaCh) {
|
|
|
|
// for the interleavings with channel bits in the bottom,
|
|
|
|
// if the system uses a channel striping granularity that
|
|
|
|
// is larger than the DRAM burst size, then map the
|
|
|
|
// sequential accesses within a stripe to a number of
|
|
|
|
// columns in the DRAM, effectively placing some of the
|
|
|
|
// lower-order column bits as the least-significant bits
|
|
|
|
// of the address (above the ones denoting the burst size)
|
|
|
|
assert(columnsPerStripe >= 1);
|
|
|
|
|
|
|
|
// channel striping has to be done at a granularity that
|
|
|
|
// is equal or larger to a cache line
|
|
|
|
if (system()->cacheLineSize() > range.granularity()) {
|
|
|
|
fatal("Channel interleaving of %s must be at least as large "
|
|
|
|
"as the cache line size\n", name());
|
2013-04-22 19:20:34 +02:00
|
|
|
}
|
2014-08-26 16:12:45 +02:00
|
|
|
|
|
|
|
// ...and equal or smaller than the row-buffer size
|
|
|
|
if (rowBufferSize < range.granularity()) {
|
|
|
|
fatal("Channel interleaving of %s must be at most as large "
|
|
|
|
"as the row-buffer size\n", name());
|
|
|
|
}
|
|
|
|
// this is essentially the check above, so just to be sure
|
|
|
|
assert(columnsPerStripe <= columnsPerRowBuffer);
|
2013-03-01 19:20:22 +01:00
|
|
|
}
|
|
|
|
}
|
2014-05-10 00:58:48 +02:00
|
|
|
|
|
|
|
// some basic sanity checks
|
|
|
|
if (tREFI <= tRP || tREFI <= tRFC) {
|
|
|
|
fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n",
|
|
|
|
tREFI, tRP, tRFC);
|
|
|
|
}
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
2014-03-23 16:12:01 +01:00
|
|
|
void
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::init()
|
2014-03-23 16:12:01 +01:00
|
|
|
{
|
|
|
|
if (!port.isConnected()) {
|
2014-03-23 16:12:12 +01:00
|
|
|
fatal("DRAMCtrl %s is unconnected!\n", name());
|
2014-03-23 16:12:01 +01:00
|
|
|
} else {
|
|
|
|
port.sendRangeChange();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-09-21 17:48:13 +02:00
|
|
|
void
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::startup()
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
2014-03-23 16:12:06 +01:00
|
|
|
// update the start tick for the precharge accounting to the
|
|
|
|
// current tick
|
2014-05-10 00:58:48 +02:00
|
|
|
pwrStateTick = curTick();
|
2014-03-23 16:12:06 +01:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// shift the bus busy time sufficiently far ahead that we never
|
|
|
|
// have to worry about negative values when computing the time for
|
|
|
|
// the next request, this will add an insignificant bubble at the
|
|
|
|
// start of simulation
|
|
|
|
busBusyUntil = curTick() + tRP + tRCD + tCL;
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// kick off the refresh, and give ourselves enough time to
|
|
|
|
// precharge
|
|
|
|
schedule(refreshEvent, curTick() + tREFI - tRP);
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
Tick
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::recvAtomic(PacketPtr pkt)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr());
|
|
|
|
|
|
|
|
// do the actual memory access and turn the packet into a response
|
|
|
|
access(pkt);
|
|
|
|
|
|
|
|
Tick latency = 0;
|
|
|
|
if (!pkt->memInhibitAsserted() && pkt->hasData()) {
|
|
|
|
// this value is not supposed to be accurate, just enough to
|
|
|
|
// keep things going, mimic a closed page
|
|
|
|
latency = tRP + tRCD + tCL;
|
|
|
|
}
|
|
|
|
return latency;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::readQueueFull(unsigned int neededEntries) const
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
2013-08-19 09:52:30 +02:00
|
|
|
DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n",
|
|
|
|
readBufferSize, readQueue.size() + respQueue.size(),
|
|
|
|
neededEntries);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
return
|
|
|
|
(readQueue.size() + respQueue.size() + neededEntries) > readBufferSize;
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::writeQueueFull(unsigned int neededEntries) const
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
2013-08-19 09:52:30 +02:00
|
|
|
DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n",
|
|
|
|
writeBufferSize, writeQueue.size(), neededEntries);
|
|
|
|
return (writeQueue.size() + neededEntries) > writeBufferSize;
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::DRAMPacket*
|
|
|
|
DRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size,
|
2014-03-23 16:12:06 +01:00
|
|
|
bool isRead)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
2013-04-22 19:20:34 +02:00
|
|
|
// decode the address based on the address mapping scheme, with
|
2014-03-23 16:11:53 +01:00
|
|
|
// Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and
|
|
|
|
// channel, respectively
|
2012-09-21 17:48:13 +02:00
|
|
|
uint8_t rank;
|
2013-11-01 16:56:20 +01:00
|
|
|
uint8_t bank;
|
2014-06-30 19:56:01 +02:00
|
|
|
// use a 64-bit unsigned during the computations as the row is
|
|
|
|
// always the top bits, and check before creating the DRAMPacket
|
|
|
|
uint64_t row;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2014-08-26 16:12:45 +02:00
|
|
|
// truncate the address to a DRAM burst, which makes it unique to
|
|
|
|
// a specific column, row, bank, rank and channel
|
2013-08-19 09:52:30 +02:00
|
|
|
Addr addr = dramPktAddr / burstSize;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-01-31 13:49:18 +01:00
|
|
|
// we have removed the lowest order address bits that denote the
|
2013-08-19 09:52:30 +02:00
|
|
|
// position within the column
|
2014-03-23 16:11:53 +01:00
|
|
|
if (addrMapping == Enums::RoRaBaChCo) {
|
2013-01-31 13:49:18 +01:00
|
|
|
// the lowest order bits denote the column to ensure that
|
|
|
|
// sequential cache lines occupy the same row
|
2013-08-19 09:52:30 +02:00
|
|
|
addr = addr / columnsPerRowBuffer;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-04-22 19:20:34 +02:00
|
|
|
// take out the channel part of the address
|
|
|
|
addr = addr / channels;
|
|
|
|
|
|
|
|
// after the channel bits, get the bank bits to interleave
|
|
|
|
// over the banks
|
|
|
|
bank = addr % banksPerRank;
|
|
|
|
addr = addr / banksPerRank;
|
|
|
|
|
|
|
|
// after the bank, we get the rank bits which thus interleaves
|
|
|
|
// over the ranks
|
|
|
|
rank = addr % ranksPerChannel;
|
|
|
|
addr = addr / ranksPerChannel;
|
|
|
|
|
|
|
|
// lastly, get the row bits
|
|
|
|
row = addr % rowsPerBank;
|
|
|
|
addr = addr / rowsPerBank;
|
2014-03-23 16:11:53 +01:00
|
|
|
} else if (addrMapping == Enums::RoRaBaCoCh) {
|
2014-08-26 16:12:45 +02:00
|
|
|
// take out the lower-order column bits
|
|
|
|
addr = addr / columnsPerStripe;
|
|
|
|
|
2013-04-22 19:20:34 +02:00
|
|
|
// take out the channel part of the address
|
2013-03-01 19:20:22 +01:00
|
|
|
addr = addr / channels;
|
|
|
|
|
2014-08-26 16:12:45 +02:00
|
|
|
// next, the higher-order column bites
|
|
|
|
addr = addr / (columnsPerRowBuffer / columnsPerStripe);
|
2013-04-22 19:20:34 +02:00
|
|
|
|
|
|
|
// after the column bits, we get the bank bits to interleave
|
2013-01-31 13:49:18 +01:00
|
|
|
// over the banks
|
2012-09-21 17:48:13 +02:00
|
|
|
bank = addr % banksPerRank;
|
|
|
|
addr = addr / banksPerRank;
|
|
|
|
|
2013-01-31 13:49:18 +01:00
|
|
|
// after the bank, we get the rank bits which thus interleaves
|
|
|
|
// over the ranks
|
2012-09-21 17:48:13 +02:00
|
|
|
rank = addr % ranksPerChannel;
|
|
|
|
addr = addr / ranksPerChannel;
|
|
|
|
|
2013-01-31 13:49:18 +01:00
|
|
|
// lastly, get the row bits
|
2012-09-21 17:48:13 +02:00
|
|
|
row = addr % rowsPerBank;
|
|
|
|
addr = addr / rowsPerBank;
|
2014-03-23 16:11:53 +01:00
|
|
|
} else if (addrMapping == Enums::RoCoRaBaCh) {
|
2013-01-31 13:49:18 +01:00
|
|
|
// optimise for closed page mode and utilise maximum
|
|
|
|
// parallelism of the DRAM (at the cost of power)
|
|
|
|
|
2014-08-26 16:12:45 +02:00
|
|
|
// take out the lower-order column bits
|
|
|
|
addr = addr / columnsPerStripe;
|
|
|
|
|
2013-03-01 19:20:22 +01:00
|
|
|
// take out the channel part of the address, not that this has
|
|
|
|
// to match with how accesses are interleaved between the
|
|
|
|
// controllers in the address mapping
|
|
|
|
addr = addr / channels;
|
|
|
|
|
2013-01-31 13:49:18 +01:00
|
|
|
// start with the bank bits, as this provides the maximum
|
|
|
|
// opportunity for parallelism between requests
|
2012-09-21 17:48:13 +02:00
|
|
|
bank = addr % banksPerRank;
|
|
|
|
addr = addr / banksPerRank;
|
|
|
|
|
2013-01-31 13:49:18 +01:00
|
|
|
// next get the rank bits
|
2012-09-21 17:48:13 +02:00
|
|
|
rank = addr % ranksPerChannel;
|
|
|
|
addr = addr / ranksPerChannel;
|
|
|
|
|
2014-08-26 16:12:45 +02:00
|
|
|
// next, the higher-order column bites
|
|
|
|
addr = addr / (columnsPerRowBuffer / columnsPerStripe);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-01-31 13:49:18 +01:00
|
|
|
// lastly, get the row bits
|
2012-09-21 17:48:13 +02:00
|
|
|
row = addr % rowsPerBank;
|
|
|
|
addr = addr / rowsPerBank;
|
|
|
|
} else
|
|
|
|
panic("Unknown address mapping policy chosen!");
|
|
|
|
|
|
|
|
assert(rank < ranksPerChannel);
|
|
|
|
assert(bank < banksPerRank);
|
|
|
|
assert(row < rowsPerBank);
|
2014-06-30 19:56:01 +02:00
|
|
|
assert(row < Bank::NO_ROW);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n",
|
2013-08-19 09:52:30 +02:00
|
|
|
dramPktAddr, rank, bank, row);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
// create the corresponding DRAM packet with the entry time and
|
2013-03-01 19:20:24 +01:00
|
|
|
// ready time set to the current tick, the latter will be updated
|
|
|
|
// later
|
2013-11-01 16:56:20 +01:00
|
|
|
uint16_t bank_id = banksPerRank * rank + bank;
|
|
|
|
return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr,
|
|
|
|
size, banks[rank][bank]);
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
// only add to the read queue here. whenever the request is
|
|
|
|
// eventually done, set the readyTime, and call schedule()
|
|
|
|
assert(!pkt->isWrite());
|
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
assert(pktCount != 0);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
// if the request size is larger than burst size, the pkt is split into
|
|
|
|
// multiple DRAM packets
|
|
|
|
// Note if the pkt starting address is not aligened to burst size, the
|
|
|
|
// address of first DRAM packet is kept unaliged. Subsequent DRAM packets
|
|
|
|
// are aligned to burst size boundaries. This is to ensure we accurately
|
|
|
|
// check read packets against packets in write queue.
|
|
|
|
Addr addr = pkt->getAddr();
|
|
|
|
unsigned pktsServicedByWrQ = 0;
|
|
|
|
BurstHelper* burst_helper = NULL;
|
|
|
|
for (int cnt = 0; cnt < pktCount; ++cnt) {
|
|
|
|
unsigned size = std::min((addr | (burstSize - 1)) + 1,
|
|
|
|
pkt->getAddr() + pkt->getSize()) - addr;
|
|
|
|
readPktSize[ceilLog2(size)]++;
|
|
|
|
readBursts++;
|
|
|
|
|
|
|
|
// First check write buffer to see if the data is already at
|
|
|
|
// the controller
|
|
|
|
bool foundInWrQ = false;
|
2013-08-19 09:52:32 +02:00
|
|
|
for (auto i = writeQueue.begin(); i != writeQueue.end(); ++i) {
|
2013-08-19 09:52:31 +02:00
|
|
|
// check if the read is subsumed in the write entry we are
|
|
|
|
// looking at
|
|
|
|
if ((*i)->addr <= addr &&
|
|
|
|
(addr + size) <= ((*i)->addr + (*i)->size)) {
|
2013-08-19 09:52:30 +02:00
|
|
|
foundInWrQ = true;
|
|
|
|
servicedByWrQ++;
|
|
|
|
pktsServicedByWrQ++;
|
|
|
|
DPRINTF(DRAM, "Read to addr %lld with size %d serviced by "
|
|
|
|
"write queue\n", addr, size);
|
2013-11-01 16:56:28 +01:00
|
|
|
bytesReadWrQ += burstSize;
|
2013-08-19 09:52:30 +02:00
|
|
|
break;
|
|
|
|
}
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
// If not found in the write q, make a DRAM packet and
|
|
|
|
// push it onto the read queue
|
|
|
|
if (!foundInWrQ) {
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
// Make the burst helper for split packets
|
|
|
|
if (pktCount > 1 && burst_helper == NULL) {
|
|
|
|
DPRINTF(DRAM, "Read to addr %lld translates to %d "
|
|
|
|
"dram requests\n", pkt->getAddr(), pktCount);
|
|
|
|
burst_helper = new BurstHelper(pktCount);
|
|
|
|
}
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-11-01 16:56:19 +01:00
|
|
|
DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true);
|
2013-08-19 09:52:30 +02:00
|
|
|
dram_pkt->burstHelper = burst_helper;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
assert(!readQueueFull(1));
|
|
|
|
rdQLenPdf[readQueue.size() + respQueue.size()]++;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
DPRINTF(DRAM, "Adding to read queue\n");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
readQueue.push_back(dram_pkt);
|
|
|
|
|
|
|
|
// Update stats
|
|
|
|
avgRdQLen = readQueue.size() + respQueue.size();
|
|
|
|
}
|
|
|
|
|
|
|
|
// Starting address of next dram pkt (aligend to burstSize boundary)
|
|
|
|
addr = (addr | (burstSize - 1)) + 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
// If all packets are serviced by write queue, we send the repsonse back
|
|
|
|
if (pktsServicedByWrQ == pktCount) {
|
|
|
|
accessAndRespond(pkt, frontendLatency);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Update how many split packets are serviced by write queue
|
|
|
|
if (burst_helper != NULL)
|
|
|
|
burst_helper->burstsServiced = pktsServicedByWrQ;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// If we are not already scheduled to get a request out of the
|
|
|
|
// queue, do so now
|
|
|
|
if (!nextReqEvent.scheduled()) {
|
2013-03-01 19:20:24 +01:00
|
|
|
DPRINTF(DRAM, "Request scheduled immediately\n");
|
|
|
|
schedule(nextReqEvent, curTick());
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
// only add to the write queue here. whenever the request is
|
|
|
|
// eventually done, set the readyTime, and call schedule()
|
|
|
|
assert(pkt->isWrite());
|
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
// if the request size is larger than burst size, the pkt is split into
|
|
|
|
// multiple DRAM packets
|
|
|
|
Addr addr = pkt->getAddr();
|
|
|
|
for (int cnt = 0; cnt < pktCount; ++cnt) {
|
|
|
|
unsigned size = std::min((addr | (burstSize - 1)) + 1,
|
|
|
|
pkt->getAddr() + pkt->getSize()) - addr;
|
|
|
|
writePktSize[ceilLog2(size)]++;
|
|
|
|
writeBursts++;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-08-19 09:52:31 +02:00
|
|
|
// see if we can merge with an existing item in the write
|
2013-08-19 09:52:36 +02:00
|
|
|
// queue and keep track of whether we have merged or not so we
|
|
|
|
// can stop at that point and also avoid enqueueing a new
|
|
|
|
// request
|
2013-08-19 09:52:31 +02:00
|
|
|
bool merged = false;
|
|
|
|
auto w = writeQueue.begin();
|
|
|
|
|
|
|
|
while(!merged && w != writeQueue.end()) {
|
|
|
|
// either of the two could be first, if they are the same
|
|
|
|
// it does not matter which way we go
|
|
|
|
if ((*w)->addr >= addr) {
|
2013-08-19 09:52:36 +02:00
|
|
|
// the existing one starts after the new one, figure
|
|
|
|
// out where the new one ends with respect to the
|
|
|
|
// existing one
|
2013-08-19 09:52:31 +02:00
|
|
|
if ((addr + size) >= ((*w)->addr + (*w)->size)) {
|
|
|
|
// check if the existing one is completely
|
|
|
|
// subsumed in the new one
|
|
|
|
DPRINTF(DRAM, "Merging write covering existing burst\n");
|
|
|
|
merged = true;
|
|
|
|
// update both the address and the size
|
|
|
|
(*w)->addr = addr;
|
|
|
|
(*w)->size = size;
|
|
|
|
} else if ((addr + size) >= (*w)->addr &&
|
|
|
|
((*w)->addr + (*w)->size - addr) <= burstSize) {
|
|
|
|
// the new one is just before or partially
|
|
|
|
// overlapping with the existing one, and together
|
|
|
|
// they fit within a burst
|
|
|
|
DPRINTF(DRAM, "Merging write before existing burst\n");
|
|
|
|
merged = true;
|
|
|
|
// the existing queue item needs to be adjusted with
|
|
|
|
// respect to both address and size
|
|
|
|
(*w)->size = (*w)->addr + (*w)->size - addr;
|
2014-01-29 01:00:49 +01:00
|
|
|
(*w)->addr = addr;
|
2013-08-19 09:52:31 +02:00
|
|
|
}
|
|
|
|
} else {
|
2013-08-19 09:52:36 +02:00
|
|
|
// the new one starts after the current one, figure
|
|
|
|
// out where the existing one ends with respect to the
|
|
|
|
// new one
|
2013-08-19 09:52:31 +02:00
|
|
|
if (((*w)->addr + (*w)->size) >= (addr + size)) {
|
|
|
|
// check if the new one is completely subsumed in the
|
|
|
|
// existing one
|
|
|
|
DPRINTF(DRAM, "Merging write into existing burst\n");
|
|
|
|
merged = true;
|
|
|
|
// no adjustments necessary
|
|
|
|
} else if (((*w)->addr + (*w)->size) >= addr &&
|
|
|
|
(addr + size - (*w)->addr) <= burstSize) {
|
|
|
|
// the existing one is just before or partially
|
|
|
|
// overlapping with the new one, and together
|
|
|
|
// they fit within a burst
|
|
|
|
DPRINTF(DRAM, "Merging write after existing burst\n");
|
|
|
|
merged = true;
|
|
|
|
// the address is right, and only the size has
|
|
|
|
// to be adjusted
|
|
|
|
(*w)->size = addr + size - (*w)->addr;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
++w;
|
|
|
|
}
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-08-19 09:52:31 +02:00
|
|
|
// if the item was not merged we need to create a new write
|
|
|
|
// and enqueue it
|
|
|
|
if (!merged) {
|
2013-11-01 16:56:19 +01:00
|
|
|
DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-08-19 09:52:31 +02:00
|
|
|
assert(writeQueue.size() < writeBufferSize);
|
|
|
|
wrQLenPdf[writeQueue.size()]++;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-08-19 09:52:31 +02:00
|
|
|
DPRINTF(DRAM, "Adding to write queue\n");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-08-19 09:52:31 +02:00
|
|
|
writeQueue.push_back(dram_pkt);
|
2013-08-19 09:52:30 +02:00
|
|
|
|
2013-08-19 09:52:31 +02:00
|
|
|
// Update stats
|
|
|
|
avgWrQLen = writeQueue.size();
|
2013-11-01 16:56:31 +01:00
|
|
|
} else {
|
|
|
|
// keep track of the fact that this burst effectively
|
|
|
|
// disappeared as it was merged with an existing one
|
|
|
|
mergedWrBursts++;
|
2013-08-19 09:52:31 +02:00
|
|
|
}
|
2013-08-19 09:52:30 +02:00
|
|
|
|
|
|
|
// Starting address of next dram pkt (aligend to burstSize boundary)
|
|
|
|
addr = (addr | (burstSize - 1)) + 1;
|
|
|
|
}
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
// we do not wait for the writes to be send to the actual memory,
|
|
|
|
// but instead take responsibility for the consistency here and
|
|
|
|
// snoop the write queue for any upcoming reads
|
2013-08-19 09:52:30 +02:00
|
|
|
// @todo, if a pkt size is larger than burst size, we might need a
|
|
|
|
// different front end latency
|
2013-05-30 18:54:12 +02:00
|
|
|
accessAndRespond(pkt, frontendLatency);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// If we are not already scheduled to get a request out of the
|
|
|
|
// queue, do so now
|
|
|
|
if (!nextReqEvent.scheduled()) {
|
|
|
|
DPRINTF(DRAM, "Request scheduled immediately\n");
|
|
|
|
schedule(nextReqEvent, curTick());
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::printQs() const {
|
2012-09-21 17:48:13 +02:00
|
|
|
DPRINTF(DRAM, "===READ QUEUE===\n\n");
|
2013-08-19 09:52:32 +02:00
|
|
|
for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) {
|
2012-09-21 17:48:13 +02:00
|
|
|
DPRINTF(DRAM, "Read %lu\n", (*i)->addr);
|
|
|
|
}
|
|
|
|
DPRINTF(DRAM, "\n===RESP QUEUE===\n\n");
|
2013-08-19 09:52:32 +02:00
|
|
|
for (auto i = respQueue.begin() ; i != respQueue.end() ; ++i) {
|
2012-09-21 17:48:13 +02:00
|
|
|
DPRINTF(DRAM, "Response %lu\n", (*i)->addr);
|
|
|
|
}
|
|
|
|
DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n");
|
2013-08-19 09:52:32 +02:00
|
|
|
for (auto i = writeQueue.begin() ; i != writeQueue.end() ; ++i) {
|
2012-09-21 17:48:13 +02:00
|
|
|
DPRINTF(DRAM, "Write %lu\n", (*i)->addr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::recvTimingReq(PacketPtr pkt)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
2012-11-02 17:50:16 +01:00
|
|
|
/// @todo temporary hack to deal with memory corruption issues until
|
|
|
|
/// 4-phase transactions are complete
|
|
|
|
for (int x = 0; x < pendingDelete.size(); x++)
|
|
|
|
delete pendingDelete[x];
|
|
|
|
pendingDelete.clear();
|
|
|
|
|
2012-09-21 17:48:13 +02:00
|
|
|
// This is where we enter from the outside world
|
2013-03-01 19:20:24 +01:00
|
|
|
DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n",
|
2013-08-19 09:52:30 +02:00
|
|
|
pkt->cmdString(), pkt->getAddr(), pkt->getSize());
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-03-01 19:20:24 +01:00
|
|
|
// simply drop inhibited packets for now
|
|
|
|
if (pkt->memInhibitAsserted()) {
|
2014-03-23 16:12:06 +01:00
|
|
|
DPRINTF(DRAM, "Inhibited packet -- Dropping it now\n");
|
2013-03-01 19:20:24 +01:00
|
|
|
pendingDelete.push_back(pkt);
|
|
|
|
return true;
|
|
|
|
}
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
// Calc avg gap between requests
|
|
|
|
if (prevArrival != 0) {
|
|
|
|
totGap += curTick() - prevArrival;
|
|
|
|
}
|
|
|
|
prevArrival = curTick();
|
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
|
|
|
|
// Find out how many dram packets a pkt translates to
|
|
|
|
// If the burst size is equal or larger than the pkt size, then a pkt
|
|
|
|
// translates to only one dram packet. Otherwise, a pkt translates to
|
|
|
|
// multiple dram packets
|
2012-09-21 17:48:13 +02:00
|
|
|
unsigned size = pkt->getSize();
|
2013-08-19 09:52:30 +02:00
|
|
|
unsigned offset = pkt->getAddr() & (burstSize - 1);
|
|
|
|
unsigned int dram_pkt_count = divCeil(offset + size, burstSize);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
// check local buffers and do not accept if full
|
|
|
|
if (pkt->isRead()) {
|
2013-03-01 19:20:24 +01:00
|
|
|
assert(size != 0);
|
2013-08-19 09:52:30 +02:00
|
|
|
if (readQueueFull(dram_pkt_count)) {
|
2013-03-01 19:20:24 +01:00
|
|
|
DPRINTF(DRAM, "Read queue full, not accepting\n");
|
2012-09-21 17:48:13 +02:00
|
|
|
// remember that we have to retry this port
|
|
|
|
retryRdReq = true;
|
|
|
|
numRdRetry++;
|
|
|
|
return false;
|
|
|
|
} else {
|
2013-08-19 09:52:30 +02:00
|
|
|
addToReadQueue(pkt, dram_pkt_count);
|
2012-09-21 17:48:13 +02:00
|
|
|
readReqs++;
|
2013-11-01 16:56:31 +01:00
|
|
|
bytesReadSys += size;
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
} else if (pkt->isWrite()) {
|
2013-03-01 19:20:24 +01:00
|
|
|
assert(size != 0);
|
2013-08-19 09:52:30 +02:00
|
|
|
if (writeQueueFull(dram_pkt_count)) {
|
2013-03-01 19:20:24 +01:00
|
|
|
DPRINTF(DRAM, "Write queue full, not accepting\n");
|
2012-09-21 17:48:13 +02:00
|
|
|
// remember that we have to retry this port
|
|
|
|
retryWrReq = true;
|
|
|
|
numWrRetry++;
|
|
|
|
return false;
|
|
|
|
} else {
|
2013-08-19 09:52:30 +02:00
|
|
|
addToWriteQueue(pkt, dram_pkt_count);
|
2012-09-21 17:48:13 +02:00
|
|
|
writeReqs++;
|
2013-11-01 16:56:31 +01:00
|
|
|
bytesWrittenSys += size;
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
DPRINTF(DRAM,"Neither read nor write, ignore timing\n");
|
|
|
|
neitherReadNorWrite++;
|
2013-05-30 18:54:12 +02:00
|
|
|
accessAndRespond(pkt, 1);
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::processRespondEvent()
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
DPRINTF(DRAM,
|
|
|
|
"processRespondEvent(): Some req has reached its readyTime\n");
|
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
DRAMPacket* dram_pkt = respQueue.front();
|
|
|
|
|
|
|
|
if (dram_pkt->burstHelper) {
|
|
|
|
// it is a split packet
|
|
|
|
dram_pkt->burstHelper->burstsServiced++;
|
|
|
|
if (dram_pkt->burstHelper->burstsServiced ==
|
2014-03-23 16:12:06 +01:00
|
|
|
dram_pkt->burstHelper->burstCount) {
|
2013-08-19 09:52:30 +02:00
|
|
|
// we have now serviced all children packets of a system packet
|
|
|
|
// so we can now respond to the requester
|
|
|
|
// @todo we probably want to have a different front end and back
|
|
|
|
// end latency for split packets
|
|
|
|
accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency);
|
|
|
|
delete dram_pkt->burstHelper;
|
|
|
|
dram_pkt->burstHelper = NULL;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
// it is not a split packet
|
|
|
|
accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency);
|
|
|
|
}
|
|
|
|
|
|
|
|
delete respQueue.front();
|
|
|
|
respQueue.pop_front();
|
|
|
|
|
|
|
|
if (!respQueue.empty()) {
|
|
|
|
assert(respQueue.front()->readyTime >= curTick());
|
|
|
|
assert(!respondEvent.scheduled());
|
|
|
|
schedule(respondEvent, respQueue.front()->readyTime);
|
|
|
|
} else {
|
|
|
|
// if there is nothing left in any queue, signal a drain
|
|
|
|
if (writeQueue.empty() && readQueue.empty() &&
|
|
|
|
drainManager) {
|
|
|
|
drainManager->signalDrainDone();
|
|
|
|
drainManager = NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// We have made a location in the queue available at this point,
|
|
|
|
// so if there is a read that was forced to wait, retry now
|
|
|
|
if (retryRdReq) {
|
|
|
|
retryRdReq = false;
|
|
|
|
port.sendRetry();
|
|
|
|
}
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2014-05-10 00:58:48 +02:00
|
|
|
DRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
2014-05-10 00:58:48 +02:00
|
|
|
// This method does the arbitration between requests. The chosen
|
|
|
|
// packet is simply moved to the head of the queue. The other
|
|
|
|
// methods know that this is the place to look. For example, with
|
|
|
|
// FCFS, this method does nothing
|
|
|
|
assert(!queue.empty());
|
|
|
|
|
|
|
|
if (queue.size() == 1) {
|
|
|
|
DPRINTF(DRAM, "Single request, nothing to do\n");
|
2012-09-21 17:48:13 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (memSchedPolicy == Enums::fcfs) {
|
|
|
|
// Do nothing, since the correct request is already head
|
|
|
|
} else if (memSchedPolicy == Enums::frfcfs) {
|
2014-05-10 00:58:48 +02:00
|
|
|
reorderQueue(queue);
|
2012-09-21 17:48:13 +02:00
|
|
|
} else
|
|
|
|
panic("No scheduling policy chosen\n");
|
|
|
|
}
|
|
|
|
|
2013-11-01 16:56:27 +01:00
|
|
|
void
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue)
|
2013-11-01 16:56:27 +01:00
|
|
|
{
|
|
|
|
// Only determine this when needed
|
|
|
|
uint64_t earliest_banks = 0;
|
|
|
|
|
|
|
|
// Search for row hits first, if no row hit is found then schedule the
|
|
|
|
// packet to one of the earliest banks available
|
|
|
|
bool found_earliest_pkt = false;
|
|
|
|
auto selected_pkt_it = queue.begin();
|
|
|
|
|
|
|
|
for (auto i = queue.begin(); i != queue.end() ; ++i) {
|
|
|
|
DRAMPacket* dram_pkt = *i;
|
|
|
|
const Bank& bank = dram_pkt->bankRef;
|
|
|
|
// Check if it is a row hit
|
|
|
|
if (bank.openRow == dram_pkt->row) {
|
2014-05-10 00:58:48 +02:00
|
|
|
// FCFS within the hits
|
2013-11-01 16:56:27 +01:00
|
|
|
DPRINTF(DRAM, "Row buffer hit\n");
|
|
|
|
selected_pkt_it = i;
|
|
|
|
break;
|
|
|
|
} else if (!found_earliest_pkt) {
|
|
|
|
// No row hit, go for first ready
|
|
|
|
if (earliest_banks == 0)
|
2014-05-10 00:58:48 +02:00
|
|
|
earliest_banks = minBankActAt(queue);
|
|
|
|
|
|
|
|
// simplistic approximation of when the bank can issue an
|
|
|
|
// activate, this is calculated in minBankActAt and could
|
|
|
|
// be cached
|
|
|
|
Tick act_at = bank.openRow == Bank::NO_ROW ?
|
|
|
|
bank.actAllowedAt :
|
|
|
|
std::max(bank.preAllowedAt, curTick()) + tRP;
|
2013-11-01 16:56:27 +01:00
|
|
|
|
|
|
|
// Bank is ready or is the first available bank
|
2014-05-10 00:58:48 +02:00
|
|
|
if (act_at <= curTick() ||
|
2013-11-01 16:56:27 +01:00
|
|
|
bits(earliest_banks, dram_pkt->bankId, dram_pkt->bankId)) {
|
|
|
|
// Remember the packet to be scheduled to one of the earliest
|
2014-05-10 00:58:48 +02:00
|
|
|
// banks available, FCFS amongst the earliest banks
|
2013-11-01 16:56:27 +01:00
|
|
|
selected_pkt_it = i;
|
|
|
|
found_earliest_pkt = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
DRAMPacket* selected_pkt = *selected_pkt_it;
|
|
|
|
queue.erase(selected_pkt_it);
|
|
|
|
queue.push_front(selected_pkt);
|
|
|
|
}
|
|
|
|
|
2012-09-21 17:48:13 +02:00
|
|
|
void
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr());
|
|
|
|
|
|
|
|
bool needsResponse = pkt->needsResponse();
|
|
|
|
// do the actual memory access which also turns the packet into a
|
|
|
|
// response
|
|
|
|
access(pkt);
|
|
|
|
|
|
|
|
// turn packet around to go back to requester if response expected
|
|
|
|
if (needsResponse) {
|
|
|
|
// access already turned the packet into a response
|
|
|
|
assert(pkt->isResponse());
|
|
|
|
|
2013-02-19 11:56:06 +01:00
|
|
|
// @todo someone should pay for this
|
|
|
|
pkt->busFirstWordDelay = pkt->busLastWordDelay = 0;
|
|
|
|
|
2013-05-30 18:54:12 +02:00
|
|
|
// queue the packet in the response queue to be sent out after
|
|
|
|
// the static latency has passed
|
|
|
|
port.schedTimingResp(pkt, curTick() + static_latency);
|
2012-09-21 17:48:13 +02:00
|
|
|
} else {
|
2013-03-18 10:22:45 +01:00
|
|
|
// @todo the packet is going to be deleted, and the DRAMPacket
|
|
|
|
// is still having a pointer to it
|
|
|
|
pendingDelete.push_back(pkt);
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
DPRINTF(DRAM, "Done\n");
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2013-01-31 13:49:14 +01:00
|
|
|
void
|
2014-06-30 19:56:02 +02:00
|
|
|
DRAMCtrl::activateBank(Bank& bank, Tick act_tick, uint32_t row)
|
2013-01-31 13:49:14 +01:00
|
|
|
{
|
2014-06-30 19:56:02 +02:00
|
|
|
// get the rank index from the bank
|
|
|
|
uint8_t rank = bank.rank;
|
|
|
|
|
2013-11-01 16:56:22 +01:00
|
|
|
assert(actTicks[rank].size() == activationLimit);
|
2013-01-31 13:49:14 +01:00
|
|
|
|
|
|
|
DPRINTF(DRAM, "Activate at tick %d\n", act_tick);
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// update the open row
|
2014-06-30 19:56:02 +02:00
|
|
|
assert(bank.openRow == Bank::NO_ROW);
|
|
|
|
bank.openRow = row;
|
2014-05-10 00:58:48 +02:00
|
|
|
|
|
|
|
// start counting anew, this covers both the case when we
|
|
|
|
// auto-precharged, and when this access is forced to
|
|
|
|
// precharge
|
2014-06-30 19:56:02 +02:00
|
|
|
bank.bytesAccessed = 0;
|
|
|
|
bank.rowAccesses = 0;
|
2014-05-10 00:58:48 +02:00
|
|
|
|
|
|
|
++numBanksActive;
|
|
|
|
assert(numBanksActive <= banksPerRank * ranksPerChannel);
|
|
|
|
|
2014-06-30 19:56:03 +02:00
|
|
|
DPRINTF(DRAM, "Activate bank %d, rank %d at tick %lld, now got %d active\n",
|
|
|
|
bank.bank, bank.rank, act_tick, numBanksActive);
|
|
|
|
|
|
|
|
DPRINTF(DRAMPower, "%llu,ACT,%d,%d\n", divCeil(act_tick, tCK), bank.bank,
|
|
|
|
bank.rank);
|
2013-11-01 16:56:28 +01:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// The next access has to respect tRAS for this bank
|
2014-06-30 19:56:02 +02:00
|
|
|
bank.preAllowedAt = act_tick + tRAS;
|
2014-05-10 00:58:48 +02:00
|
|
|
|
|
|
|
// Respect the row-to-column command delay
|
2014-06-30 19:56:02 +02:00
|
|
|
bank.colAllowedAt = act_tick + tRCD;
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2013-11-01 16:56:24 +01:00
|
|
|
// start by enforcing tRRD
|
|
|
|
for(int i = 0; i < banksPerRank; i++) {
|
2014-05-10 00:58:48 +02:00
|
|
|
// next activate to any bank in this rank must not happen
|
|
|
|
// before tRRD
|
|
|
|
banks[rank][i].actAllowedAt = std::max(act_tick + tRRD,
|
|
|
|
banks[rank][i].actAllowedAt);
|
2013-11-01 16:56:24 +01:00
|
|
|
}
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2013-11-01 16:56:24 +01:00
|
|
|
// next, we deal with tXAW, if the activation limit is disabled
|
|
|
|
// then we are done
|
2013-11-01 16:56:22 +01:00
|
|
|
if (actTicks[rank].empty())
|
2013-08-19 09:52:26 +02:00
|
|
|
return;
|
|
|
|
|
2013-01-31 13:49:14 +01:00
|
|
|
// sanity check
|
2013-11-01 16:56:22 +01:00
|
|
|
if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) {
|
2014-05-10 00:58:48 +02:00
|
|
|
panic("Got %d activates in window %d (%llu - %llu) which is smaller "
|
|
|
|
"than %llu\n", activationLimit, act_tick - actTicks[rank].back(),
|
|
|
|
act_tick, actTicks[rank].back(), tXAW);
|
2013-01-31 13:49:14 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
// shift the times used for the book keeping, the last element
|
|
|
|
// (highest index) is the oldest one and hence the lowest value
|
2013-11-01 16:56:22 +01:00
|
|
|
actTicks[rank].pop_back();
|
2013-01-31 13:49:14 +01:00
|
|
|
|
|
|
|
// record an new activation (in the future)
|
2013-11-01 16:56:22 +01:00
|
|
|
actTicks[rank].push_front(act_tick);
|
2013-01-31 13:49:14 +01:00
|
|
|
|
|
|
|
// cannot activate more than X times in time window tXAW, push the
|
|
|
|
// next one (the X + 1'st activate) to be tXAW away from the
|
|
|
|
// oldest in our window of X
|
2013-11-01 16:56:22 +01:00
|
|
|
if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) {
|
2013-01-31 13:49:14 +01:00
|
|
|
DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate no earlier "
|
2014-05-10 00:58:48 +02:00
|
|
|
"than %llu\n", activationLimit, actTicks[rank].back() + tXAW);
|
2013-01-31 13:49:14 +01:00
|
|
|
for(int j = 0; j < banksPerRank; j++)
|
|
|
|
// next activate must not happen before end of window
|
2014-05-10 00:58:48 +02:00
|
|
|
banks[rank][j].actAllowedAt =
|
|
|
|
std::max(actTicks[rank].back() + tXAW,
|
|
|
|
banks[rank][j].actAllowedAt);
|
2013-01-31 13:49:14 +01:00
|
|
|
}
|
2014-05-10 00:58:48 +02:00
|
|
|
|
|
|
|
// at the point when this activate takes place, make sure we
|
|
|
|
// transition to the active power state
|
|
|
|
if (!activateEvent.scheduled())
|
|
|
|
schedule(activateEvent, act_tick);
|
|
|
|
else if (activateEvent.when() > act_tick)
|
|
|
|
// move it sooner in time
|
|
|
|
reschedule(activateEvent, act_tick);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
DRAMCtrl::processActivateEvent()
|
|
|
|
{
|
|
|
|
// we should transition to the active state as soon as any bank is active
|
|
|
|
if (pwrState != PWR_ACT)
|
|
|
|
// note that at this point numBanksActive could be back at
|
|
|
|
// zero again due to a precharge scheduled in the future
|
|
|
|
schedulePowerEvent(PWR_ACT, curTick());
|
2013-01-31 13:49:14 +01:00
|
|
|
}
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
void
|
2014-06-30 19:56:03 +02:00
|
|
|
DRAMCtrl::prechargeBank(Bank& bank, Tick pre_at, bool trace)
|
2014-05-10 00:58:48 +02:00
|
|
|
{
|
|
|
|
// make sure the bank has an open row
|
|
|
|
assert(bank.openRow != Bank::NO_ROW);
|
|
|
|
|
|
|
|
// sample the bytes per activate here since we are closing
|
|
|
|
// the page
|
|
|
|
bytesPerActivate.sample(bank.bytesAccessed);
|
|
|
|
|
|
|
|
bank.openRow = Bank::NO_ROW;
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// no precharge allowed before this one
|
|
|
|
bank.preAllowedAt = pre_at;
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
Tick pre_done_at = pre_at + tRP;
|
|
|
|
|
|
|
|
bank.actAllowedAt = std::max(bank.actAllowedAt, pre_done_at);
|
2014-05-10 00:58:48 +02:00
|
|
|
|
|
|
|
assert(numBanksActive != 0);
|
|
|
|
--numBanksActive;
|
|
|
|
|
2014-06-30 19:56:03 +02:00
|
|
|
DPRINTF(DRAM, "Precharging bank %d, rank %d at tick %lld, now got "
|
|
|
|
"%d active\n", bank.bank, bank.rank, pre_at, numBanksActive);
|
|
|
|
|
|
|
|
if (trace)
|
|
|
|
DPRINTF(DRAMPower, "%llu,PRE,%d,%d\n", divCeil(pre_at, tCK),
|
|
|
|
bank.bank, bank.rank);
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// if we look at the current number of active banks we might be
|
|
|
|
// tempted to think the DRAM is now idle, however this can be
|
|
|
|
// undone by an activate that is scheduled to happen before we
|
|
|
|
// would have reached the idle state, so schedule an event and
|
|
|
|
// rather check once we actually make it to the point in time when
|
|
|
|
// the (last) precharge takes place
|
|
|
|
if (!prechargeEvent.scheduled())
|
2014-05-10 00:58:48 +02:00
|
|
|
schedule(prechargeEvent, pre_done_at);
|
|
|
|
else if (prechargeEvent.when() < pre_done_at)
|
|
|
|
reschedule(prechargeEvent, pre_done_at);
|
2014-05-10 00:58:48 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
DRAMCtrl::processPrechargeEvent()
|
|
|
|
{
|
2014-05-10 00:58:48 +02:00
|
|
|
// if we reached zero, then special conditions apply as we track
|
|
|
|
// if all banks are precharged for the power models
|
|
|
|
if (numBanksActive == 0) {
|
2014-05-10 00:58:48 +02:00
|
|
|
// we should transition to the idle state when the last bank
|
|
|
|
// is precharged
|
|
|
|
schedulePowerEvent(PWR_IDLE, curTick());
|
2014-05-10 00:58:48 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-09-21 17:48:13 +02:00
|
|
|
void
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n",
|
|
|
|
dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row);
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// get the bank
|
|
|
|
Bank& bank = dram_pkt->bankRef;
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// for the state we need to track if it is a row hit or not
|
|
|
|
bool row_hit = true;
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// respect any constraints on the command (e.g. tRCD or tCCD)
|
|
|
|
Tick cmd_at = std::max(bank.colAllowedAt, curTick());
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// Determine the access latency and update the bank state
|
|
|
|
if (bank.openRow == dram_pkt->row) {
|
|
|
|
// nothing to do
|
2014-05-10 00:58:48 +02:00
|
|
|
} else {
|
2014-05-10 00:58:48 +02:00
|
|
|
row_hit = false;
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// If there is a page open, precharge it.
|
|
|
|
if (bank.openRow != Bank::NO_ROW) {
|
2014-05-10 00:58:48 +02:00
|
|
|
prechargeBank(bank, std::max(bank.preAllowedAt, curTick()));
|
2013-01-31 13:49:14 +01:00
|
|
|
}
|
2013-11-01 16:56:26 +01:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// next we need to account for the delay in activating the
|
|
|
|
// page
|
|
|
|
Tick act_tick = std::max(bank.actAllowedAt, curTick());
|
2014-03-23 16:12:03 +01:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// Record the activation and deal with all the global timing
|
|
|
|
// constraints caused be a new activation (tRRD and tXAW)
|
2014-06-30 19:56:02 +02:00
|
|
|
activateBank(bank, act_tick, dram_pkt->row);
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// issue the command as early as possible
|
|
|
|
cmd_at = bank.colAllowedAt;
|
2014-05-10 00:58:48 +02:00
|
|
|
}
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// we need to wait until the bus is available before we can issue
|
|
|
|
// the command
|
|
|
|
cmd_at = std::max(cmd_at, busBusyUntil - tCL);
|
|
|
|
|
|
|
|
// update the packet ready time
|
|
|
|
dram_pkt->readyTime = cmd_at + tCL + tBURST;
|
|
|
|
|
|
|
|
// only one burst can use the bus at any one point in time
|
|
|
|
assert(dram_pkt->readyTime - busBusyUntil >= tBURST);
|
|
|
|
|
|
|
|
// not strictly necessary, but update the time for the next
|
|
|
|
// read/write (add a max with tCCD here)
|
|
|
|
bank.colAllowedAt = cmd_at + tBURST;
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// If this is a write, we also need to respect the write recovery
|
|
|
|
// time before a precharge, in the case of a read, respect the
|
|
|
|
// read to precharge constraint
|
|
|
|
bank.preAllowedAt = std::max(bank.preAllowedAt,
|
|
|
|
dram_pkt->isRead ? cmd_at + tRTP :
|
|
|
|
dram_pkt->readyTime + tWR);
|
2014-03-23 16:12:05 +01:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// increment the bytes accessed and the accesses per row
|
|
|
|
bank.bytesAccessed += burstSize;
|
|
|
|
++bank.rowAccesses;
|
|
|
|
|
|
|
|
// if we reached the max, then issue with an auto-precharge
|
|
|
|
bool auto_precharge = pageMgmt == Enums::close ||
|
|
|
|
bank.rowAccesses == maxAccessesPerRow;
|
|
|
|
|
|
|
|
// if we did not hit the limit, we might still want to
|
|
|
|
// auto-precharge
|
|
|
|
if (!auto_precharge &&
|
|
|
|
(pageMgmt == Enums::open_adaptive ||
|
|
|
|
pageMgmt == Enums::close_adaptive)) {
|
|
|
|
// a twist on the open and close page policies:
|
|
|
|
// 1) open_adaptive page policy does not blindly keep the
|
|
|
|
// page open, but close it if there are no row hits, and there
|
|
|
|
// are bank conflicts in the queue
|
|
|
|
// 2) close_adaptive page policy does not blindly close the
|
|
|
|
// page, but closes it only if there are no row hits in the queue.
|
|
|
|
// In this case, only force an auto precharge when there
|
|
|
|
// are no same page hits in the queue
|
|
|
|
bool got_more_hits = false;
|
|
|
|
bool got_bank_conflict = false;
|
|
|
|
|
|
|
|
// either look at the read queue or write queue
|
|
|
|
const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue :
|
|
|
|
writeQueue;
|
|
|
|
auto p = queue.begin();
|
|
|
|
// make sure we are not considering the packet that we are
|
|
|
|
// currently dealing with (which is the head of the queue)
|
|
|
|
++p;
|
|
|
|
|
|
|
|
// keep on looking until we have found required condition or
|
|
|
|
// reached the end
|
|
|
|
while (!(got_more_hits &&
|
|
|
|
(got_bank_conflict || pageMgmt == Enums::close_adaptive)) &&
|
|
|
|
p != queue.end()) {
|
|
|
|
bool same_rank_bank = (dram_pkt->rank == (*p)->rank) &&
|
|
|
|
(dram_pkt->bank == (*p)->bank);
|
|
|
|
bool same_row = dram_pkt->row == (*p)->row;
|
|
|
|
got_more_hits |= same_rank_bank && same_row;
|
|
|
|
got_bank_conflict |= same_rank_bank && !same_row;
|
|
|
|
++p;
|
2013-11-01 16:56:26 +01:00
|
|
|
}
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// auto pre-charge when either
|
|
|
|
// 1) open_adaptive policy, we have not got any more hits, and
|
|
|
|
// have a bank conflict
|
|
|
|
// 2) close_adaptive policy and we have not got any more hits
|
|
|
|
auto_precharge = !got_more_hits &&
|
|
|
|
(got_bank_conflict || pageMgmt == Enums::close_adaptive);
|
|
|
|
}
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-06-30 19:56:03 +02:00
|
|
|
// DRAMPower trace command to be written
|
|
|
|
std::string mem_cmd = dram_pkt->isRead ? "RD" : "WR";
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// if this access should use auto-precharge, then we are
|
|
|
|
// closing the row
|
|
|
|
if (auto_precharge) {
|
2014-06-30 19:56:03 +02:00
|
|
|
prechargeBank(bank, std::max(curTick(), bank.preAllowedAt), false);
|
|
|
|
|
|
|
|
mem_cmd.append("A");
|
2013-11-01 16:56:16 +01:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId);
|
|
|
|
}
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2012-09-21 17:48:13 +02:00
|
|
|
// Update bus state
|
|
|
|
busBusyUntil = dram_pkt->readyTime;
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
DPRINTF(DRAM, "Access to %lld, ready at %lld bus busy until %lld.\n",
|
|
|
|
dram_pkt->addr, dram_pkt->readyTime, busBusyUntil);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2014-06-30 19:56:03 +02:00
|
|
|
DPRINTF(DRAMPower, "%llu,%s,%d,%d\n", divCeil(cmd_at, tCK), mem_cmd,
|
|
|
|
dram_pkt->bank, dram_pkt->rank);
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// Update the minimum timing between the requests, this is a
|
|
|
|
// conservative estimate of when we have to schedule the next
|
|
|
|
// request to not introduce any unecessary bubbles. In most cases
|
|
|
|
// we will wake up sooner than we have to.
|
|
|
|
nextReqTime = busBusyUntil - (tRP + tRCD + tCL);
|
2013-11-01 16:56:25 +01:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// Update the stats and schedule the next request
|
2013-11-01 16:56:31 +01:00
|
|
|
if (dram_pkt->isRead) {
|
2014-03-23 16:12:14 +01:00
|
|
|
++readsThisTime;
|
2014-05-10 00:58:48 +02:00
|
|
|
if (row_hit)
|
2013-11-01 16:56:31 +01:00
|
|
|
readRowHits++;
|
|
|
|
bytesReadDRAM += burstSize;
|
|
|
|
perBankRdBursts[dram_pkt->bankId]++;
|
2014-05-10 00:58:48 +02:00
|
|
|
|
|
|
|
// Update latency stats
|
|
|
|
totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime;
|
|
|
|
totBusLat += tBURST;
|
2014-05-10 00:58:48 +02:00
|
|
|
totQLat += cmd_at - dram_pkt->entryTime;
|
2013-11-01 16:56:31 +01:00
|
|
|
} else {
|
2014-03-23 16:12:14 +01:00
|
|
|
++writesThisTime;
|
2014-05-10 00:58:48 +02:00
|
|
|
if (row_hit)
|
2013-11-01 16:56:31 +01:00
|
|
|
writeRowHits++;
|
|
|
|
bytesWritten += burstSize;
|
|
|
|
perBankWrBursts[dram_pkt->bankId]++;
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2014-05-10 00:58:48 +02:00
|
|
|
DRAMCtrl::processNextReqEvent()
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
2014-05-10 00:58:48 +02:00
|
|
|
if (busState == READ_TO_WRITE) {
|
|
|
|
DPRINTF(DRAM, "Switching to writes after %d reads with %d reads "
|
|
|
|
"waiting\n", readsThisTime, readQueue.size());
|
|
|
|
|
|
|
|
// sample and reset the read-related stats as we are now
|
|
|
|
// transitioning to writes, and all reads are done
|
|
|
|
rdPerTurnAround.sample(readsThisTime);
|
|
|
|
readsThisTime = 0;
|
|
|
|
|
|
|
|
// now proceed to do the actual writes
|
|
|
|
busState = WRITE;
|
|
|
|
} else if (busState == WRITE_TO_READ) {
|
|
|
|
DPRINTF(DRAM, "Switching to reads after %d writes with %d writes "
|
|
|
|
"waiting\n", writesThisTime, writeQueue.size());
|
|
|
|
|
|
|
|
wrPerTurnAround.sample(writesThisTime);
|
|
|
|
writesThisTime = 0;
|
|
|
|
|
|
|
|
busState = READ;
|
|
|
|
}
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
if (refreshState != REF_IDLE) {
|
|
|
|
// if a refresh waiting for this event loop to finish, then hand
|
|
|
|
// over now, and do not schedule a new nextReqEvent
|
|
|
|
if (refreshState == REF_DRAIN) {
|
|
|
|
DPRINTF(DRAM, "Refresh drain done, now precharging\n");
|
|
|
|
|
|
|
|
refreshState = REF_PRE;
|
|
|
|
|
|
|
|
// hand control back to the refresh event loop
|
|
|
|
schedule(refreshEvent, curTick());
|
|
|
|
}
|
|
|
|
|
|
|
|
// let the refresh finish before issuing any further requests
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// when we get here it is either a read or a write
|
|
|
|
if (busState == READ) {
|
|
|
|
|
|
|
|
// track if we should switch or not
|
|
|
|
bool switch_to_writes = false;
|
|
|
|
|
|
|
|
if (readQueue.empty()) {
|
|
|
|
// In the case there is no read request to go next,
|
|
|
|
// trigger writes if we have passed the low threshold (or
|
|
|
|
// if we are draining)
|
|
|
|
if (!writeQueue.empty() &&
|
|
|
|
(drainManager || writeQueue.size() > writeLowThreshold)) {
|
|
|
|
|
|
|
|
switch_to_writes = true;
|
|
|
|
} else {
|
|
|
|
// check if we are drained
|
|
|
|
if (respQueue.empty () && drainManager) {
|
|
|
|
drainManager->signalDrainDone();
|
|
|
|
drainManager = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
// nothing to do, not even any point in scheduling an
|
|
|
|
// event for the next request
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
// Figure out which read request goes next, and move it to the
|
|
|
|
// front of the read queue
|
|
|
|
chooseNext(readQueue);
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
DRAMPacket* dram_pkt = readQueue.front();
|
|
|
|
|
|
|
|
doDRAMAccess(dram_pkt);
|
2014-05-10 00:58:48 +02:00
|
|
|
|
|
|
|
// At this point we're done dealing with the request
|
2014-05-10 00:58:48 +02:00
|
|
|
readQueue.pop_front();
|
|
|
|
|
|
|
|
// sanity check
|
|
|
|
assert(dram_pkt->size <= burstSize);
|
|
|
|
assert(dram_pkt->readyTime >= curTick());
|
|
|
|
|
|
|
|
// Insert into response queue. It will be sent back to the
|
|
|
|
// requestor at its readyTime
|
|
|
|
if (respQueue.empty()) {
|
|
|
|
assert(!respondEvent.scheduled());
|
|
|
|
schedule(respondEvent, dram_pkt->readyTime);
|
|
|
|
} else {
|
|
|
|
assert(respQueue.back()->readyTime <= dram_pkt->readyTime);
|
|
|
|
assert(respondEvent.scheduled());
|
|
|
|
}
|
|
|
|
|
|
|
|
respQueue.push_back(dram_pkt);
|
2014-05-10 00:58:48 +02:00
|
|
|
|
|
|
|
// we have so many writes that we have to transition
|
|
|
|
if (writeQueue.size() > writeHighThreshold) {
|
|
|
|
switch_to_writes = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// switching to writes, either because the read queue is empty
|
|
|
|
// and the writes have passed the low threshold (or we are
|
|
|
|
// draining), or because the writes hit the hight threshold
|
|
|
|
if (switch_to_writes) {
|
|
|
|
// transition to writing
|
|
|
|
busState = READ_TO_WRITE;
|
|
|
|
|
|
|
|
// add a bubble to the data bus, as defined by the
|
|
|
|
// tRTW parameter
|
|
|
|
busBusyUntil += tRTW;
|
|
|
|
|
|
|
|
// update the minimum timing between the requests,
|
|
|
|
// this shifts us back in time far enough to do any
|
|
|
|
// bank preparation
|
|
|
|
nextReqTime = busBusyUntil - (tRP + tRCD + tCL);
|
|
|
|
}
|
2012-11-08 10:25:06 +01:00
|
|
|
} else {
|
2014-05-10 00:58:48 +02:00
|
|
|
chooseNext(writeQueue);
|
|
|
|
DRAMPacket* dram_pkt = writeQueue.front();
|
|
|
|
// sanity check
|
|
|
|
assert(dram_pkt->size <= burstSize);
|
|
|
|
doDRAMAccess(dram_pkt);
|
|
|
|
|
|
|
|
writeQueue.pop_front();
|
|
|
|
delete dram_pkt;
|
|
|
|
|
|
|
|
// If we emptied the write queue, or got sufficiently below the
|
|
|
|
// threshold (using the minWritesPerSwitch as the hysteresis) and
|
|
|
|
// are not draining, or we have reads waiting and have done enough
|
|
|
|
// writes, then switch to reads.
|
|
|
|
if (writeQueue.empty() ||
|
|
|
|
(writeQueue.size() + minWritesPerSwitch < writeLowThreshold &&
|
|
|
|
!drainManager) ||
|
|
|
|
(!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) {
|
|
|
|
// turn the bus back around for reads again
|
|
|
|
busState = WRITE_TO_READ;
|
|
|
|
|
|
|
|
// note that the we switch back to reads also in the idle
|
|
|
|
// case, which eventually will check for any draining and
|
|
|
|
// also pause any further scheduling if there is really
|
|
|
|
// nothing to do
|
|
|
|
|
|
|
|
// here we get a bit creative and shift the bus busy time not
|
|
|
|
// just the tWTR, but also a CAS latency to capture the fact
|
|
|
|
// that we are allowed to prepare a new bank, but not issue a
|
|
|
|
// read command until after tWTR, in essence we capture a
|
|
|
|
// bubble on the data bus that is tWTR + tCL
|
|
|
|
busBusyUntil += tWTR + tCL;
|
|
|
|
|
|
|
|
// update the minimum timing between the requests, this shifts
|
|
|
|
// us back in time far enough to do any bank preparation
|
|
|
|
nextReqTime = busBusyUntil - (tRP + tRCD + tCL);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
schedule(nextReqEvent, std::max(nextReqTime, curTick()));
|
|
|
|
|
|
|
|
// If there is space available and we have writes waiting then let
|
|
|
|
// them retry. This is done here to ensure that the retry does not
|
|
|
|
// cause a nextReqEvent to be scheduled before we do so as part of
|
|
|
|
// the next request processing
|
|
|
|
if (retryWrReq && writeQueue.size() < writeBufferSize) {
|
|
|
|
retryWrReq = false;
|
|
|
|
port.sendRetry();
|
2012-11-08 10:25:06 +01:00
|
|
|
}
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
2013-11-01 16:56:20 +01:00
|
|
|
uint64_t
|
2014-05-10 00:58:48 +02:00
|
|
|
DRAMCtrl::minBankActAt(const deque<DRAMPacket*>& queue) const
|
2013-11-01 16:56:20 +01:00
|
|
|
{
|
|
|
|
uint64_t bank_mask = 0;
|
2014-05-10 00:58:48 +02:00
|
|
|
Tick min_act_at = MaxTick;
|
2013-11-01 16:56:20 +01:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// deterimne if we have queued transactions targetting a
|
2013-11-01 16:56:20 +01:00
|
|
|
// bank in question
|
|
|
|
vector<bool> got_waiting(ranksPerChannel * banksPerRank, false);
|
|
|
|
for (auto p = queue.begin(); p != queue.end(); ++p) {
|
|
|
|
got_waiting[(*p)->bankId] = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (int i = 0; i < ranksPerChannel; i++) {
|
|
|
|
for (int j = 0; j < banksPerRank; j++) {
|
2014-05-10 00:58:48 +02:00
|
|
|
uint8_t bank_id = i * banksPerRank + j;
|
|
|
|
|
2013-11-01 16:56:20 +01:00
|
|
|
// if we have waiting requests for the bank, and it is
|
|
|
|
// amongst the first available, update the mask
|
2014-05-10 00:58:48 +02:00
|
|
|
if (got_waiting[bank_id]) {
|
|
|
|
// simplistic approximation of when the bank can issue
|
|
|
|
// an activate, ignoring any rank-to-rank switching
|
|
|
|
// cost
|
|
|
|
Tick act_at = banks[i][j].openRow == Bank::NO_ROW ?
|
|
|
|
banks[i][j].actAllowedAt :
|
|
|
|
std::max(banks[i][j].preAllowedAt, curTick()) + tRP;
|
|
|
|
|
|
|
|
if (act_at <= min_act_at) {
|
|
|
|
// reset bank mask if new minimum is found
|
|
|
|
if (act_at < min_act_at)
|
|
|
|
bank_mask = 0;
|
|
|
|
// set the bit corresponding to the available bank
|
|
|
|
replaceBits(bank_mask, bank_id, bank_id, 1);
|
|
|
|
min_act_at = act_at;
|
|
|
|
}
|
2013-11-01 16:56:20 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2013-11-01 16:56:20 +01:00
|
|
|
return bank_mask;
|
|
|
|
}
|
|
|
|
|
2012-09-21 17:48:13 +02:00
|
|
|
void
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::processRefreshEvent()
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
2014-05-10 00:58:48 +02:00
|
|
|
// when first preparing the refresh, remember when it was due
|
|
|
|
if (refreshState == REF_IDLE) {
|
|
|
|
// remember when the refresh is due
|
|
|
|
refreshDueAt = curTick();
|
|
|
|
|
|
|
|
// proceed to drain
|
|
|
|
refreshState = REF_DRAIN;
|
|
|
|
|
|
|
|
DPRINTF(DRAM, "Refresh due\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
// let any scheduled read or write go ahead, after which it will
|
|
|
|
// hand control back to this event loop
|
|
|
|
if (refreshState == REF_DRAIN) {
|
|
|
|
if (nextReqEvent.scheduled()) {
|
|
|
|
// hand control over to the request loop until it is
|
|
|
|
// evaluated next
|
|
|
|
DPRINTF(DRAM, "Refresh awaiting draining\n");
|
|
|
|
|
|
|
|
return;
|
|
|
|
} else {
|
|
|
|
refreshState = REF_PRE;
|
|
|
|
}
|
|
|
|
}
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// at this point, ensure that all banks are precharged
|
|
|
|
if (refreshState == REF_PRE) {
|
2014-05-10 00:58:48 +02:00
|
|
|
// precharge any active bank if we are not already in the idle
|
|
|
|
// state
|
|
|
|
if (pwrState != PWR_IDLE) {
|
2014-05-10 00:58:48 +02:00
|
|
|
// at the moment, we use a precharge all even if there is
|
|
|
|
// only a single bank open
|
2014-05-10 00:58:48 +02:00
|
|
|
DPRINTF(DRAM, "Precharging all\n");
|
2014-05-10 00:58:48 +02:00
|
|
|
|
|
|
|
// first determine when we can precharge
|
|
|
|
Tick pre_at = curTick();
|
2014-05-10 00:58:48 +02:00
|
|
|
for (int i = 0; i < ranksPerChannel; i++) {
|
|
|
|
for (int j = 0; j < banksPerRank; j++) {
|
2014-05-10 00:58:48 +02:00
|
|
|
// respect both causality and any existing bank
|
|
|
|
// constraints, some banks could already have a
|
|
|
|
// (auto) precharge scheduled
|
|
|
|
pre_at = std::max(banks[i][j].preAllowedAt, pre_at);
|
|
|
|
}
|
|
|
|
}
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// make sure all banks are precharged, and for those that
|
|
|
|
// already are, update their availability
|
|
|
|
Tick act_allowed_at = pre_at + tRP;
|
|
|
|
|
|
|
|
for (int i = 0; i < ranksPerChannel; i++) {
|
|
|
|
for (int j = 0; j < banksPerRank; j++) {
|
|
|
|
if (banks[i][j].openRow != Bank::NO_ROW) {
|
2014-06-30 19:56:03 +02:00
|
|
|
prechargeBank(banks[i][j], pre_at, false);
|
2014-05-10 00:58:48 +02:00
|
|
|
} else {
|
|
|
|
banks[i][j].actAllowedAt =
|
|
|
|
std::max(banks[i][j].actAllowedAt, act_allowed_at);
|
|
|
|
banks[i][j].preAllowedAt =
|
|
|
|
std::max(banks[i][j].preAllowedAt, pre_at);
|
2014-05-10 00:58:48 +02:00
|
|
|
}
|
2014-05-10 00:58:48 +02:00
|
|
|
}
|
2014-06-30 19:56:03 +02:00
|
|
|
|
|
|
|
// at the moment this affects all ranks
|
|
|
|
DPRINTF(DRAMPower, "%llu,PREA,0,%d\n", divCeil(pre_at, tCK),
|
|
|
|
i);
|
2014-05-10 00:58:48 +02:00
|
|
|
}
|
2014-05-10 00:58:48 +02:00
|
|
|
} else {
|
|
|
|
DPRINTF(DRAM, "All banks already precharged, starting refresh\n");
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// go ahead and kick the power state machine into gear if
|
|
|
|
// we are already idle
|
|
|
|
schedulePowerEvent(PWR_REF, curTick());
|
|
|
|
}
|
2014-05-10 00:58:48 +02:00
|
|
|
|
|
|
|
refreshState = REF_RUN;
|
2014-05-10 00:58:48 +02:00
|
|
|
assert(numBanksActive == 0);
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// wait for all banks to be precharged, at which point the
|
|
|
|
// power state machine will transition to the idle state, and
|
|
|
|
// automatically move to a refresh, at that point it will also
|
|
|
|
// call this method to get the refresh event loop going again
|
2014-05-10 00:58:48 +02:00
|
|
|
return;
|
|
|
|
}
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// last but not least we perform the actual refresh
|
|
|
|
if (refreshState == REF_RUN) {
|
|
|
|
// should never get here with any banks active
|
|
|
|
assert(numBanksActive == 0);
|
2014-05-10 00:58:48 +02:00
|
|
|
assert(pwrState == PWR_REF);
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
Tick ref_done_at = curTick() + tRFC;
|
2014-05-10 00:58:48 +02:00
|
|
|
|
|
|
|
for (int i = 0; i < ranksPerChannel; i++) {
|
|
|
|
for (int j = 0; j < banksPerRank; j++) {
|
2014-05-10 00:58:48 +02:00
|
|
|
banks[i][j].actAllowedAt = ref_done_at;
|
2014-05-10 00:58:48 +02:00
|
|
|
}
|
2014-06-30 19:56:03 +02:00
|
|
|
|
|
|
|
// at the moment this affects all ranks
|
|
|
|
DPRINTF(DRAMPower, "%llu,REF,0,%d\n", divCeil(curTick(), tCK), i);
|
2014-05-10 00:58:48 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
// make sure we did not wait so long that we cannot make up
|
|
|
|
// for it
|
2014-05-10 00:58:48 +02:00
|
|
|
if (refreshDueAt + tREFI < ref_done_at) {
|
2014-05-10 00:58:48 +02:00
|
|
|
fatal("Refresh was delayed so long we cannot catch up\n");
|
2013-11-01 16:56:28 +01:00
|
|
|
}
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// compensate for the delay in actually performing the refresh
|
|
|
|
// when scheduling the next one
|
|
|
|
schedule(refreshEvent, refreshDueAt + tREFI - tRP);
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
assert(!powerEvent.scheduled());
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
// move to the idle power state once the refresh is done, this
|
|
|
|
// will also move the refresh state machine to the refresh
|
|
|
|
// idle state
|
2014-05-10 00:58:48 +02:00
|
|
|
schedulePowerEvent(PWR_IDLE, ref_done_at);
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
DPRINTF(DRAMState, "Refresh done at %llu and next refresh at %llu\n",
|
2014-05-10 00:58:48 +02:00
|
|
|
ref_done_at, refreshDueAt + tREFI);
|
2014-05-10 00:58:48 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
DRAMCtrl::schedulePowerEvent(PowerState pwr_state, Tick tick)
|
|
|
|
{
|
|
|
|
// respect causality
|
|
|
|
assert(tick >= curTick());
|
|
|
|
|
|
|
|
if (!powerEvent.scheduled()) {
|
|
|
|
DPRINTF(DRAMState, "Scheduling power event at %llu to state %d\n",
|
|
|
|
tick, pwr_state);
|
|
|
|
|
|
|
|
// insert the new transition
|
|
|
|
pwrStateTrans = pwr_state;
|
|
|
|
|
|
|
|
schedule(powerEvent, tick);
|
|
|
|
} else {
|
|
|
|
panic("Scheduled power event at %llu to state %d, "
|
|
|
|
"with scheduled event at %llu to %d\n", tick, pwr_state,
|
|
|
|
powerEvent.when(), pwrStateTrans);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
DRAMCtrl::processPowerEvent()
|
|
|
|
{
|
|
|
|
// remember where we were, and for how long
|
|
|
|
Tick duration = curTick() - pwrStateTick;
|
|
|
|
PowerState prev_state = pwrState;
|
|
|
|
|
|
|
|
// update the accounting
|
|
|
|
pwrStateTime[prev_state] += duration;
|
|
|
|
|
|
|
|
pwrState = pwrStateTrans;
|
|
|
|
pwrStateTick = curTick();
|
|
|
|
|
|
|
|
if (pwrState == PWR_IDLE) {
|
|
|
|
DPRINTF(DRAMState, "All banks precharged\n");
|
|
|
|
|
|
|
|
// if we were refreshing, make sure we start scheduling requests again
|
|
|
|
if (prev_state == PWR_REF) {
|
|
|
|
DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration);
|
|
|
|
assert(pwrState == PWR_IDLE);
|
|
|
|
|
|
|
|
// kick things into action again
|
|
|
|
refreshState = REF_IDLE;
|
|
|
|
assert(!nextReqEvent.scheduled());
|
|
|
|
schedule(nextReqEvent, curTick());
|
|
|
|
} else {
|
|
|
|
assert(prev_state == PWR_ACT);
|
|
|
|
|
|
|
|
// if we have a pending refresh, and are now moving to
|
|
|
|
// the idle state, direclty transition to a refresh
|
|
|
|
if (refreshState == REF_RUN) {
|
|
|
|
// there should be nothing waiting at this point
|
|
|
|
assert(!powerEvent.scheduled());
|
|
|
|
|
|
|
|
// update the state in zero time and proceed below
|
|
|
|
pwrState = PWR_REF;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// we transition to the refresh state, let the refresh state
|
|
|
|
// machine know of this state update and let it deal with the
|
|
|
|
// scheduling of the next power state transition as well as the
|
|
|
|
// following refresh
|
|
|
|
if (pwrState == PWR_REF) {
|
|
|
|
DPRINTF(DRAMState, "Refreshing\n");
|
|
|
|
// kick the refresh event loop into action again, and that
|
|
|
|
// in turn will schedule a transition to the idle power
|
|
|
|
// state once the refresh is done
|
|
|
|
assert(refreshState == REF_RUN);
|
|
|
|
processRefreshEvent();
|
2014-05-10 00:58:48 +02:00
|
|
|
}
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::regStats()
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
using namespace Stats;
|
|
|
|
|
|
|
|
AbstractMemory::regStats();
|
|
|
|
|
|
|
|
readReqs
|
|
|
|
.name(name() + ".readReqs")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Number of read requests accepted");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
writeReqs
|
|
|
|
.name(name() + ".writeReqs")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Number of write requests accepted");
|
2013-08-19 09:52:30 +02:00
|
|
|
|
|
|
|
readBursts
|
|
|
|
.name(name() + ".readBursts")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Number of DRAM read bursts, "
|
|
|
|
"including those serviced by the write queue");
|
2013-08-19 09:52:30 +02:00
|
|
|
|
|
|
|
writeBursts
|
|
|
|
.name(name() + ".writeBursts")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Number of DRAM write bursts, "
|
|
|
|
"including those merged in the write queue");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
servicedByWrQ
|
|
|
|
.name(name() + ".servicedByWrQ")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Number of DRAM read bursts serviced by the write queue");
|
|
|
|
|
|
|
|
mergedWrBursts
|
|
|
|
.name(name() + ".mergedWrBursts")
|
|
|
|
.desc("Number of DRAM write bursts merged with an existing one");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
neitherReadNorWrite
|
2013-11-01 16:56:31 +01:00
|
|
|
.name(name() + ".neitherReadNorWriteReqs")
|
|
|
|
.desc("Number of requests that are neither read nor write");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-11-01 16:56:31 +01:00
|
|
|
perBankRdBursts
|
2012-09-21 17:48:13 +02:00
|
|
|
.init(banksPerRank * ranksPerChannel)
|
2013-11-01 16:56:31 +01:00
|
|
|
.name(name() + ".perBankRdBursts")
|
|
|
|
.desc("Per bank write bursts");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-11-01 16:56:31 +01:00
|
|
|
perBankWrBursts
|
2012-09-21 17:48:13 +02:00
|
|
|
.init(banksPerRank * ranksPerChannel)
|
2013-11-01 16:56:31 +01:00
|
|
|
.name(name() + ".perBankWrBursts")
|
|
|
|
.desc("Per bank write bursts");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
avgRdQLen
|
|
|
|
.name(name() + ".avgRdQLen")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Average read queue length when enqueuing")
|
2012-09-21 17:48:13 +02:00
|
|
|
.precision(2);
|
|
|
|
|
|
|
|
avgWrQLen
|
|
|
|
.name(name() + ".avgWrQLen")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Average write queue length when enqueuing")
|
2012-09-21 17:48:13 +02:00
|
|
|
.precision(2);
|
|
|
|
|
|
|
|
totQLat
|
|
|
|
.name(name() + ".totQLat")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Total ticks spent queuing");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
totBusLat
|
|
|
|
.name(name() + ".totBusLat")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Total ticks spent in databus transfers");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
totMemAccLat
|
|
|
|
.name(name() + ".totMemAccLat")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Total ticks spent from burst creation until serviced "
|
|
|
|
"by the DRAM");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
avgQLat
|
|
|
|
.name(name() + ".avgQLat")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Average queueing delay per DRAM burst")
|
2012-09-21 17:48:13 +02:00
|
|
|
.precision(2);
|
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
avgQLat = totQLat / (readBursts - servicedByWrQ);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
avgBusLat
|
|
|
|
.name(name() + ".avgBusLat")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Average bus latency per DRAM burst")
|
2012-09-21 17:48:13 +02:00
|
|
|
.precision(2);
|
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
avgBusLat = totBusLat / (readBursts - servicedByWrQ);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
avgMemAccLat
|
|
|
|
.name(name() + ".avgMemAccLat")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Average memory access latency per DRAM burst")
|
2012-09-21 17:48:13 +02:00
|
|
|
.precision(2);
|
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
numRdRetry
|
|
|
|
.name(name() + ".numRdRetry")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Number of times read queue was full causing retry");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
numWrRetry
|
|
|
|
.name(name() + ".numWrRetry")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Number of times write queue was full causing retry");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
readRowHits
|
|
|
|
.name(name() + ".readRowHits")
|
|
|
|
.desc("Number of row buffer hits during reads");
|
|
|
|
|
|
|
|
writeRowHits
|
|
|
|
.name(name() + ".writeRowHits")
|
|
|
|
.desc("Number of row buffer hits during writes");
|
|
|
|
|
|
|
|
readRowHitRate
|
|
|
|
.name(name() + ".readRowHitRate")
|
|
|
|
.desc("Row buffer hit rate for reads")
|
|
|
|
.precision(2);
|
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
writeRowHitRate
|
|
|
|
.name(name() + ".writeRowHitRate")
|
|
|
|
.desc("Row buffer hit rate for writes")
|
|
|
|
.precision(2);
|
|
|
|
|
2013-11-01 16:56:31 +01:00
|
|
|
writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
readPktSize
|
2013-08-19 09:52:30 +02:00
|
|
|
.init(ceilLog2(burstSize) + 1)
|
2012-09-21 17:48:13 +02:00
|
|
|
.name(name() + ".readPktSize")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Read request sizes (log2)");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
writePktSize
|
2013-08-19 09:52:30 +02:00
|
|
|
.init(ceilLog2(burstSize) + 1)
|
2012-09-21 17:48:13 +02:00
|
|
|
.name(name() + ".writePktSize")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Write request sizes (log2)");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
rdQLenPdf
|
2013-03-01 19:20:24 +01:00
|
|
|
.init(readBufferSize)
|
2012-09-21 17:48:13 +02:00
|
|
|
.name(name() + ".rdQLenPdf")
|
|
|
|
.desc("What read queue length does an incoming req see");
|
|
|
|
|
|
|
|
wrQLenPdf
|
2013-03-01 19:20:24 +01:00
|
|
|
.init(writeBufferSize)
|
2012-09-21 17:48:13 +02:00
|
|
|
.name(name() + ".wrQLenPdf")
|
|
|
|
.desc("What write queue length does an incoming req see");
|
|
|
|
|
2013-05-30 18:54:13 +02:00
|
|
|
bytesPerActivate
|
2014-03-23 16:12:03 +01:00
|
|
|
.init(maxAccessesPerRow)
|
2013-05-30 18:54:13 +02:00
|
|
|
.name(name() + ".bytesPerActivate")
|
|
|
|
.desc("Bytes accessed per row activation")
|
|
|
|
.flags(nozero);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2014-03-23 16:12:14 +01:00
|
|
|
rdPerTurnAround
|
|
|
|
.init(readBufferSize)
|
|
|
|
.name(name() + ".rdPerTurnAround")
|
|
|
|
.desc("Reads before turning the bus around for writes")
|
|
|
|
.flags(nozero);
|
|
|
|
|
|
|
|
wrPerTurnAround
|
|
|
|
.init(writeBufferSize)
|
|
|
|
.name(name() + ".wrPerTurnAround")
|
|
|
|
.desc("Writes before turning the bus around for reads")
|
|
|
|
.flags(nozero);
|
|
|
|
|
2013-11-01 16:56:28 +01:00
|
|
|
bytesReadDRAM
|
|
|
|
.name(name() + ".bytesReadDRAM")
|
|
|
|
.desc("Total number of bytes read from DRAM");
|
|
|
|
|
|
|
|
bytesReadWrQ
|
|
|
|
.name(name() + ".bytesReadWrQ")
|
|
|
|
.desc("Total number of bytes read from write queue");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
bytesWritten
|
|
|
|
.name(name() + ".bytesWritten")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Total number of bytes written to DRAM");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-11-01 16:56:31 +01:00
|
|
|
bytesReadSys
|
|
|
|
.name(name() + ".bytesReadSys")
|
|
|
|
.desc("Total read bytes from the system interface side");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-11-01 16:56:31 +01:00
|
|
|
bytesWrittenSys
|
|
|
|
.name(name() + ".bytesWrittenSys")
|
|
|
|
.desc("Total written bytes from the system interface side");
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
avgRdBW
|
|
|
|
.name(name() + ".avgRdBW")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Average DRAM read bandwidth in MiByte/s")
|
2012-09-21 17:48:13 +02:00
|
|
|
.precision(2);
|
|
|
|
|
2013-11-01 16:56:31 +01:00
|
|
|
avgRdBW = (bytesReadDRAM / 1000000) / simSeconds;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
avgWrBW
|
|
|
|
.name(name() + ".avgWrBW")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Average achieved write bandwidth in MiByte/s")
|
2012-09-21 17:48:13 +02:00
|
|
|
.precision(2);
|
|
|
|
|
|
|
|
avgWrBW = (bytesWritten / 1000000) / simSeconds;
|
|
|
|
|
2013-11-01 16:56:31 +01:00
|
|
|
avgRdBWSys
|
|
|
|
.name(name() + ".avgRdBWSys")
|
|
|
|
.desc("Average system read bandwidth in MiByte/s")
|
2012-09-21 17:48:13 +02:00
|
|
|
.precision(2);
|
|
|
|
|
2013-11-01 16:56:31 +01:00
|
|
|
avgRdBWSys = (bytesReadSys / 1000000) / simSeconds;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-11-01 16:56:31 +01:00
|
|
|
avgWrBWSys
|
|
|
|
.name(name() + ".avgWrBWSys")
|
|
|
|
.desc("Average system write bandwidth in MiByte/s")
|
2012-09-21 17:48:13 +02:00
|
|
|
.precision(2);
|
|
|
|
|
2013-11-01 16:56:31 +01:00
|
|
|
avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
peakBW
|
|
|
|
.name(name() + ".peakBW")
|
2013-11-01 16:56:31 +01:00
|
|
|
.desc("Theoretical peak bandwidth in MiByte/s")
|
2012-09-21 17:48:13 +02:00
|
|
|
.precision(2);
|
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
busUtil
|
|
|
|
.name(name() + ".busUtil")
|
|
|
|
.desc("Data bus utilization in percentage")
|
|
|
|
.precision(2);
|
|
|
|
|
|
|
|
busUtil = (avgRdBW + avgWrBW) / peakBW * 100;
|
|
|
|
|
|
|
|
totGap
|
|
|
|
.name(name() + ".totGap")
|
|
|
|
.desc("Total gap between requests");
|
|
|
|
|
|
|
|
avgGap
|
|
|
|
.name(name() + ".avgGap")
|
|
|
|
.desc("Average gap between requests")
|
|
|
|
.precision(2);
|
|
|
|
|
|
|
|
avgGap = totGap / (readReqs + writeReqs);
|
2013-11-01 16:56:28 +01:00
|
|
|
|
|
|
|
// Stats for DRAM Power calculation based on Micron datasheet
|
|
|
|
busUtilRead
|
|
|
|
.name(name() + ".busUtilRead")
|
|
|
|
.desc("Data bus utilization in percentage for reads")
|
|
|
|
.precision(2);
|
|
|
|
|
|
|
|
busUtilRead = avgRdBW / peakBW * 100;
|
|
|
|
|
|
|
|
busUtilWrite
|
|
|
|
.name(name() + ".busUtilWrite")
|
|
|
|
.desc("Data bus utilization in percentage for writes")
|
|
|
|
.precision(2);
|
|
|
|
|
|
|
|
busUtilWrite = avgWrBW / peakBW * 100;
|
|
|
|
|
|
|
|
pageHitRate
|
|
|
|
.name(name() + ".pageHitRate")
|
|
|
|
.desc("Row buffer hit rate, read and write combined")
|
|
|
|
.precision(2);
|
|
|
|
|
2013-11-01 16:56:31 +01:00
|
|
|
pageHitRate = (writeRowHits + readRowHits) /
|
|
|
|
(writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100;
|
2013-11-01 16:56:28 +01:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
pwrStateTime
|
|
|
|
.init(5)
|
|
|
|
.name(name() + ".memoryStateTime")
|
|
|
|
.desc("Time in different power states");
|
|
|
|
pwrStateTime.subname(0, "IDLE");
|
|
|
|
pwrStateTime.subname(1, "REF");
|
|
|
|
pwrStateTime.subname(2, "PRE_PDN");
|
|
|
|
pwrStateTime.subname(3, "ACT");
|
|
|
|
pwrStateTime.subname(4, "ACT_PDN");
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::recvFunctional(PacketPtr pkt)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
// rely on the abstract memory
|
|
|
|
functionalAccess(pkt);
|
|
|
|
}
|
|
|
|
|
2012-10-15 14:12:35 +02:00
|
|
|
BaseSlavePort&
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::getSlavePort(const string &if_name, PortID idx)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
if (if_name != "port") {
|
|
|
|
return MemObject::getSlavePort(if_name, idx);
|
|
|
|
} else {
|
|
|
|
return port;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned int
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::drain(DrainManager *dm)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
2012-11-02 17:32:01 +01:00
|
|
|
unsigned int count = port.drain(dm);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
// if there is anything in any of our internal queues, keep track
|
|
|
|
// of that as well
|
2013-03-01 19:20:24 +01:00
|
|
|
if (!(writeQueue.empty() && readQueue.empty() &&
|
|
|
|
respQueue.empty())) {
|
2012-11-08 10:25:06 +01:00
|
|
|
DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d,"
|
2013-03-01 19:20:24 +01:00
|
|
|
" resp: %d\n", writeQueue.size(), readQueue.size(),
|
|
|
|
respQueue.size());
|
2012-09-21 17:48:13 +02:00
|
|
|
++count;
|
2012-11-02 17:32:01 +01:00
|
|
|
drainManager = dm;
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2012-11-08 10:25:06 +01:00
|
|
|
// the only part that is not drained automatically over time
|
2014-05-10 00:58:48 +02:00
|
|
|
// is the write queue, thus kick things into action if needed
|
|
|
|
if (!writeQueue.empty() && !nextReqEvent.scheduled()) {
|
|
|
|
schedule(nextReqEvent, curTick());
|
|
|
|
}
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
if (count)
|
2012-11-02 17:32:01 +01:00
|
|
|
setDrainState(Drainable::Draining);
|
2012-09-21 17:48:13 +02:00
|
|
|
else
|
2012-11-02 17:32:01 +01:00
|
|
|
setDrainState(Drainable::Drained);
|
2012-09-21 17:48:13 +02:00
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory)
|
2012-09-21 17:48:13 +02:00
|
|
|
: QueuedSlavePort(name, &_memory, queue), queue(_memory, *this),
|
|
|
|
memory(_memory)
|
|
|
|
{ }
|
|
|
|
|
|
|
|
AddrRangeList
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::MemoryPort::getAddrRanges() const
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
AddrRangeList ranges;
|
|
|
|
ranges.push_back(memory.getAddrRange());
|
|
|
|
return ranges;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
pkt->pushLabel(memory.name());
|
|
|
|
|
|
|
|
if (!queue.checkFunctional(pkt)) {
|
|
|
|
// Default implementation of SimpleTimingPort::recvFunctional()
|
|
|
|
// calls recvAtomic() and throws away the latency; we can save a
|
|
|
|
// little here by just not calculating the latency.
|
|
|
|
memory.recvFunctional(pkt);
|
|
|
|
}
|
|
|
|
|
|
|
|
pkt->popLabel();
|
|
|
|
}
|
|
|
|
|
|
|
|
Tick
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
return memory.recvAtomic(pkt);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt)
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
|
|
|
// pass it to the memory controller
|
|
|
|
return memory.recvTimingReq(pkt);
|
|
|
|
}
|
|
|
|
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl*
|
|
|
|
DRAMCtrlParams::create()
|
2012-09-21 17:48:13 +02:00
|
|
|
{
|
2014-03-23 16:12:12 +01:00
|
|
|
return new DRAMCtrl(this);
|
2012-09-21 17:48:13 +02:00
|
|
|
}
|