mem: Merge DRAM page-management calculations
This patch treats the closed page policy as yet another case of auto-precharging, and thus merges the code with that used for the other policies.
This commit is contained in:
Andreas Hansson
parent
87f4c956c4
commit
c735ef6cb0
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@ -810,68 +810,48 @@ DRAMCtrl::estimateLatency(DRAMPacket* dram_pkt, Tick inTime)
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Tick potentialActTick;
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const Bank& bank = dram_pkt->bankRef;
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// open-page policy or close_adaptive policy
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if (pageMgmt == Enums::open || pageMgmt == Enums::open_adaptive ||
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pageMgmt == Enums::close_adaptive) {
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if (bank.openRow == dram_pkt->row) {
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// When we have a row-buffer hit,
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// we don't care about tRAS having expired or not,
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// but do care about bank being free for access
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rowHitFlag = true;
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// When a series of requests arrive to the same row,
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// DDR systems are capable of streaming data continuously
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// at maximum bandwidth (subject to tCCD). Here, we approximate
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// this condition, and assume that if whenever a bank is already
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// busy and a new request comes in, it can be completed with no
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// penalty beyond waiting for the existing read to complete.
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if (bank.freeAt > inTime) {
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accLat += bank.freeAt - inTime;
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bankLat += 0;
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} else {
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// CAS latency only
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accLat += tCL;
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bankLat += tCL;
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}
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if (bank.openRow == dram_pkt->row) {
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// When we have a row-buffer hit,
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// we don't care about tRAS having expired or not,
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// but do care about bank being free for access
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rowHitFlag = true;
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} else {
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// Row-buffer miss, need to close existing row
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// once tRAS has expired, then open the new one,
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// then add cas latency.
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Tick freeTime = std::max(bank.tRASDoneAt, bank.freeAt);
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if (freeTime > inTime)
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accLat += freeTime - inTime;
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// If the there is no open row (open adaptive), then there
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// is no precharge delay, otherwise go with tRP
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Tick precharge_delay = bank.openRow == Bank::NO_ROW ? 0 : tRP;
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//The bank is free, and you may be able to activate
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potentialActTick = inTime + accLat + precharge_delay;
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if (potentialActTick < bank.actAllowedAt)
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accLat += bank.actAllowedAt - potentialActTick;
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accLat += precharge_delay + tRCD + tCL;
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bankLat += precharge_delay + tRCD + tCL;
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}
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} else if (pageMgmt == Enums::close) {
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// With a close page policy, no notion of
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// bank.tRASDoneAt
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if (bank.freeAt > inTime)
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// When a series of requests arrive to the same row,
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// DDR systems are capable of streaming data continuously
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// at maximum bandwidth (subject to tCCD). Here, we approximate
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// this condition, and assume that if whenever a bank is already
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// busy and a new request comes in, it can be completed with no
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// penalty beyond waiting for the existing read to complete.
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if (bank.freeAt > inTime) {
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accLat += bank.freeAt - inTime;
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bankLat += 0;
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} else {
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// CAS latency only
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accLat += tCL;
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bankLat += tCL;
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}
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} else {
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// Row-buffer miss, need to close existing row
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// once tRAS has expired, then open the new one,
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// then add cas latency.
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Tick freeTime = std::max(bank.tRASDoneAt, bank.freeAt);
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if (freeTime > inTime)
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accLat += freeTime - inTime;
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// If the there is no open row, then there is no precharge
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// delay, otherwise go with tRP
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Tick precharge_delay = bank.openRow == Bank::NO_ROW ? 0 : tRP;
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//The bank is free, and you may be able to activate
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potentialActTick = inTime + accLat;
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potentialActTick = inTime + accLat + precharge_delay;
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if (potentialActTick < bank.actAllowedAt)
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accLat += bank.actAllowedAt - potentialActTick;
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// page already closed, simply open the row, and
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// add cas latency
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accLat += tRCD + tCL;
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bankLat += tRCD + tCL;
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} else
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panic("No page management policy chosen\n");
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accLat += precharge_delay + tRCD + tCL;
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bankLat += precharge_delay + tRCD + tCL;
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}
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DPRINTF(DRAM, "Returning < %lld, %lld > from estimateLatency()\n",
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bankLat, accLat);
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@ -1033,115 +1013,97 @@ DRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt)
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Bank& bank = dram_pkt->bankRef;
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// Update bank state
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if (pageMgmt == Enums::open || pageMgmt == Enums::open_adaptive ||
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pageMgmt == Enums::close_adaptive) {
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if (rowHitFlag) {
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bank.freeAt = curTick() + addDelay + accessLat;
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} else {
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// If there is a page open, precharge it.
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if (bank.openRow != Bank::NO_ROW) {
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prechargeBank(bank, std::max(std::max(bank.freeAt,
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bank.tRASDoneAt),
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curTick()) + tRP);
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}
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// Any precharge is already part of the latency
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// estimation, so update the bank free time
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bank.freeAt = curTick() + addDelay + accessLat;
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// any waiting for banks account for in freeAt
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actTick = bank.freeAt - tCL - tRCD;
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// If you activated a new row do to this access, the next access
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// will have to respect tRAS for this bank
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bank.tRASDoneAt = actTick + tRAS;
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recordActivate(actTick, dram_pkt->rank, dram_pkt->bank,
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dram_pkt->row);
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if (rowHitFlag) {
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bank.freeAt = curTick() + addDelay + accessLat;
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} else {
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// If there is a page open, precharge it.
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if (bank.openRow != Bank::NO_ROW) {
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prechargeBank(bank, std::max(std::max(bank.freeAt,
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bank.tRASDoneAt),
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curTick()) + tRP);
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}
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// increment the bytes accessed and the accesses per row
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bank.bytesAccessed += burstSize;
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++bank.rowAccesses;
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// Any precharge is already part of the latency
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// estimation, so update the bank free time
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bank.freeAt = curTick() + addDelay + accessLat;
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// if we reached the max, then issue with an auto-precharge
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bool auto_precharge = bank.rowAccesses == maxAccessesPerRow;
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// any waiting for banks account for in freeAt
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actTick = bank.freeAt - tCL - tRCD;
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// if we did not hit the limit, we might still want to
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// auto-precharge
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if (!auto_precharge &&
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(pageMgmt == Enums::open_adaptive ||
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pageMgmt == Enums::close_adaptive)) {
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// a twist on the open and close page policies:
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// 1) open_adaptive page policy does not blindly keep the
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// page open, but close it if there are no row hits, and there
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// are bank conflicts in the queue
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// 2) close_adaptive page policy does not blindly close the
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// page, but closes it only if there are no row hits in the queue.
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// In this case, only force an auto precharge when there
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// are no same page hits in the queue
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bool got_more_hits = false;
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bool got_bank_conflict = false;
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// either look at the read queue or write queue
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const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue :
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writeQueue;
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auto p = queue.begin();
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// make sure we are not considering the packet that we are
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// currently dealing with (which is the head of the queue)
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++p;
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// keep on looking until we have found required condition or
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// reached the end
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while (!(got_more_hits &&
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(got_bank_conflict || pageMgmt == Enums::close_adaptive)) &&
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p != queue.end()) {
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bool same_rank_bank = (dram_pkt->rank == (*p)->rank) &&
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(dram_pkt->bank == (*p)->bank);
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bool same_row = dram_pkt->row == (*p)->row;
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got_more_hits |= same_rank_bank && same_row;
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got_bank_conflict |= same_rank_bank && !same_row;
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++p;
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}
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// auto pre-charge when either
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// 1) open_adaptive policy, we have not got any more hits, and
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// have a bank conflict
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// 2) close_adaptive policy and we have not got any more hits
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auto_precharge = !got_more_hits &&
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(got_bank_conflict || pageMgmt == Enums::close_adaptive);
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}
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// if this access should use auto-precharge, then we are
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// closing the row
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if (auto_precharge) {
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prechargeBank(bank, std::max(bank.freeAt, bank.tRASDoneAt) + tRP);
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DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId);
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}
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DPRINTF(DRAM, "doDRAMAccess::bank.freeAt is %lld\n", bank.freeAt);
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} else if (pageMgmt == Enums::close) {
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actTick = curTick() + addDelay + accessLat - tRCD - tCL;
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recordActivate(actTick, dram_pkt->rank, dram_pkt->bank, dram_pkt->row);
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bank.freeAt = actTick + tRCD + tCL;
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// If you activated a new row do to this access, the next access
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// will have to respect tRAS for this bank
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bank.tRASDoneAt = actTick + tRAS;
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// sample the relevant values when precharging
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bank.bytesAccessed = burstSize;
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bank.rowAccesses = 1;
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recordActivate(actTick, dram_pkt->rank, dram_pkt->bank,
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dram_pkt->row);
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}
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// increment the bytes accessed and the accesses per row
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bank.bytesAccessed += burstSize;
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++bank.rowAccesses;
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// if we reached the max, then issue with an auto-precharge
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bool auto_precharge = pageMgmt == Enums::close ||
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bank.rowAccesses == maxAccessesPerRow;
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// if we did not hit the limit, we might still want to
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// auto-precharge
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if (!auto_precharge &&
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(pageMgmt == Enums::open_adaptive ||
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pageMgmt == Enums::close_adaptive)) {
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// a twist on the open and close page policies:
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// 1) open_adaptive page policy does not blindly keep the
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// page open, but close it if there are no row hits, and there
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// are bank conflicts in the queue
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// 2) close_adaptive page policy does not blindly close the
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// page, but closes it only if there are no row hits in the queue.
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// In this case, only force an auto precharge when there
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// are no same page hits in the queue
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bool got_more_hits = false;
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bool got_bank_conflict = false;
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// either look at the read queue or write queue
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const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue :
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writeQueue;
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auto p = queue.begin();
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// make sure we are not considering the packet that we are
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// currently dealing with (which is the head of the queue)
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++p;
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// keep on looking until we have found required condition or
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// reached the end
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while (!(got_more_hits &&
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(got_bank_conflict || pageMgmt == Enums::close_adaptive)) &&
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p != queue.end()) {
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bool same_rank_bank = (dram_pkt->rank == (*p)->rank) &&
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(dram_pkt->bank == (*p)->bank);
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bool same_row = dram_pkt->row == (*p)->row;
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got_more_hits |= same_rank_bank && same_row;
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got_bank_conflict |= same_rank_bank && !same_row;
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++p;
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}
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// auto pre-charge when either
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// 1) open_adaptive policy, we have not got any more hits, and
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// have a bank conflict
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// 2) close_adaptive policy and we have not got any more hits
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auto_precharge = !got_more_hits &&
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(got_bank_conflict || pageMgmt == Enums::close_adaptive);
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}
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// if this access should use auto-precharge, then we are
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// closing the row
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if (auto_precharge) {
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prechargeBank(bank, std::max(bank.freeAt, bank.tRASDoneAt) + tRP);
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DPRINTF(DRAM, "doDRAMAccess::bank.freeAt is %lld\n", bank.freeAt);
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} else
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panic("No page management policy chosen\n");
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DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId);
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}
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DPRINTF(DRAM, "doDRAMAccess::bank.freeAt is %lld\n", bank.freeAt);
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// Update request parameters
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dram_pkt->readyTime = curTick() + addDelay + accessLat + tBURST;
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DPRINTF(DRAM, "Req %lld: curtick is %lld accessLat is %d " \
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"readytime is %lld busbusyuntil is %lld. " \
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"Scheduling at readyTime\n", dram_pkt->addr,
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