mem: Add DDR4 bank group timing
Added the following parameter to the DRAMCtrl class: - bank_groups_per_rank This defaults to 1. For the DDR4 case, the default is overridden to indicate bank group architecture, with multiple bank groups per rank. Added the following delays to the DRAMCtrl class: - tCCD_L : CAS-to-CAS, same bank group delay - tRRD_L : RAS-to-RAS, same bank group delay These parameters are only applied when bank group timing is enabled. Bank group timing is currently enabled only for DDR4 memories. For all other memories, these delays will default to '0 ns' In the DRAM controller model, applied the bank group timing to the per bank parameters actAllowedAt and colAllowedAt. The actAllowedAt will be updated based on bank group when an ACT is issued. The colAllowedAt will be updated based on bank group when a RD/WR burst is issued. At the moment no modifications are made to the scheduling.
This commit is contained in:
Wendy Elsasser
parent
b6ecfe9183
commit
bf23847072
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@ -111,6 +111,11 @@ class DRAMCtrl(AbstractMemory):
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"device/chip")
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devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
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ranks_per_channel = Param.Unsigned("Number of ranks per channel")
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# default to 0 bank groups per rank, indicating bank group architecture
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# is not used
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# update per memory class when bank group architecture is supported
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bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank")
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banks_per_rank = Param.Unsigned("Number of banks per rank")
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# only used for the address mapping as the controller by
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# construction is a single channel and multiple controllers have
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@ -147,8 +152,17 @@ class DRAMCtrl(AbstractMemory):
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# This parameter has to account for burst length.
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# Read/Write requests with data size larger than one full burst are broken
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# down into multiple requests in the controller
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# tBURST is equivalent to the CAS-to-CAS delay (tCCD)
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# With bank group architectures, tBURST represents the CAS-to-CAS
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# delay for bursts to different bank groups (tCCD_S)
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tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
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# CAS-to-CAS delay for bursts to the same bank group
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# only utilized with bank group architectures; set to 0 for default case
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# tBURST is equivalent to tCCD_S; no explicit parameter required
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# for CAS-to-CAS delay for bursts to different bank groups
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tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay")
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# time taken to complete one refresh cycle (N rows in all banks)
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tRFC = Param.Latency("Refresh cycle time")
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@ -171,6 +185,9 @@ class DRAMCtrl(AbstractMemory):
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# minimum row activate to row activate delay time
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tRRD = Param.Latency("ACT to ACT delay")
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# only utilized with bank group architectures; set to 0 for default case
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tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay")
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# time window in which a maximum number of activates are allowed
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# to take place, set to 0 to disable
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tXAW = Param.Latency("X activation window")
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@ -274,6 +291,10 @@ class DDR4_2400_x64(DRAMCtrl):
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# Use a single rank
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ranks_per_channel = 1
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# DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
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# Set to 4 for x4, x8 case
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bank_groups_per_rank = 4
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# DDR4 has 16 banks (4 bank groups) in all
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# configurations. Currently we do not capture the additional
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# constraints incurred by the bank groups
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@ -283,16 +304,29 @@ class DDR4_2400_x64(DRAMCtrl):
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tCK = '0.833ns'
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# 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
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# tBURST is equivalent to the CAS-to-CAS delay (tCCD)
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# With bank group architectures, tBURST represents the CAS-to-CAS
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# delay for bursts to different bank groups (tCCD_S)
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tBURST = '3.333ns'
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# @2400 data rate, tCCD_L is 6 CK
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# CAS-to-CAS delay for bursts to the same bank group
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# tBURST is equivalent to tCCD_S; no explicit parameter required
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# for CAS-to-CAS delay for bursts to different bank groups
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tCCD_L = '5ns';
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# DDR4-2400 17-17-17
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tRCD = '14.16ns'
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tCL = '14.16ns'
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tRP = '14.16ns'
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tRAS = '32ns'
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# Here using the average of RRD_S and RRD_L
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tRRD = '4.1ns'
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# RRD_S (different bank group) for 1K page is MAX(4 CK, 3.3ns)
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tRRD = '3.3ns'
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# RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
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tRRD_L = '4.9ns';
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tXAW = '21ns'
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activation_limit = 4
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tRFC = '260ns'
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@ -69,6 +69,8 @@ DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) :
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columnsPerRowBuffer(rowBufferSize / burstSize),
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columnsPerStripe(range.granularity() / burstSize),
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ranksPerChannel(p->ranks_per_channel),
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bankGroupsPerRank(p->bank_groups_per_rank),
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bankGroupArch(p->bank_groups_per_rank > 0),
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banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0),
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readBufferSize(p->read_buffer_size),
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writeBufferSize(p->write_buffer_size),
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@ -77,9 +79,9 @@ DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) :
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minWritesPerSwitch(p->min_writes_per_switch),
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writesThisTime(0), readsThisTime(0),
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tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST),
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tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), tWR(p->tWR),
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tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD),
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tXAW(p->tXAW), activationLimit(p->activation_limit),
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tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS),
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tWR(p->tWR), tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD),
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tRRD_L(p->tRRD_L), tXAW(p->tXAW), activationLimit(p->activation_limit),
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memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping),
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pageMgmt(p->page_policy),
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maxAccessesPerRow(p->max_accesses_per_row),
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@ -104,6 +106,19 @@ DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) :
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for (int b = 0; b < banksPerRank; b++) {
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banks[r][b].rank = r;
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banks[r][b].bank = b;
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if (bankGroupArch) {
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// Simply assign lower bits to bank group in order to
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// rotate across bank groups as banks are incremented
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// e.g. with 4 banks per bank group and 16 banks total:
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// banks 0,4,8,12 are in bank group 0
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// banks 1,5,9,13 are in bank group 1
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// banks 2,6,10,14 are in bank group 2
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// banks 3,7,11,15 are in bank group 3
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banks[r][b].bankgr = b % bankGroupsPerRank;
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} else {
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// No bank groups; simply assign to bank number
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banks[r][b].bankgr = b;
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}
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}
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}
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@ -168,6 +183,35 @@ DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) :
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fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n",
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tREFI, tRP, tRFC);
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}
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// basic bank group architecture checks ->
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if (bankGroupArch) {
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// must have at least one bank per bank group
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if (bankGroupsPerRank > banksPerRank) {
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fatal("banks per rank (%d) must be equal to or larger than "
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"banks groups per rank (%d)\n",
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banksPerRank, bankGroupsPerRank);
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}
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// must have same number of banks in each bank group
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if ((banksPerRank % bankGroupsPerRank) != 0) {
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fatal("Banks per rank (%d) must be evenly divisible by bank groups "
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"per rank (%d) for equal banks per bank group\n",
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banksPerRank, bankGroupsPerRank);
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}
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// tCCD_L should be greater than minimal, back-to-back burst delay
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if (tCCD_L <= tBURST) {
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fatal("tCCD_L (%d) should be larger than tBURST (%d) when "
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"bank groups per rank (%d) is greater than 1\n",
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tCCD_L, tBURST, bankGroupsPerRank);
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}
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// tRRD_L is greater than minimal, same bank group ACT-to-ACT delay
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if (tRRD_L <= tRRD) {
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fatal("tRRD_L (%d) should be larger than tRRD (%d) when "
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"bank groups per rank (%d) is greater than 1\n",
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tRRD_L, tRRD, bankGroupsPerRank);
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}
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}
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}
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void
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@ -824,14 +868,25 @@ DRAMCtrl::activateBank(Bank& bank, Tick act_tick, uint32_t row)
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bank.preAllowedAt = act_tick + tRAS;
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// Respect the row-to-column command delay
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bank.colAllowedAt = act_tick + tRCD;
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bank.colAllowedAt = std::max(act_tick + tRCD, bank.colAllowedAt);
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// start by enforcing tRRD
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for(int i = 0; i < banksPerRank; i++) {
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// next activate to any bank in this rank must not happen
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// before tRRD
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banks[rank][i].actAllowedAt = std::max(act_tick + tRRD,
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banks[rank][i].actAllowedAt);
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if (bankGroupArch && (bank.bankgr == banks[rank][i].bankgr)) {
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// bank group architecture requires longer delays between
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// ACT commands within the same bank group. Use tRRD_L
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// in this case
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banks[rank][i].actAllowedAt = std::max(act_tick + tRRD_L,
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banks[rank][i].actAllowedAt);
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} else {
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// use shorter tRRD value when either
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// 1) bank group architecture is not supportted
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// 2) bank is in a different bank group
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banks[rank][i].actAllowedAt = std::max(act_tick + tRRD,
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banks[rank][i].actAllowedAt);
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}
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}
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// next, we deal with tXAW, if the activation limit is disabled
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@ -986,9 +1041,38 @@ DRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt)
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// only one burst can use the bus at any one point in time
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assert(dram_pkt->readyTime - busBusyUntil >= tBURST);
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// not strictly necessary, but update the time for the next
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// read/write (add a max with tCCD here)
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bank.colAllowedAt = cmd_at + tBURST;
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// update the time for the next read/write burst for each
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// bank (add a max with tCCD/tCCD_L here)
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Tick cmd_dly;
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for(int j = 0; j < ranksPerChannel; j++) {
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for(int i = 0; i < banksPerRank; i++) {
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// next burst to same bank group in this rank must not happen
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// before tCCD_L. Different bank group timing requirement is
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// tBURST; Add tCS for different ranks
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if (dram_pkt->rank == j) {
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if (bankGroupArch && (bank.bankgr == banks[j][i].bankgr)) {
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// bank group architecture requires longer delays between
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// RD/WR burst commands to the same bank group.
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// Use tCCD_L in this case
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cmd_dly = tCCD_L;
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} else {
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// use tBURST (equivalent to tCCD_S), the shorter
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// cas-to-cas delay value, when either:
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// 1) bank group architecture is not supportted
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// 2) bank is in a different bank group
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cmd_dly = tBURST;
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}
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} else {
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// different rank is by default in a different bank group
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// use tBURST (equivalent to tCCD_S), which is the shorter
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// cas-to-cas delay in this case
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// Add tCS to account for rank-to-rank bus delay requirements
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cmd_dly = tBURST + tCS;
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}
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banks[j][i].colAllowedAt = std::max(cmd_at + cmd_dly,
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banks[j][i].colAllowedAt);
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}
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}
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// Save rank of current access
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activeRank = dram_pkt->rank;
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@ -1184,15 +1268,8 @@ DRAMCtrl::processNextReqEvent()
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// that we are allowed to prepare a new bank, but not issue a
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// read command until after tWTR, in essence we capture a
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// bubble on the data bus that is tWTR + tCL
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if (switched_cmd_type) {
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// add a bubble to the data bus for write-to-read turn around
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// or tCS (different rank bus delay).
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busBusyUntil += (dram_pkt->rank == activeRank) ? tWTR + tCL :
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tCS;
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} else if (dram_pkt->rank != activeRank) {
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// add a bubble to the data bus, as defined by the
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// tCS parameter for rank-to-rank delay
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busBusyUntil += tCS;
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if (switched_cmd_type && dram_pkt->rank == activeRank) {
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busBusyUntil += tWTR + tCL;
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}
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doDRAMAccess(dram_pkt);
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@ -1235,14 +1312,12 @@ DRAMCtrl::processNextReqEvent()
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// sanity check
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assert(dram_pkt->size <= burstSize);
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if (switched_cmd_type) {
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// add a bubble to the data bus, as defined by the
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// tRTW or tCS parameter, depending on whether changing ranks
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busBusyUntil += (dram_pkt->rank == activeRank) ? tRTW : tCS;
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} else if (dram_pkt->rank != activeRank) {
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// add a bubble to the data bus, as defined by the
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// tCS parameter for rank-to-rank delay
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busBusyUntil += tCS;
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// add a bubble to the data bus, as defined by the
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// tRTW when access is to the same rank as previous burst
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// Different rank timing is handled with tCS, which is
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// applied to colAllowedAt
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if (switched_cmd_type && dram_pkt->rank == activeRank) {
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busBusyUntil += tRTW;
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}
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doDRAMAccess(dram_pkt);
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@ -158,6 +158,7 @@ class DRAMCtrl : public AbstractMemory
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uint32_t openRow;
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uint8_t rank;
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uint8_t bank;
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uint8_t bankgr;
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Tick colAllowedAt;
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Tick preAllowedAt;
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@ -167,7 +168,7 @@ class DRAMCtrl : public AbstractMemory
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uint32_t bytesAccessed;
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Bank() :
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openRow(NO_ROW), rank(0), bank(0),
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openRow(NO_ROW), rank(0), bank(0), bankgr(0),
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colAllowedAt(0), preAllowedAt(0), actAllowedAt(0),
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rowAccesses(0), bytesAccessed(0)
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{ }
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@ -470,6 +471,8 @@ class DRAMCtrl : public AbstractMemory
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const uint32_t columnsPerRowBuffer;
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const uint32_t columnsPerStripe;
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const uint32_t ranksPerChannel;
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const uint32_t bankGroupsPerRank;
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const bool bankGroupArch;
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const uint32_t banksPerRank;
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const uint32_t channels;
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uint32_t rowsPerBank;
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@ -490,6 +493,7 @@ class DRAMCtrl : public AbstractMemory
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const Tick tRTW;
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const Tick tCS;
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const Tick tBURST;
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const Tick tCCD_L;
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const Tick tRCD;
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const Tick tCL;
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const Tick tRP;
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@ -499,6 +503,7 @@ class DRAMCtrl : public AbstractMemory
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const Tick tRFC;
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const Tick tREFI;
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const Tick tRRD;
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const Tick tRRD_L;
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const Tick tXAW;
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const uint32_t activationLimit;
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