gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt

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---------- Begin Simulation Statistics ----------
regress: Regression tester updates Regression tester updates required by the following patches: brad/moved_python_protocol_files: config: moved python protocol config files brad/ruby_options_movement: config: reorganized how ruby specifies command-line options brad/config_token_bcast: ruby: added token broadcast config params to cmd options brad/topology_name: config: Added the topology description to m5 config.ini brad/ruby_system_names: config: Improve ruby simobject names brad/consolidated_protocol_stats: slicc: Consolidated the protocol stats printing brad/ruby_request_type_ostream_fix: ruby: Added ruby_request_type ostream def to libruby.hh brad/memtest_dma_extension: memtest: Memtester support for DMA brad/token_dma_lockdown_fix: MOESI_CMP_token: Fixed dma persistent lockdown bugs brad/profile_generic_mach_type: ruby: Reincarnated the responding machine profiling brad/network_msg_consolidated_stats: ruby: Added consolidated network msg stats brad/bcast_msg_profiling: ruby: Added bcast msg profiling to hammer and token brad/l2cache_profiling_fix: ruby: Fixed L2 cache miss profiling brad/llsc_ruby_m5_fix: ruby: fix ruby llsc support to sync sc outcomes brad/ruby_latency_fixes: ruby: Reduced ruby latencies brad/hammer_l2_cache_latency: ruby: Updated MOESI_hammer L2 latency behavior brad/deterministic_resurrection: ruby: Resurrected Ruby's deterministic tests brad/token_dma_fixes: ruby: MOESI_CMP_token dma fixes brad/ruby_cmd_options: config: added cmd options to control ruby debug brad/token_owner_fixes: ruby: fixed token bugs associated with owner token counts brad/ruby_remove_try_except: ruby: Improved try except blocks in ruby creation brad/ruby_port_callback_fix: ruby: Fixed RubyPort sendTiming callbacks brad/interrupt_drain_fix: devices: Fixed periodic interrupts to work with draining brad/llsc_trace_profile: ruby: Added SC fail indication to trace profiling brad/no_migrate_atomic: ruby: Disable migratory sharing for token and hammer brad/ruby_start_time_fix: ruby: Reset ruby stats in RubySystem unserialize brad/numa_bit_select_fix: ruby: fixed DirectoryMemory's numa_high_bit configuration brad/hammer_probe_filter: ruby: added probe filter support to hammer brad/miss_latency_detail_profile: MOESI_hammer: break down miss latency stalled cycles brad/recycle_latency_fix: ruby: Recycle latency fix for hammer brad/stall_and_wait: ruby: Stall and wait input messages instead of recycling brad/rubytest_request_flag_fix: ruby: Fixed minor bug in ruby test for setting the request type brad/hammer_merge_gets: ruby: Added merge GETS optimization to hammer brad/regress_updates: regress: Regression tester updates
2010-08-21 02:44:26 +02:00
sim_seconds 0.000208 # Number of seconds simulated
sim_ticks 208400 # Number of ticks simulated
final_tick 208400 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 49772 # Simulator instruction rate (inst/s)
host_op_rate 49764 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1619227 # Simulator tick rate (ticks/s)
host_mem_usage 231924 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory
system.physmem.bytes_read::total 34460 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory
system.physmem.bytes_written::total 6696 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 123109405 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 42245681 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 165355086 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 123109405 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 123109405 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 32130518 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 32130518 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 123109405 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 74376200 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 197485605 # Total bandwidth to/from this memory (bytes/s)
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.dir_cntrl0.probeFilter.num_data_array_reads 0 # number of data array reads
system.dir_cntrl0.probeFilter.num_data_array_writes 0 # number of data array writes
system.dir_cntrl0.probeFilter.num_tag_array_reads 0 # number of tag array reads
system.dir_cntrl0.probeFilter.num_tag_array_writes 0 # number of tag array writes
system.dir_cntrl0.probeFilter.num_tag_array_stalls 0 # number of stalls caused by tag array
system.dir_cntrl0.probeFilter.num_data_array_stalls 0 # number of stalls caused by data array
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6415 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 6432 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 208400 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6404 # Number of instructions committed
system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_int_insts 6331 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 208400 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------