2010-05-24 07:44:15 +02:00
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// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
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// All rights reserved.
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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2008-02-27 05:39:22 +01:00
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// Copyright (c) 2008 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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2007-06-13 20:05:08 +02:00
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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//////////////////////////////////////////////////////////////////////////
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//
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// LdStOp Microop templates
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//
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//////////////////////////////////////////////////////////////////////////
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2007-06-20 17:02:50 +02:00
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// LEA template
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def template MicroLeaExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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%(code)s;
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template MicroLeaDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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%(class_name)s(ExtMachInst _machInst,
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2010-08-23 18:44:19 +02:00
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const char * instMnem, uint64_t setFlags,
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2009-07-16 18:29:29 +02:00
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uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
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uint64_t _disp, InstRegIndex _segment,
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InstRegIndex _data,
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2009-02-25 19:18:22 +01:00
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uint8_t _dataSize, uint8_t _addressSize,
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Request::FlagsType _memFlags);
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2007-06-20 17:02:50 +02:00
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%(BasicExecDeclare)s
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};
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}};
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// Load templates
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2007-06-19 16:18:25 +02:00
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def template MicroLoadExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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2009-02-25 19:18:22 +01:00
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fault = read(xc, EA, Mem, memFlags);
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2007-07-21 00:02:09 +02:00
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2009-02-25 19:19:22 +01:00
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if (fault == NoFault) {
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2007-06-19 16:18:25 +02:00
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%(code)s;
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2009-11-09 07:49:57 +01:00
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} else if (memFlags & Request::PREFETCH) {
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2009-02-25 19:19:22 +01:00
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// For prefetches, ignore any faults/exceptions.
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return NoFault;
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2007-06-19 16:18:25 +02:00
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}
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template MicroLoadInitiateAcc {{
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Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
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Trace::InstRecord * traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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2009-02-25 19:18:22 +01:00
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fault = read(xc, EA, Mem, memFlags);
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2007-06-19 16:18:25 +02:00
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return fault;
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}
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}};
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def template MicroLoadCompleteAcc {{
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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%(CPU_exec_context)s * xc,
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Trace::InstRecord * traceData) const
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{
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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2008-11-10 06:55:43 +01:00
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Mem = get(pkt);
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2007-08-27 05:30:36 +02:00
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2007-06-19 16:18:25 +02:00
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%(code)s;
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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// Store templates
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def template MicroStoreExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s * xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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%(code)s;
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if(fault == NoFault)
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{
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2009-02-25 19:18:22 +01:00
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fault = write(xc, Mem, EA, memFlags);
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2007-07-27 07:08:35 +02:00
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if(fault == NoFault)
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2007-07-21 00:02:09 +02:00
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{
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2007-07-27 07:08:35 +02:00
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%(op_wb)s;
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2007-07-21 00:02:09 +02:00
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}
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2007-06-19 16:18:25 +02:00
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}
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return fault;
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}
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}};
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def template MicroStoreInitiateAcc {{
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Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
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Trace::InstRecord * traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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%(code)s;
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if(fault == NoFault)
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{
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2011-07-03 07:31:22 +02:00
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fault = write(xc, Mem, EA, memFlags);
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2007-06-19 16:18:25 +02:00
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}
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return fault;
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}
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}};
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def template MicroStoreCompleteAcc {{
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2009-02-25 19:15:56 +01:00
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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%(CPU_exec_context)s * xc, Trace::InstRecord * traceData) const
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2007-06-19 16:18:25 +02:00
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{
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2009-02-25 19:15:56 +01:00
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%(op_decl)s;
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%(op_rd)s;
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%(complete_code)s;
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%(op_wb)s;
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2007-06-19 16:18:25 +02:00
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return NoFault;
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}
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}};
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// Common templates
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//This delcares the initiateAcc function in memory operations
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def template InitiateAccDeclare {{
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Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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//This declares the completeAcc function in memory operations
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def template CompleteAccDeclare {{
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Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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def template MicroLdStOpDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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2007-06-13 20:05:08 +02:00
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public:
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%(class_name)s(ExtMachInst _machInst,
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2010-08-23 18:44:19 +02:00
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const char * instMnem, uint64_t setFlags,
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2009-07-16 18:29:29 +02:00
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uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
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uint64_t _disp, InstRegIndex _segment,
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InstRegIndex _data,
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2009-02-25 19:18:22 +01:00
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uint8_t _dataSize, uint8_t _addressSize,
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Request::FlagsType _memFlags);
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2007-06-13 20:05:08 +02:00
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%(BasicExecDeclare)s
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2007-06-19 16:18:25 +02:00
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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2007-06-13 20:05:08 +02:00
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};
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}};
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def template MicroLdStOpConstructor {{
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inline %(class_name)s::%(class_name)s(
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2010-08-23 18:44:19 +02:00
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ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
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2009-07-16 18:29:29 +02:00
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uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
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uint64_t _disp, InstRegIndex _segment,
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InstRegIndex _data,
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2009-02-25 19:18:22 +01:00
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uint8_t _dataSize, uint8_t _addressSize,
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Request::FlagsType _memFlags) :
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2010-08-23 18:44:19 +02:00
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%(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
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2007-06-19 16:18:25 +02:00
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_scale, _index, _base,
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_disp, _segment, _data,
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2009-02-25 19:18:22 +01:00
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_dataSize, _addressSize, _memFlags, %(op_class)s)
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2007-06-13 20:05:08 +02:00
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{
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2010-08-23 18:44:19 +02:00
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%(constructor)s;
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2007-06-13 20:05:08 +02:00
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}
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}};
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2007-06-19 16:18:25 +02:00
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let {{
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class LdStOp(X86Microop):
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2009-02-25 19:18:22 +01:00
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def __init__(self, data, segment, addr, disp,
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2011-03-02 07:42:59 +01:00
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dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec):
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2007-06-19 16:18:25 +02:00
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self.data = data
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[self.scale, self.index, self.base] = addr
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self.disp = disp
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self.segment = segment
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2007-07-20 00:15:47 +02:00
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self.dataSize = dataSize
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2007-10-13 01:37:55 +02:00
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self.addressSize = addressSize
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2009-02-25 19:18:22 +01:00
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self.memFlags = baseFlags
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if atCPL0:
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self.memFlags += " | (CPL0FlagBit << FlagShift)"
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2011-03-02 07:42:18 +01:00
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self.instFlags = ""
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2009-02-25 19:19:22 +01:00
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if prefetch:
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2009-11-09 07:49:57 +01:00
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self.memFlags += " | Request::PREFETCH"
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2011-03-02 07:42:59 +01:00
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self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
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if nonSpec:
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self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
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2009-02-27 18:23:50 +01:00
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self.memFlags += " | (machInst.legacy.addr ? " + \
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"(AddrSizeFlagBit << FlagShift) : 0)"
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2007-06-19 16:18:25 +02:00
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2010-08-23 18:44:19 +02:00
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def getAllocator(self, microFlags):
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allocator = '''new %(class_name)s(machInst, macrocodeBlock,
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2007-06-19 16:18:25 +02:00
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%(flags)s, %(scale)s, %(index)s, %(base)s,
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%(disp)s, %(segment)s, %(data)s,
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2009-02-25 19:18:22 +01:00
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%(dataSize)s, %(addressSize)s, %(memFlags)s)''' % {
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2007-06-19 16:18:25 +02:00
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"class_name" : self.className,
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2011-03-02 07:42:18 +01:00
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"flags" : self.microFlagsText(microFlags) + self.instFlags,
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2007-06-19 16:18:25 +02:00
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"scale" : self.scale, "index" : self.index,
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"base" : self.base,
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"disp" : self.disp,
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"segment" : self.segment, "data" : self.data,
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2009-02-25 19:18:22 +01:00
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"dataSize" : self.dataSize, "addressSize" : self.addressSize,
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"memFlags" : self.memFlags}
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2007-06-19 16:18:25 +02:00
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return allocator
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2011-02-14 02:44:24 +01:00
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class BigLdStOp(X86Microop):
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def __init__(self, data, segment, addr, disp,
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2011-03-02 07:42:59 +01:00
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dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec):
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2011-02-14 02:44:24 +01:00
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self.data = data
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[self.scale, self.index, self.base] = addr
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self.disp = disp
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self.segment = segment
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self.dataSize = dataSize
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self.addressSize = addressSize
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self.memFlags = baseFlags
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if atCPL0:
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self.memFlags += " | (CPL0FlagBit << FlagShift)"
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2011-03-02 07:42:59 +01:00
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self.instFlags = ""
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2011-02-14 02:44:24 +01:00
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if prefetch:
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self.memFlags += " | Request::PREFETCH"
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2011-03-02 07:42:59 +01:00
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self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
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if nonSpec:
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|
|
|
self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
|
2011-02-14 02:44:24 +01:00
|
|
|
self.memFlags += " | (machInst.legacy.addr ? " + \
|
|
|
|
"(AddrSizeFlagBit << FlagShift) : 0)"
|
|
|
|
|
|
|
|
def getAllocator(self, microFlags):
|
|
|
|
allocString = '''
|
|
|
|
(%(dataSize)s >= 4) ?
|
|
|
|
(StaticInstPtr)(new %(class_name)sBig(machInst,
|
|
|
|
macrocodeBlock, %(flags)s, %(scale)s, %(index)s,
|
|
|
|
%(base)s, %(disp)s, %(segment)s, %(data)s,
|
|
|
|
%(dataSize)s, %(addressSize)s, %(memFlags)s)) :
|
|
|
|
(StaticInstPtr)(new %(class_name)s(machInst,
|
|
|
|
macrocodeBlock, %(flags)s, %(scale)s, %(index)s,
|
|
|
|
%(base)s, %(disp)s, %(segment)s, %(data)s,
|
|
|
|
%(dataSize)s, %(addressSize)s, %(memFlags)s))
|
|
|
|
'''
|
|
|
|
allocator = allocString % {
|
|
|
|
"class_name" : self.className,
|
2011-03-02 07:42:59 +01:00
|
|
|
"flags" : self.microFlagsText(microFlags) + self.instFlags,
|
2011-02-14 02:44:24 +01:00
|
|
|
"scale" : self.scale, "index" : self.index,
|
|
|
|
"base" : self.base,
|
|
|
|
"disp" : self.disp,
|
|
|
|
"segment" : self.segment, "data" : self.data,
|
|
|
|
"dataSize" : self.dataSize, "addressSize" : self.addressSize,
|
|
|
|
"memFlags" : self.memFlags}
|
|
|
|
return allocator
|
2007-06-19 16:18:25 +02:00
|
|
|
}};
|
|
|
|
|
|
|
|
let {{
|
|
|
|
|
|
|
|
# Make these empty strings so that concatenating onto
|
|
|
|
# them will always work.
|
|
|
|
header_output = ""
|
|
|
|
decoder_output = ""
|
|
|
|
exec_output = ""
|
|
|
|
|
2009-02-27 18:25:16 +01:00
|
|
|
calculateEA = '''
|
|
|
|
EA = bits(SegBase + scale * Index + Base + disp, addressSize * 8 - 1, 0);
|
|
|
|
'''
|
2007-06-19 16:18:25 +02:00
|
|
|
|
2011-02-14 02:44:24 +01:00
|
|
|
def defineMicroLoadOp(mnemonic, code, bigCode='',
|
|
|
|
mem_flags="0", big=True):
|
2007-06-19 16:18:25 +02:00
|
|
|
global header_output
|
|
|
|
global decoder_output
|
|
|
|
global exec_output
|
|
|
|
global microopClasses
|
|
|
|
Name = mnemonic
|
|
|
|
name = mnemonic.lower()
|
|
|
|
|
|
|
|
# Build up the all register version of this micro op
|
2011-02-14 02:44:24 +01:00
|
|
|
iops = [InstObjParams(name, Name, 'X86ISA::LdStOp',
|
|
|
|
{"code": code, "ea_code": calculateEA})]
|
|
|
|
if big:
|
|
|
|
iops += [InstObjParams(name, Name + "Big", 'X86ISA::LdStOp',
|
|
|
|
{"code": bigCode, "ea_code": calculateEA})]
|
|
|
|
for iop in iops:
|
|
|
|
header_output += MicroLdStOpDeclare.subst(iop)
|
|
|
|
decoder_output += MicroLdStOpConstructor.subst(iop)
|
|
|
|
exec_output += MicroLoadExecute.subst(iop)
|
|
|
|
exec_output += MicroLoadInitiateAcc.subst(iop)
|
|
|
|
exec_output += MicroLoadCompleteAcc.subst(iop)
|
|
|
|
|
|
|
|
base = LdStOp
|
|
|
|
if big:
|
|
|
|
base = BigLdStOp
|
|
|
|
class LoadOp(base):
|
2007-10-13 01:37:55 +02:00
|
|
|
def __init__(self, data, segment, addr, disp = 0,
|
2009-02-25 19:18:22 +01:00
|
|
|
dataSize="env.dataSize",
|
|
|
|
addressSize="env.addressSize",
|
2011-03-02 07:42:59 +01:00
|
|
|
atCPL0=False, prefetch=False, nonSpec=False):
|
2009-02-25 19:18:22 +01:00
|
|
|
super(LoadOp, self).__init__(data, segment, addr,
|
2009-02-25 19:19:22 +01:00
|
|
|
disp, dataSize, addressSize, mem_flags,
|
2011-03-02 07:42:59 +01:00
|
|
|
atCPL0, prefetch, nonSpec)
|
2007-06-19 16:18:25 +02:00
|
|
|
self.className = Name
|
|
|
|
self.mnemonic = name
|
|
|
|
|
|
|
|
microopClasses[name] = LoadOp
|
|
|
|
|
2011-02-14 02:44:24 +01:00
|
|
|
defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);',
|
|
|
|
'Data = Mem & mask(dataSize * 8);')
|
2009-02-25 19:18:22 +01:00
|
|
|
defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);',
|
2011-02-14 02:44:24 +01:00
|
|
|
'Data = Mem & mask(dataSize * 8);',
|
|
|
|
'(StoreCheck << FlagShift)')
|
2009-04-19 13:55:43 +02:00
|
|
|
defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);',
|
2011-02-14 02:44:24 +01:00
|
|
|
'Data = Mem & mask(dataSize * 8);',
|
|
|
|
'(StoreCheck << FlagShift) | Request::LOCKED')
|
|
|
|
defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;', big = False)
|
2007-06-19 16:18:25 +02:00
|
|
|
|
2011-06-22 04:28:14 +02:00
|
|
|
def defineMicroStoreOp(mnemonic, code, completeCode="", mem_flags="0"):
|
2007-06-19 16:18:25 +02:00
|
|
|
global header_output
|
|
|
|
global decoder_output
|
|
|
|
global exec_output
|
|
|
|
global microopClasses
|
|
|
|
Name = mnemonic
|
|
|
|
name = mnemonic.lower()
|
|
|
|
|
|
|
|
# Build up the all register version of this micro op
|
2007-07-15 02:14:19 +02:00
|
|
|
iop = InstObjParams(name, Name, 'X86ISA::LdStOp',
|
2007-10-03 07:08:09 +02:00
|
|
|
{"code": code,
|
2009-02-25 19:15:56 +01:00
|
|
|
"complete_code": completeCode,
|
2009-02-25 19:18:22 +01:00
|
|
|
"ea_code": calculateEA})
|
2007-06-19 16:18:25 +02:00
|
|
|
header_output += MicroLdStOpDeclare.subst(iop)
|
|
|
|
decoder_output += MicroLdStOpConstructor.subst(iop)
|
|
|
|
exec_output += MicroStoreExecute.subst(iop)
|
|
|
|
exec_output += MicroStoreInitiateAcc.subst(iop)
|
|
|
|
exec_output += MicroStoreCompleteAcc.subst(iop)
|
|
|
|
|
|
|
|
class StoreOp(LdStOp):
|
2007-10-13 01:37:55 +02:00
|
|
|
def __init__(self, data, segment, addr, disp = 0,
|
2009-02-25 19:18:22 +01:00
|
|
|
dataSize="env.dataSize",
|
|
|
|
addressSize="env.addressSize",
|
2011-03-02 07:42:59 +01:00
|
|
|
atCPL0=False, nonSpec=False):
|
|
|
|
super(StoreOp, self).__init__(data, segment, addr, disp,
|
|
|
|
dataSize, addressSize, mem_flags, atCPL0, False,
|
|
|
|
nonSpec)
|
2007-06-19 16:18:25 +02:00
|
|
|
self.className = Name
|
|
|
|
self.mnemonic = name
|
|
|
|
|
|
|
|
microopClasses[name] = StoreOp
|
|
|
|
|
2009-02-25 19:19:14 +01:00
|
|
|
defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);')
|
2009-04-19 13:55:58 +02:00
|
|
|
defineMicroStoreOp('Stul', 'Mem = pick(Data, 2, dataSize);',
|
|
|
|
mem_flags="Request::LOCKED")
|
2007-08-30 05:36:12 +02:00
|
|
|
defineMicroStoreOp('Stfp', 'Mem = FpData.uqw;')
|
2009-02-25 19:15:56 +01:00
|
|
|
defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags="Request::NO_ACCESS")
|
2007-06-20 17:02:50 +02:00
|
|
|
|
2007-07-15 02:14:19 +02:00
|
|
|
iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp',
|
2007-10-03 07:08:09 +02:00
|
|
|
{"code": "Data = merge(Data, EA, dataSize);",
|
2009-04-19 12:24:51 +02:00
|
|
|
"ea_code": '''
|
|
|
|
EA = bits(scale * Index + Base + disp, addressSize * 8 - 1, 0);
|
|
|
|
'''})
|
2007-06-20 17:02:50 +02:00
|
|
|
header_output += MicroLeaDeclare.subst(iop)
|
|
|
|
decoder_output += MicroLdStOpConstructor.subst(iop)
|
|
|
|
exec_output += MicroLeaExecute.subst(iop)
|
|
|
|
|
|
|
|
class LeaOp(LdStOp):
|
2007-10-13 01:37:55 +02:00
|
|
|
def __init__(self, data, segment, addr, disp = 0,
|
|
|
|
dataSize="env.dataSize", addressSize="env.addressSize"):
|
2011-03-02 07:42:59 +01:00
|
|
|
super(LeaOp, self).__init__(data, segment, addr, disp,
|
|
|
|
dataSize, addressSize, "0", False, False, False)
|
2007-06-20 17:02:50 +02:00
|
|
|
self.className = "Lea"
|
|
|
|
self.mnemonic = "lea"
|
|
|
|
|
|
|
|
microopClasses["lea"] = LeaOp
|
2007-10-22 23:30:56 +02:00
|
|
|
|
|
|
|
|
2008-02-27 05:39:22 +01:00
|
|
|
iop = InstObjParams("tia", "Tia", 'X86ISA::LdStOp',
|
|
|
|
{"code": "xc->demapPage(EA, 0);",
|
2009-02-25 19:18:22 +01:00
|
|
|
"ea_code": calculateEA})
|
2008-02-27 05:39:22 +01:00
|
|
|
header_output += MicroLeaDeclare.subst(iop)
|
|
|
|
decoder_output += MicroLdStOpConstructor.subst(iop)
|
|
|
|
exec_output += MicroLeaExecute.subst(iop)
|
|
|
|
|
|
|
|
class TiaOp(LdStOp):
|
|
|
|
def __init__(self, segment, addr, disp = 0,
|
2009-02-25 19:18:22 +01:00
|
|
|
dataSize="env.dataSize",
|
|
|
|
addressSize="env.addressSize"):
|
2009-07-16 18:29:29 +02:00
|
|
|
super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
|
2011-03-02 07:42:59 +01:00
|
|
|
addr, disp, dataSize, addressSize, "0", False, False,
|
|
|
|
False)
|
2008-02-27 05:39:22 +01:00
|
|
|
self.className = "Tia"
|
|
|
|
self.mnemonic = "tia"
|
|
|
|
|
|
|
|
microopClasses["tia"] = TiaOp
|
|
|
|
|
2007-10-22 23:30:56 +02:00
|
|
|
class CdaOp(LdStOp):
|
|
|
|
def __init__(self, segment, addr, disp = 0,
|
2009-02-25 19:18:22 +01:00
|
|
|
dataSize="env.dataSize",
|
|
|
|
addressSize="env.addressSize", atCPL0=False):
|
2009-07-16 18:29:29 +02:00
|
|
|
super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
|
2009-08-23 23:16:58 +02:00
|
|
|
addr, disp, dataSize, addressSize, "Request::NO_ACCESS",
|
2011-03-02 07:42:59 +01:00
|
|
|
atCPL0, False, False)
|
2007-10-22 23:30:56 +02:00
|
|
|
self.className = "Cda"
|
|
|
|
self.mnemonic = "cda"
|
|
|
|
|
|
|
|
microopClasses["cda"] = CdaOp
|
2007-06-19 16:18:25 +02:00
|
|
|
}};
|
|
|
|
|