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x86 fixes

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Make the emulation environment consider the rex prefix.
Implement and hook in forms of j, jmp, cmp, syscall, movzx
Added a format for an instruction to carry a call to the SE mode syscalls system
Made memory instructions which refer to the rip do so directly
Made the operand size overridable in the microassembly
Made the "ext" field of register operations 16 bits to hold a sparse encoding of flags to set or conditions to predicate on
Added an explicit "rax" operand for the syscall format
Implemented syscall returns.

--HG--
extra : convert_revision : ae84bd8c6a1d400906e17e8b8c4185f2ebd4c5f2
This commit is contained in:
Gabe Black 2007-07-19 15:15:47 -07:00
parent 09f056a1ef
commit cfadef74d1
13 changed files with 391 additions and 155 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
src/arch/x86/emulenv.cc
View file

@ -66,8 +66,8 @@ void EmulEnv::doModRM(const ExtMachInst & machInst)
//Use the SIB byte for addressing if the modrm byte calls for it.
if (machInst.modRM.rm == 4 && machInst.addrSize != 2) {
scale = 1 << machInst.sib.scale;
index = machInst.sib.index;
base = machInst.sib.base;
index = machInst.sib.index | (machInst.rex.x << 3);
base = machInst.sib.base | (machInst.rex.b << 3);
//In this special case, we don't use a base. The displacement also
//changes, but that's managed by the predecoder.
if (machInst.sib.base == INTREG_RBP && machInst.modRM.mod == 0)
@ -80,11 +80,13 @@ void EmulEnv::doModRM(const ExtMachInst & machInst)
warn("I'm not really using 16 bit MODRM like I'm supposed to!\n");
} else {
scale = 0;
base = machInst.modRM.rm;
base = machInst.modRM.rm | (machInst.rex.b << 3);
if (machInst.modRM.mod == 0 && machInst.modRM.rm == 5) {
base = NUM_INTREGS;
if (machInst.mode.submode == SixtyFourBitMode)
base = NUM_INTREGS+7;
//Since we need to use a different encoding of this
//instruction anyway, just ignore the base in those cases
// if (machInst.mode.submode == SixtyFourBitMode)
// base = NUM_INTREGS+7;
}
}
}

10
src/arch/x86/isa/decoder/one_byte_opcodes.isa
View file

@ -163,8 +163,8 @@
0x1: cmp_Ev_Gv();
0x2: cmp_Gb_Eb();
0x3: cmp_Gv_Ev();
0x4: cmp_Al_Ib();
0x5: cmp_rAX_Iz();
0x4: Inst::CMP(rAl,Ib);
0x5: Inst::CMP(rAX,Iz);
0x6: M5InternalError::error(
{{"Tried to execute the DS segment override prefix!"}});
0x7: decode MODE_SUBMODE {
@ -262,10 +262,10 @@
0x0: jo_Jb();
0x1: jno_Jb();
0x2: jb_Jb();
0x3: jnb_Jb();
0x3: Inst::JNB(Jb);
0x4: Inst::JZ(Jb);
0x5: Inst::JNZ(Jb);
0x6: jbe_Jb();
0x6: Inst::JBE(Jb);
0x7: jnbe_Jb();
}
0x0F: decode OPCODE_OP_BOTTOM3 {
@ -475,7 +475,7 @@
0x0: This_should_be_an_illegal_instruction();
default: jmp_Ap();
}
0x3: jmp_Jb();
0x3: Inst::JMP(Jb);
0x4: in_Al_Dx();
0x5: in_eAX_Dx();
0x6: out_Dx_Al();

234
src/arch/x86/isa/decoder/two_byte_opcodes.isa
View file

@ -67,21 +67,25 @@
0x03: lsl_Gv_Ew();
//sandpile.org doesn't seem to know what this is... ?
0x04: loadall_or_reset_or_hang();
#if FULL_SYSTEM
0x05: syscall();
#else
0x05: SyscallInst::syscall('xc->syscall(rax)');
#endif
0x06: clts();
//sandpile.org says (AMD) after sysret, so I might want to check
//if that means amd64 or AMD machines
0x07: loadall_or_sysret();
}
0x01: decode OPCODE_OP_BOTTOM3 {
0x0: holderholder();
0x1: holder();
0x2: holder();
0x3: holder();
0x4: holder();
0x5: holder();
0x6: holder();
0x7: holder();
0x0: invd();
0x1: wbinvd();
0x2: This_should_be_an_illegal_instruction();
0x3: UD1();
0x4: This_should_be_an_illegal_instruction();
0x5: threednow();
0x6: threednow();
0x7: threednow();
}
0x02: decode OPCODE_OP_BOTTOM3 {
0x0: holder();
@ -94,14 +98,14 @@
0x7: holder();
}
0x03: decode OPCODE_OP_BOTTOM3 {
0x0: holder();
0x1: holder();
0x2: holder();
0x3: holder();
0x4: holder();
0x5: holder();
0x6: holder();
0x7: holder();
0x0: group17();
0x1: group17();
0x2: group17();
0x3: group17();
0x4: group17();
0x5: group17();
0x6: group17();
0x7: group17();
}
0x04: decode OPCODE_OP_BOTTOM3 {
0x0: holder();
@ -124,44 +128,44 @@
0x7: holder();
}
0x06: decode OPCODE_OP_BOTTOM3 {
0x0: holder();
0x1: holder();
0x2: holder();
0x3: holder();
0x4: holder();
0x5: holder();
0x6: holder();
0x7: holder();
0x0: wrmsr();
0x1: rdtsc();
0x2: rdmsr();
0x3: rdpmc();
0x4: sysenter();
0x5: sysexit();
0x6: This_should_be_an_illegal_instruction();
0x7: getsec();
}
0x07: decode OPCODE_OP_BOTTOM3 {
0x0: holder();
0x1: holder();
0x2: holder();
0x3: holder();
0x4: holder();
0x5: holder();
0x6: holder();
0x7: holder();
0x0: three_byte_opcode();
0x1: three_byte_opcode();
0x2: three_byte_opcode();
0x3: three_byte_opcode();
0x4: three_byte_opcode();
0x5: three_byte_opcode();
0x6: three_byte_opcode();
0x7: three_byte_opcode();
}
0x08: decode OPCODE_OP_BOTTOM3 {
0x0: holder();
0x1: holder();
0x2: holder();
0x3: holder();
0x4: holder();
0x5: holder();
0x6: holder();
0x7: holder();
0x0: cmovo_Gv_Ev();
0x1: cmovno_Gv_Ev();
0x2: cmovb_Gv_Ev();
0x3: cmovnb_Gv_Ev();
0x4: cmovz_Gv_Ev();
0x5: cmovnz_Gv_Ev();
0x6: cmovbe_Gv_Ev();
0x7: cmovnbe_Gv_Ev();
}
0x09: decode OPCODE_OP_BOTTOM3 {
0x0: holder();
0x1: holder();
0x2: holder();
0x3: holder();
0x4: holder();
0x5: holder();
0x6: holder();
0x7: holder();
0x0: cmovs_Gv_Ev();
0x1: cmovns_Gv_Ev();
0x2: cmovp_Gv_Ev();
0x3: cmovnp_Gv_Ev();
0x4: cmovl_Gv_Ev();
0x5: cmovnl_Gv_Ev();
0x6: cmovle_Gv_Ev();
0x7: cmovnle_Gv_Ev();
}
0x0A: decode OPCODE_OP_BOTTOM3 {
0x0: holder();
@ -227,81 +231,81 @@
0x0: jo_Jz();
0x1: jno_Jz();
0x2: jb_Jz();
0x3: jnb_Jz();
0x4: jz_Jz();
0x3: Inst::JNB(Jz);
0x4: Inst::JZ(Jz);
0x5: Inst::JNZ(Jz);
0x6: jbe_Jz();
0x6: Inst::JBE(Jz);
0x7: jnbe_Jz();
}
0x11: decode OPCODE_OP_BOTTOM3 {
0x0: holder();
0x1: holder();
0x2: holder();
0x3: holder();
0x4: holder();
0x5: holder();
0x6: holder();
0x7: holder();
0x0: js_Jz();
0x1: jns_Jz();
0x2: jp_Jz();
0x3: jnp_Jz();
0x4: jl_Jz();
0x5: jnl_Jz();
0x6: jle_Jz();
0x7: jnle_Jz();
}
0x12: decode OPCODE_OP_BOTTOM3 {
0x0: holder();
0x1: holder();
0x2: holder();
0x3: holder();
0x4: holder();
0x5: holder();
0x6: holder();
0x7: holder();
0x0: seto_Eb();
0x1: setno_Eb();
0x2: setb_Eb();
0x3: setnb_Eb();
0x4: setz_Eb();
0x5: setnz_Eb();
0x6: setbe_Eb();
0x7: setnbe_Eb();
}
0x13: decode OPCODE_OP_BOTTOM3 {
0x0: holder();
0x1: holder();
0x2: holder();
0x3: holder();
0x4: holder();
0x5: holder();
0x6: holder();
0x7: holder();
0x0: sets_Eb();
0x1: setns_Eb();
0x2: setp_Eb();
0x3: setnp_Eb();
0x4: setl_Eb();
0x5: setnl_Eb();
0x6: setle_Eb();
0x7: setnle_Eb();
}
0x14: decode OPCODE_OP_BOTTOM3 {
0x0: holder();
0x1: holder();
0x2: holder();
0x3: holder();
0x4: holder();
0x5: holder();
0x6: holder();
0x7: holder();
0x0: push_fs();
0x1: pop_fs();
0x2: cpuid();
0x3: bt_Ev_Gv();
0x4: shld_Ev_Gv_Ib();
0x5: shld_Ev_Gv_rCl();
0x6: xbts_and_cmpxchg();
0x7: ibts_and_cmpxchg();
}
0x15: decode OPCODE_OP_BOTTOM3 {
0x0: holder();
0x1: holder();
0x2: holder();
0x3: holder();
0x4: holder();
0x5: holder();
0x6: holder();
0x7: holder();
0x0: push_gs();
0x1: pop_gs();
0x2: rsm_smm();
0x3: bts_Ev_Gv();
0x4: shrd_Ev_Gv_Ib();
0x5: shrd_Ev_Gv_rCl();
0x6: group16();
0x7: imul_Gv_Ev();
}
0x16: decode OPCODE_OP_BOTTOM3 {
0x0: holder();
0x1: holder();
0x2: holder();
0x3: holder();
0x4: holder();
0x5: holder();
0x6: holder();
0x7: holder();
0x0: cmpxchg_Eb_Gb();
0x1: cmpxchg_Ev_Gv();
0x2: lss_Gz_Mp();
0x3: btr_Ev_Gv();
0x4: lfs_Gz_Mp();
0x5: lgs_Gz_Mp();
0x6: Inst::MOVZX_B(Gv,Eb);
0x7: Inst::MOVZX_W(Gv,Ew);
}
0x17: decode OPCODE_OP_BOTTOM3 {
0x0: holder();
0x1: holder();
0x2: holder();
0x3: holder();
0x4: holder();
0x5: holder();
0x6: holder();
0x7: holder();
0x0: jmpe_Jz(); // IA-64?
0x1: group11_UD2();
0x2: group8_Ev_Ib();
0x3: btc_Ev_Gv();
0x4: bsf_Gv_Ev();
0x5: bsr_Gv_Ev();
0x6: movsx_Gv_Eb();
0x7: movsx_Gv_Ew();
}
0x18: decode OPCODE_OP_BOTTOM3 {
0x0: holder();
@ -314,14 +318,14 @@
0x7: holder();
}
0x19: decode OPCODE_OP_BOTTOM3 {
0x0: holder();
0x1: holder();
0x2: holder();
0x3: holder();
0x4: holder();
0x5: holder();
0x6: holder();
0x7: holder();
0x0: bswap_rAx();
0x1: bswap_rCx();
0x2: bswap_rDx();
0x3: bswap_rBx();
0x4: bswap_rSP();
0x5: bswap_rBP();
0x6: bswap_rSI();
0x7: bswap_rDI();
}
0x1A: decode OPCODE_OP_BOTTOM3 {
0x0: holder();

4
src/arch/x86/isa/formats/formats.isa
View file

@ -98,3 +98,7 @@
//Include a format which implements a batch of instructions which do the same
//thing on a variety of inputs
##include "multi.isa"
//Include a format which makes instructions who's sole purpose is to generate
//a syscall.
##include "syscall.isa"

112
src/arch/x86/isa/formats/syscall.isa Normal file
View file

@ -0,0 +1,112 @@
// -*- mode:c++ -*-
// Copyright (c) 2007 The Hewlett-Packard Development Company
// All rights reserved.
//
// Redistribution and use of this software in source and binary forms,
// with or without modification, are permitted provided that the
// following conditions are met:
//
// The software must be used only for Non-Commercial Use which means any
// use which is NOT directed to receiving any direct monetary
// compensation for, or commercial advantage from such use. Illustrative
// examples of non-commercial use are academic research, personal study,
// teaching, education and corporate research & development.
// Illustrative examples of commercial use are distributing products for
// commercial advantage and providing services using the software for
// commercial advantage.
//
// If you wish to use this software or functionality therein that may be
// covered by patents for commercial use, please contact:
// Director of Intellectual Property Licensing
// Office of Strategy and Technology
// Hewlett-Packard Company
// 1501 Page Mill Road
// Palo Alto, California 94304
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer. Redistributions
// in binary form must reproduce the above copyright notice, this list of
// conditions and the following disclaimer in the documentation and/or
// other materials provided with the distribution. Neither the name of
// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission. No right of
// sublicense is granted herewith. Derivatives of the software and
// output created using the software may be prepared, but only for
// Non-Commercial Uses. Derivatives of the software may be shared with
// others provided: (i) the others agree to abide by the list of
// conditions herein which includes the Non-Commercial Use restrictions;
// and (ii) such Derivatives of the software include the above copyright
// notice to acknowledge the contribution from this software where
// applicable, this list of conditions and the disclaimer below.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
////////////////////////////////////////////////////////////////////
//
// "Format" which describes an instruction whose only purpose is to
// call a syscall in SE mode.
//
output header {{
class SyscallInst : public X86ISA::X86StaticInst
{
public:
/// Constructor
SyscallInst(const char *_mnemonic, ExtMachInst _machInst,
OpClass __opClass) :
X86ISA::X86StaticInst(_mnemonic, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string SyscallInst::generateDisassembly(Addr PC,
const SymbolTable *symtab) const
{
std::stringstream response;
printMnemonic(response, mnemonic);
ccprintf(response, " ");
printReg(response, _srcRegIdx[0], machInst.opSize);
return response.str();
}
}};
def template SyscallExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
%(code)s;
return fault;
}
}};
def format SyscallInst(code, *opt_flags) {{
iop = InstObjParams(name, Name, 'SyscallInst', code, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = SyscallExecute.subst(iop)
}};

12
src/arch/x86/isa/insts/compare_and_test/compare.py
View file

@ -53,8 +53,10 @@
#
# Authors: Gabe Black
microcode = ""
#let {{
# class CMP(Inst):
# "GenFault ${new UnimpInstFault}"
#}};
microcode = '''
def macroop CMP_R_I
{
limm t1, imm
sub t0, reg, t1, flags=(OF, SF, ZF, AF, PF, CF)
};
'''

4
src/arch/x86/isa/insts/compare_and_test/test.py
View file

@ -63,7 +63,7 @@ def macroop TEST_M_R
def macroop TEST_P_R
{
rdip t7
ld t1, ds, [scale, index, base], disp
ld t1, ds, [0, t0, t7], disp
and t0, t1, reg, flags=(SF, ZF, PF)
};
@ -82,7 +82,7 @@ def macroop TEST_M_I
def macroop TEST_P_I
{
rdip t7
ld t1, ds, [scale, index, base], disp
ld t1, ds, [0, t0, t7], disp
limm t2, imm
and t0, t1, t2, flags=(SF, ZF, PF)
};

48
src/arch/x86/isa/insts/control_transfer/jump.py
View file

@ -56,6 +56,9 @@
microcode = '''
def macroop JZ_I
{
# Make the defualt data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(CZF,)
@ -63,8 +66,53 @@ def macroop JZ_I
def macroop JNZ_I
{
# Make the defualt data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCZF,)
};
def macroop JNB_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCCF,)
};
def macroop JBE_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(CCvZF,)
};
def macroop JMP_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2
};
def macroop JMP_R
{
wripi reg, 0
};
def macroop JMP_M
{
ld t1, ds, [scale, index, base], disp
wripi t1, 0
};
'''

66
src/arch/x86/isa/insts/data_transfer/move.py
View file

@ -64,7 +64,7 @@ def macroop MOV_M_R {
def macroop MOV_P_R {
rdip t7
st reg, ds, [scale, index, base], disp
st reg, ds, [0, t0, t7], disp
};
def macroop MOV_R_M {
@ -73,7 +73,7 @@ def macroop MOV_R_M {
def macroop MOV_R_P {
rdip t7
ld reg, ds, [scale, index, base], disp
ld reg, ds, [0, t0, t7], disp
};
def macroop MOV_R_I {
@ -88,7 +88,7 @@ def macroop MOV_M_I {
def macroop MOV_P_I {
rdip t7
limm t1, imm
st t1, ds, [scale, index, base], disp
st t1, ds, [0, t0, t7], disp
};
def macroop MOVSXD_R_R {
@ -102,9 +102,67 @@ def macroop MOVSXD_R_M {
def macroop MOVSXD_R_P {
rdip t7
ld t1, ds, [scale, index, base], disp
ld t1, ds, [0, t0, t7], disp
sext reg, t1, dsz
};
def macroop MOVZX_B_R_R {
mov reg, reg, t0
mov reg, reg, regm, dataSize=1
};
def macroop MOVZX_B_R_M {
mov reg, reg, t0
ld reg, ds, [scale, index, base], disp, dataSize=1
};
def macroop MOVZX_B_R_P {
rdip t7
mov reg, reg, t0
ld reg, ds, [0, t0, t7], disp, dataSize=1
};
def macroop MOVZX_B_M_R {
mov t1, t1, t0
mov t1, t1, reg, dataSize=1
st t1, ds, [scale, index, base], disp
};
def macroop MOVZX_B_P_R {
rdip t7
mov t1, t1, t0
mov t1, t1, reg, dataSize=1
st t1, ds, [0, t0, t7], disp
};
def macroop MOVZX_W_R_R {
mov reg, reg, t0
mov reg, reg, regm, dataSize=2
};
def macroop MOVZX_W_R_M {
mov reg, reg, t0
ld reg, ds, [scale, index, base], disp, dataSize=2
};
def macroop MOVZX_W_R_P {
rdip t7
mov reg, reg, t0
ld reg, ds, [0, t0, t7], disp, dataSize=2
};
def macroop MOVZX_W_M_R {
mov t1, t1, t0
mov t1, t1, reg, dataSize=2
st t1, ds, [scale, index, base], disp
};
def macroop MOVZX_W_P_R {
rdip t7
mov t1, t1, t0
mov t1, t1, reg, dataSize=2
st t1, ds, [0, t0, t7], disp
};
'''
#let {{
# class MOV(Inst):

22
src/arch/x86/isa/microops/ldstop.isa
View file

@ -325,12 +325,12 @@ def template MicroLdStOpConstructor {{
let {{
class LdStOp(X86Microop):
def __init__(self, data, segment, addr, disp):
def __init__(self, data, segment, addr, disp, dataSize):
self.data = data
[self.scale, self.index, self.base] = addr
self.disp = disp
self.segment = segment
self.dataSize = "env.dataSize"
self.dataSize = dataSize
self.addressSize = "env.addressSize"
def getAllocator(self, *microFlags):
@ -376,8 +376,10 @@ let {{
exec_output += MicroLoadCompleteAcc.subst(iop)
class LoadOp(LdStOp):
def __init__(self, data, segment, addr, disp = 0):
super(LoadOp, self).__init__(data, segment, addr, disp)
def __init__(self, data, segment, addr,
disp = 0, dataSize="env.dataSize"):
super(LoadOp, self).__init__(data, segment,
addr, disp, dataSize)
self.className = Name
self.mnemonic = name
@ -403,8 +405,10 @@ let {{
exec_output += MicroStoreCompleteAcc.subst(iop)
class StoreOp(LdStOp):
def __init__(self, data, segment, addr, disp = 0):
super(StoreOp, self).__init__(data, segment, addr, disp)
def __init__(self, data, segment, addr,
disp = 0, dataSize="env.dataSize"):
super(StoreOp, self).__init__(data, segment,
addr, disp, dataSize)
self.className = Name
self.mnemonic = name
@ -419,8 +423,10 @@ let {{
exec_output += MicroLeaExecute.subst(iop)
class LeaOp(LdStOp):
def __init__(self, data, segment, addr, disp = 0):
super(LeaOp, self).__init__(data, segment, addr, disp)
def __init__(self, data, segment, addr,
disp = 0, dataSize="env.dataSize"):
super(LeaOp, self).__init__(data, segment,
addr, disp, dataSize)
self.className = "Lea"
self.mnemonic = "lea"

16
src/arch/x86/isa/microops/regop.isa
View file

@ -126,12 +126,12 @@ def template MicroRegOpDeclare {{
const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
RegIndex _src1, RegIndex _src2, RegIndex _dest,
uint8_t _dataSize, uint8_t _ext);
uint8_t _dataSize, uint16_t _ext);
%(class_name)s(ExtMachInst _machInst,
const char * instMnem,
RegIndex _src1, RegIndex _src2, RegIndex _dest,
uint8_t _dataSize, uint8_t _ext);
uint8_t _dataSize, uint16_t _ext);
%(BasicExecDeclare)s
};
@ -149,12 +149,12 @@ def template MicroRegOpImmDeclare {{
const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
RegIndex _src1, uint8_t _imm8, RegIndex _dest,
uint8_t _dataSize, uint8_t _ext);
uint8_t _dataSize, uint16_t _ext);
%(class_name)sImm(ExtMachInst _machInst,
const char * instMnem,
RegIndex _src1, uint8_t _imm8, RegIndex _dest,
uint8_t _dataSize, uint8_t _ext);
uint8_t _dataSize, uint16_t _ext);
%(BasicExecDeclare)s
};
@ -170,7 +170,7 @@ def template MicroRegOpConstructor {{
inline %(class_name)s::%(class_name)s(
ExtMachInst machInst, const char * instMnem,
RegIndex _src1, RegIndex _src2, RegIndex _dest,
uint8_t _dataSize, uint8_t _ext) :
uint8_t _dataSize, uint16_t _ext) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
false, false, false, false,
_src1, _src2, _dest, _dataSize, _ext,
@ -183,7 +183,7 @@ def template MicroRegOpConstructor {{
ExtMachInst machInst, const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
RegIndex _src1, RegIndex _src2, RegIndex _dest,
uint8_t _dataSize, uint8_t _ext) :
uint8_t _dataSize, uint16_t _ext) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
isMicro, isDelayed, isFirst, isLast,
_src1, _src2, _dest, _dataSize, _ext,
@ -203,7 +203,7 @@ def template MicroRegOpImmConstructor {{
inline %(class_name)sImm::%(class_name)sImm(
ExtMachInst machInst, const char * instMnem,
RegIndex _src1, uint8_t _imm8, RegIndex _dest,
uint8_t _dataSize, uint8_t _ext) :
uint8_t _dataSize, uint16_t _ext) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
false, false, false, false,
_src1, _imm8, _dest, _dataSize, _ext,
@ -216,7 +216,7 @@ def template MicroRegOpImmConstructor {{
ExtMachInst machInst, const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
RegIndex _src1, uint8_t _imm8, RegIndex _dest,
uint8_t _dataSize, uint8_t _ext) :
uint8_t _dataSize, uint16_t _ext) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
isMicro, isDelayed, isFirst, isLast,
_src1, _imm8, _dest, _dataSize, _ext,

1
src/arch/x86/isa/operands.isa
View file

@ -102,6 +102,7 @@ def operands {{
'Base': ('IntReg', 'uqw', 'base', 'IsInteger', 4),
'Index': ('IntReg', 'uqw', 'index', 'IsInteger', 5),
'Data': ('IntReg', 'uqw', 'data', 'IsInteger', 6),
'rax': ('IntReg', 'uqw', 'INTREG_RAX', 'IsInteger', 7),
'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 10),
'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20),
'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)

5
src/arch/x86/syscallreturn.hh
View file

@ -59,16 +59,15 @@
#define __ARCH_X86_SYSCALLRETURN_HH__
#include "base/misc.hh"
#include "cpu/thread_context.hh"
#include "sim/syscallreturn.hh"
class ThreadContext;
namespace X86ISA
{
static inline void setSyscallReturn(SyscallReturn return_value,
ThreadContext * tc)
{
panic("setSyscallReturn not implemented!\n");
tc->setIntReg(INTREG_RAX, return_value.value());
}
};