Gabe Black 2f72d6a1f4 X86: Fix store microops so they don't drop faults in timing mode. ... If a fault was returned by the CPU when a store initiated it's write, the store instruction would ignore the fault. This change fixes that.		2011-07-02 22:31:22 -07:00
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alpha	inorder/dtb: make sure DTB translate correct address	2011-06-19 21:43:41 -04:00
arm	cpus/isa: add a != operator for pcstate	2011-06-19 21:43:33 -04:00
generic	arch: print next upc correctly	2011-06-28 18:27:38 -05:00
mips	mips: fix nmsub and nmadd definitions	2011-06-22 23:35:21 -04:00
noisa	SCons: Support building without an ISA	2010-11-19 18:00:39 -06:00
power	scons: rename TraceFlags to DebugFlags	2011-06-02 17:36:21 -07:00
sparc	sparc: init. cache state in TLB	2011-06-19 21:43:35 -04:00
x86	X86: Fix store microops so they don't drop faults in timing mode.	2011-07-02 22:31:22 -07:00
isa_parser.py	ISA parser: Loosen the regular expressions matching filenames.	2011-06-07 00:46:54 -07:00
micro_asm.py	scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access	2009-09-22 15:24:16 -07:00
micro_asm_test.py	Add a second section to make sure the ROM is extended properly.	2007-05-31 22:21:21 +00:00
SConscript	scons: rename TraceFlags to DebugFlags	2011-06-02 17:36:21 -07:00