2008-02-27 05:39:22 +01:00
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// Copyright (c) 2008 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
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2007-06-13 20:05:08 +02:00
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// All rights reserved.
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//
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// Redistribution and use of this software in source and binary forms,
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// with or without modification, are permitted provided that the
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// following conditions are met:
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//
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// The software must be used only for Non-Commercial Use which means any
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// use which is NOT directed to receiving any direct monetary
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// compensation for, or commercial advantage from such use. Illustrative
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// examples of non-commercial use are academic research, personal study,
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// teaching, education and corporate research & development.
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// Illustrative examples of commercial use are distributing products for
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// commercial advantage and providing services using the software for
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// commercial advantage.
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//
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// If you wish to use this software or functionality therein that may be
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// covered by patents for commercial use, please contact:
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// Director of Intellectual Property Licensing
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// Office of Strategy and Technology
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// Hewlett-Packard Company
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// 1501 Page Mill Road
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// Palo Alto, California 94304
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//
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// Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer. Redistributions
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// in binary form must reproduce the above copyright notice, this list of
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// conditions and the following disclaimer in the documentation and/or
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// other materials provided with the distribution. Neither the name of
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// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission. No right of
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// sublicense is granted herewith. Derivatives of the software and
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// output created using the software may be prepared, but only for
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// Non-Commercial Uses. Derivatives of the software may be shared with
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// others provided: (i) the others agree to abide by the list of
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// conditions herein which includes the Non-Commercial Use restrictions;
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// and (ii) such Derivatives of the software include the above copyright
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// notice to acknowledge the contribution from this software where
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// applicable, this list of conditions and the disclaimer below.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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//////////////////////////////////////////////////////////////////////////
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//
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// LdStOp Microop templates
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//
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//////////////////////////////////////////////////////////////////////////
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2007-06-20 17:02:50 +02:00
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// LEA template
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def template MicroLeaExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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%(code)s;
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template MicroLeaDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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protected:
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void buildMe();
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public:
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%(class_name)s(ExtMachInst _machInst,
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const char * instMnem,
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bool isMicro, bool isDelayed, bool isFirst, bool isLast,
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uint8_t _scale, RegIndex _index, RegIndex _base,
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uint64_t _disp, uint8_t _segment,
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RegIndex _data,
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uint8_t _dataSize, uint8_t _addressSize);
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%(class_name)s(ExtMachInst _machInst,
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const char * instMnem,
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uint8_t _scale, RegIndex _index, RegIndex _base,
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uint64_t _disp, uint8_t _segment,
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RegIndex _data,
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uint8_t _dataSize, uint8_t _addressSize);
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%(BasicExecDeclare)s
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};
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}};
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// Load templates
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2007-06-19 16:18:25 +02:00
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def template MicroLoadExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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2007-11-12 23:37:54 +01:00
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fault = read(xc, EA, Mem, (%(mem_flags)s) | segment);
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2007-07-21 00:02:09 +02:00
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2007-06-19 16:18:25 +02:00
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if(fault == NoFault)
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{
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%(code)s;
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}
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template MicroLoadInitiateAcc {{
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Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
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Trace::InstRecord * traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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2007-11-12 23:37:54 +01:00
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fault = read(xc, EA, Mem, (%(mem_flags)s) | segment);
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2007-06-19 16:18:25 +02:00
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return fault;
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}
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}};
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def template MicroLoadCompleteAcc {{
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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%(CPU_exec_context)s * xc,
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Trace::InstRecord * traceData) const
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{
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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2007-08-27 05:30:36 +02:00
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Mem = pkt->get<typeof(Mem)>();
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2007-06-19 16:18:25 +02:00
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%(code)s;
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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// Store templates
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def template MicroStoreExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s * xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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%(code)s;
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if(fault == NoFault)
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{
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2007-11-12 23:37:54 +01:00
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fault = write(xc, Mem, EA, (%(mem_flags)s) | segment);
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2007-07-27 07:08:35 +02:00
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if(fault == NoFault)
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2007-07-21 00:02:09 +02:00
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{
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2007-07-27 07:08:35 +02:00
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%(op_wb)s;
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2007-07-21 00:02:09 +02:00
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}
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2007-06-19 16:18:25 +02:00
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}
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return fault;
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}
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}};
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def template MicroStoreInitiateAcc {{
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Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
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Trace::InstRecord * traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
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%(code)s;
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if(fault == NoFault)
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{
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2007-11-12 23:37:54 +01:00
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fault = write(xc, Mem, EA, (%(mem_flags)s) | segment);
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2007-07-27 07:08:35 +02:00
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if(fault == NoFault)
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2007-07-21 00:02:09 +02:00
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{
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2007-07-27 07:08:35 +02:00
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%(op_wb)s;
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2007-07-21 00:02:09 +02:00
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}
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2007-06-19 16:18:25 +02:00
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}
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return fault;
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}
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}};
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def template MicroStoreCompleteAcc {{
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Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc,
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Trace::InstRecord * traceData) const
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{
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return NoFault;
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}
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}};
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// Common templates
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//This delcares the initiateAcc function in memory operations
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def template InitiateAccDeclare {{
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Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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//This declares the completeAcc function in memory operations
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def template CompleteAccDeclare {{
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Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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def template MicroLdStOpDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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protected:
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2007-06-13 20:05:08 +02:00
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void buildMe();
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public:
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%(class_name)s(ExtMachInst _machInst,
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const char * instMnem,
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bool isMicro, bool isDelayed, bool isFirst, bool isLast,
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uint8_t _scale, RegIndex _index, RegIndex _base,
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uint64_t _disp, uint8_t _segment,
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RegIndex _data,
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uint8_t _dataSize, uint8_t _addressSize);
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%(class_name)s(ExtMachInst _machInst,
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const char * instMnem,
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uint8_t _scale, RegIndex _index, RegIndex _base,
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uint64_t _disp, uint8_t _segment,
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RegIndex _data,
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uint8_t _dataSize, uint8_t _addressSize);
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%(BasicExecDeclare)s
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2007-06-19 16:18:25 +02:00
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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2007-06-13 20:05:08 +02:00
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};
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}};
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def template MicroLdStOpConstructor {{
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inline void %(class_name)s::buildMe()
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{
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%(constructor)s;
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}
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inline %(class_name)s::%(class_name)s(
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ExtMachInst machInst, const char * instMnem,
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uint8_t _scale, RegIndex _index, RegIndex _base,
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uint64_t _disp, uint8_t _segment,
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RegIndex _data,
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uint8_t _dataSize, uint8_t _addressSize) :
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%(base_class)s(machInst, "%(mnemonic)s", instMnem,
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2007-06-19 16:18:25 +02:00
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false, false, false, false,
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_scale, _index, _base,
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_disp, _segment, _data,
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_dataSize, _addressSize, %(op_class)s)
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2007-06-13 20:05:08 +02:00
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{
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buildMe();
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}
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inline %(class_name)s::%(class_name)s(
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ExtMachInst machInst, const char * instMnem,
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bool isMicro, bool isDelayed, bool isFirst, bool isLast,
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uint8_t _scale, RegIndex _index, RegIndex _base,
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2007-06-19 16:18:25 +02:00
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uint64_t _disp, uint8_t _segment,
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RegIndex _data,
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uint8_t _dataSize, uint8_t _addressSize) :
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2007-06-13 20:05:08 +02:00
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%(base_class)s(machInst, "%(mnemonic)s", instMnem,
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2007-06-19 16:18:25 +02:00
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isMicro, isDelayed, isFirst, isLast,
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_scale, _index, _base,
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_disp, _segment, _data,
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_dataSize, _addressSize, %(op_class)s)
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2007-06-13 20:05:08 +02:00
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{
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buildMe();
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}
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}};
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2007-06-19 16:18:25 +02:00
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let {{
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class LdStOp(X86Microop):
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2007-10-13 01:37:55 +02:00
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def __init__(self, data, segment, addr, disp, dataSize, addressSize):
|
2007-06-19 16:18:25 +02:00
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self.data = data
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[self.scale, self.index, self.base] = addr
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self.disp = disp
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self.segment = segment
|
2007-07-20 00:15:47 +02:00
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self.dataSize = dataSize
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2007-10-13 01:37:55 +02:00
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self.addressSize = addressSize
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2007-06-19 16:18:25 +02:00
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def getAllocator(self, *microFlags):
|
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allocator = '''new %(class_name)s(machInst, mnemonic
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%(flags)s, %(scale)s, %(index)s, %(base)s,
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%(disp)s, %(segment)s, %(data)s,
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%(dataSize)s, %(addressSize)s)''' % {
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"class_name" : self.className,
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"flags" : self.microFlagsText(microFlags),
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"scale" : self.scale, "index" : self.index,
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"base" : self.base,
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"disp" : self.disp,
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"segment" : self.segment, "data" : self.data,
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"dataSize" : self.dataSize, "addressSize" : self.addressSize}
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return allocator
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}};
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let {{
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# Make these empty strings so that concatenating onto
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# them will always work.
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header_output = ""
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decoder_output = ""
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exec_output = ""
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|
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|
2007-08-05 05:12:54 +02:00
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calculateEA = "EA = SegBase + scale * Index + Base + disp;"
|
2007-06-19 16:18:25 +02:00
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|
2007-10-03 07:08:09 +02:00
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def defineMicroLoadOp(mnemonic, code, mem_flags=0):
|
2007-06-19 16:18:25 +02:00
|
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|
global header_output
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|
|
global decoder_output
|
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|
|
global exec_output
|
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|
|
global microopClasses
|
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|
|
Name = mnemonic
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|
|
name = mnemonic.lower()
|
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|
|
|
|
|
|
# Build up the all register version of this micro op
|
2007-07-15 02:14:19 +02:00
|
|
|
iop = InstObjParams(name, Name, 'X86ISA::LdStOp',
|
2007-10-03 07:08:09 +02:00
|
|
|
{"code": code,
|
|
|
|
"ea_code": calculateEA,
|
|
|
|
"mem_flags": mem_flags})
|
2007-06-19 16:18:25 +02:00
|
|
|
header_output += MicroLdStOpDeclare.subst(iop)
|
|
|
|
decoder_output += MicroLdStOpConstructor.subst(iop)
|
|
|
|
exec_output += MicroLoadExecute.subst(iop)
|
|
|
|
exec_output += MicroLoadInitiateAcc.subst(iop)
|
|
|
|
exec_output += MicroLoadCompleteAcc.subst(iop)
|
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|
|
|
|
|
|
class LoadOp(LdStOp):
|
2007-10-13 01:37:55 +02:00
|
|
|
def __init__(self, data, segment, addr, disp = 0,
|
|
|
|
dataSize="env.dataSize", addressSize="env.addressSize"):
|
2007-07-20 00:15:47 +02:00
|
|
|
super(LoadOp, self).__init__(data, segment,
|
2007-10-13 01:37:55 +02:00
|
|
|
addr, disp, dataSize, addressSize)
|
2007-06-19 16:18:25 +02:00
|
|
|
self.className = Name
|
|
|
|
self.mnemonic = name
|
|
|
|
|
|
|
|
microopClasses[name] = LoadOp
|
|
|
|
|
|
|
|
defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);')
|
2007-10-03 07:08:09 +02:00
|
|
|
defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);', 'StoreCheck')
|
2007-08-30 05:36:12 +02:00
|
|
|
defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;')
|
2007-06-19 16:18:25 +02:00
|
|
|
|
2007-10-03 07:08:09 +02:00
|
|
|
def defineMicroStoreOp(mnemonic, code, mem_flags=0):
|
2007-06-19 16:18:25 +02:00
|
|
|
global header_output
|
|
|
|
global decoder_output
|
|
|
|
global exec_output
|
|
|
|
global microopClasses
|
|
|
|
Name = mnemonic
|
|
|
|
name = mnemonic.lower()
|
|
|
|
|
|
|
|
# Build up the all register version of this micro op
|
2007-07-15 02:14:19 +02:00
|
|
|
iop = InstObjParams(name, Name, 'X86ISA::LdStOp',
|
2007-10-03 07:08:09 +02:00
|
|
|
{"code": code,
|
|
|
|
"ea_code": calculateEA,
|
|
|
|
"mem_flags": mem_flags})
|
2007-06-19 16:18:25 +02:00
|
|
|
header_output += MicroLdStOpDeclare.subst(iop)
|
|
|
|
decoder_output += MicroLdStOpConstructor.subst(iop)
|
|
|
|
exec_output += MicroStoreExecute.subst(iop)
|
|
|
|
exec_output += MicroStoreInitiateAcc.subst(iop)
|
|
|
|
exec_output += MicroStoreCompleteAcc.subst(iop)
|
|
|
|
|
|
|
|
class StoreOp(LdStOp):
|
2007-10-13 01:37:55 +02:00
|
|
|
def __init__(self, data, segment, addr, disp = 0,
|
|
|
|
dataSize="env.dataSize", addressSize="env.addressSize"):
|
2007-07-20 00:15:47 +02:00
|
|
|
super(StoreOp, self).__init__(data, segment,
|
2007-10-13 01:37:55 +02:00
|
|
|
addr, disp, dataSize, addressSize)
|
2007-06-19 16:18:25 +02:00
|
|
|
self.className = Name
|
|
|
|
self.mnemonic = name
|
|
|
|
|
|
|
|
microopClasses[name] = StoreOp
|
|
|
|
|
2007-07-19 02:45:06 +02:00
|
|
|
defineMicroStoreOp('St', 'Mem = Data;')
|
2007-08-30 05:36:12 +02:00
|
|
|
defineMicroStoreOp('Stfp', 'Mem = FpData.uqw;')
|
2007-10-22 03:44:50 +02:00
|
|
|
defineMicroStoreOp('Stupd', '''
|
|
|
|
Mem = Data;
|
|
|
|
Base = merge(Base, EA - SegBase, addressSize);
|
|
|
|
''');
|
|
|
|
|
2007-06-20 17:02:50 +02:00
|
|
|
|
2007-07-15 02:14:19 +02:00
|
|
|
iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp',
|
2007-10-03 07:08:09 +02:00
|
|
|
{"code": "Data = merge(Data, EA, dataSize);",
|
|
|
|
"ea_code": calculateEA,
|
|
|
|
"mem_flags": 0})
|
2007-06-20 17:02:50 +02:00
|
|
|
header_output += MicroLeaDeclare.subst(iop)
|
|
|
|
decoder_output += MicroLdStOpConstructor.subst(iop)
|
|
|
|
exec_output += MicroLeaExecute.subst(iop)
|
|
|
|
|
|
|
|
class LeaOp(LdStOp):
|
2007-10-13 01:37:55 +02:00
|
|
|
def __init__(self, data, segment, addr, disp = 0,
|
|
|
|
dataSize="env.dataSize", addressSize="env.addressSize"):
|
2007-07-20 00:15:47 +02:00
|
|
|
super(LeaOp, self).__init__(data, segment,
|
2007-10-13 01:37:55 +02:00
|
|
|
addr, disp, dataSize, addressSize)
|
2007-06-20 17:02:50 +02:00
|
|
|
self.className = "Lea"
|
|
|
|
self.mnemonic = "lea"
|
|
|
|
|
|
|
|
microopClasses["lea"] = LeaOp
|
2007-10-22 23:30:56 +02:00
|
|
|
|
|
|
|
|
2008-02-27 05:39:22 +01:00
|
|
|
iop = InstObjParams("tia", "Tia", 'X86ISA::LdStOp',
|
|
|
|
{"code": "xc->demapPage(EA, 0);",
|
|
|
|
"ea_code": calculateEA,
|
|
|
|
"mem_flags": 0})
|
|
|
|
header_output += MicroLeaDeclare.subst(iop)
|
|
|
|
decoder_output += MicroLdStOpConstructor.subst(iop)
|
|
|
|
exec_output += MicroLeaExecute.subst(iop)
|
|
|
|
|
|
|
|
class TiaOp(LdStOp):
|
|
|
|
def __init__(self, segment, addr, disp = 0,
|
|
|
|
dataSize="env.dataSize", addressSize="env.addressSize"):
|
|
|
|
super(TiaOp, self).__init__("NUM_INTREGS", segment,
|
|
|
|
addr, disp, dataSize, addressSize)
|
|
|
|
self.className = "Tia"
|
|
|
|
self.mnemonic = "tia"
|
|
|
|
|
|
|
|
microopClasses["tia"] = TiaOp
|
|
|
|
|
2007-10-22 23:30:56 +02:00
|
|
|
iop = InstObjParams("cda", "Cda", 'X86ISA::LdStOp',
|
|
|
|
{"code": '''
|
|
|
|
Addr paddr;
|
|
|
|
fault = xc->translateDataWriteAddr(EA, paddr,
|
|
|
|
dataSize, (1 << segment));
|
|
|
|
''',
|
|
|
|
"ea_code": calculateEA})
|
|
|
|
header_output += MicroLeaDeclare.subst(iop)
|
|
|
|
decoder_output += MicroLdStOpConstructor.subst(iop)
|
|
|
|
exec_output += MicroLeaExecute.subst(iop)
|
|
|
|
|
|
|
|
class CdaOp(LdStOp):
|
|
|
|
def __init__(self, segment, addr, disp = 0,
|
|
|
|
dataSize="env.dataSize", addressSize="env.addressSize"):
|
|
|
|
super(CdaOp, self).__init__("NUM_INTREGS", segment,
|
|
|
|
addr, disp, dataSize, addressSize)
|
|
|
|
self.className = "Cda"
|
|
|
|
self.mnemonic = "cda"
|
|
|
|
|
|
|
|
microopClasses["cda"] = CdaOp
|
2007-06-19 16:18:25 +02:00
|
|
|
}};
|
|
|
|
|