X86: Don't read in dest regs if all bits are replaced.
In x86, 32 and 64 bit writes to registers in which registers appear to be 32 or 64 bits wide overwrite all bits of the destination register. This change removes false dependencies in these cases where the previous value of a register doesn't need to be read to write a new value. New versions of most microops are created that have a "Big" suffix which simply overwrite their destination, and the right version to use is selected during microop allocation based on the selected data size. This does not change the performance of the O3 CPU model significantly, I assume because there are other false dependencies from the condition code bits in the flags register.
This commit is contained in:
Gabe Black
parent
399e095510
commit
4e1adf85f7
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@ -301,6 +301,46 @@ let {{
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"dataSize" : self.dataSize, "addressSize" : self.addressSize,
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"memFlags" : self.memFlags}
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return allocator
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class BigLdStOp(X86Microop):
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def __init__(self, data, segment, addr, disp,
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dataSize, addressSize, baseFlags, atCPL0, prefetch):
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self.data = data
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[self.scale, self.index, self.base] = addr
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self.disp = disp
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self.segment = segment
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self.dataSize = dataSize
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self.addressSize = addressSize
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self.memFlags = baseFlags
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if atCPL0:
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self.memFlags += " | (CPL0FlagBit << FlagShift)"
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if prefetch:
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self.memFlags += " | Request::PREFETCH"
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self.memFlags += " | (machInst.legacy.addr ? " + \
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"(AddrSizeFlagBit << FlagShift) : 0)"
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def getAllocator(self, microFlags):
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allocString = '''
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(%(dataSize)s >= 4) ?
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(StaticInstPtr)(new %(class_name)sBig(machInst,
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macrocodeBlock, %(flags)s, %(scale)s, %(index)s,
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%(base)s, %(disp)s, %(segment)s, %(data)s,
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%(dataSize)s, %(addressSize)s, %(memFlags)s)) :
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(StaticInstPtr)(new %(class_name)s(machInst,
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macrocodeBlock, %(flags)s, %(scale)s, %(index)s,
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%(base)s, %(disp)s, %(segment)s, %(data)s,
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%(dataSize)s, %(addressSize)s, %(memFlags)s))
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'''
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allocator = allocString % {
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"class_name" : self.className,
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"flags" : self.microFlagsText(microFlags),
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"scale" : self.scale, "index" : self.index,
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"base" : self.base,
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"disp" : self.disp,
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"segment" : self.segment, "data" : self.data,
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"dataSize" : self.dataSize, "addressSize" : self.addressSize,
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"memFlags" : self.memFlags}
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return allocator
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}};
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let {{
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@ -315,7 +355,8 @@ let {{
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EA = bits(SegBase + scale * Index + Base + disp, addressSize * 8 - 1, 0);
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'''
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def defineMicroLoadOp(mnemonic, code, mem_flags="0"):
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def defineMicroLoadOp(mnemonic, code, bigCode='',
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mem_flags="0", big=True):
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global header_output
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global decoder_output
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global exec_output
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@ -324,16 +365,22 @@ let {{
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name = mnemonic.lower()
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# Build up the all register version of this micro op
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iop = InstObjParams(name, Name, 'X86ISA::LdStOp',
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{"code": code,
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"ea_code": calculateEA})
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header_output += MicroLdStOpDeclare.subst(iop)
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decoder_output += MicroLdStOpConstructor.subst(iop)
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exec_output += MicroLoadExecute.subst(iop)
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exec_output += MicroLoadInitiateAcc.subst(iop)
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exec_output += MicroLoadCompleteAcc.subst(iop)
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iops = [InstObjParams(name, Name, 'X86ISA::LdStOp',
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{"code": code, "ea_code": calculateEA})]
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if big:
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iops += [InstObjParams(name, Name + "Big", 'X86ISA::LdStOp',
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{"code": bigCode, "ea_code": calculateEA})]
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for iop in iops:
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header_output += MicroLdStOpDeclare.subst(iop)
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decoder_output += MicroLdStOpConstructor.subst(iop)
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exec_output += MicroLoadExecute.subst(iop)
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exec_output += MicroLoadInitiateAcc.subst(iop)
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exec_output += MicroLoadCompleteAcc.subst(iop)
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class LoadOp(LdStOp):
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base = LdStOp
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if big:
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base = BigLdStOp
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class LoadOp(base):
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def __init__(self, data, segment, addr, disp = 0,
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dataSize="env.dataSize",
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addressSize="env.addressSize",
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@ -346,12 +393,15 @@ let {{
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microopClasses[name] = LoadOp
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defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);')
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defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);',
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'Data = Mem & mask(dataSize * 8);')
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defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);',
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'(StoreCheck << FlagShift)')
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'Data = Mem & mask(dataSize * 8);',
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'(StoreCheck << FlagShift)')
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defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);',
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'(StoreCheck << FlagShift) | Request::LOCKED')
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defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;')
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'Data = Mem & mask(dataSize * 8);',
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'(StoreCheck << FlagShift) | Request::LOCKED')
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defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;', big = False)
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def defineMicroStoreOp(mnemonic, code, \
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postCode="", completeCode="", mem_flags="0"):
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@ -114,8 +114,16 @@ let {{
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self.dataSize = dataSize
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def getAllocator(self, microFlags):
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allocator = '''new %(class_name)s(machInst, macrocodeBlock,
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%(flags)s, %(dest)s, %(imm)s, %(dataSize)s)''' % {
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allocString = '''
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(%(dataSize)s >= 4) ?
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(StaticInstPtr)(new %(class_name)sBig(machInst,
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macrocodeBlock, %(flags)s, %(dest)s, %(imm)s,
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%(dataSize)s)) :
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(StaticInstPtr)(new %(class_name)s(machInst,
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macrocodeBlock, %(flags)s, %(dest)s, %(imm)s,
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%(dataSize)s))
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'''
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allocator = allocString % {
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"class_name" : self.className,
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"mnemonic" : self.mnemonic,
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"flags" : self.microFlagsText(microFlags),
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@ -152,12 +160,15 @@ let {{
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let {{
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# Build up the all register version of this micro op
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iop = InstObjParams("limm", "Limm", 'X86MicroopBase',
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{"code" : "DestReg = merge(DestReg, imm, dataSize);"})
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header_output += MicroLimmOpDeclare.subst(iop)
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decoder_output += MicroLimmOpConstructor.subst(iop)
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decoder_output += MicroLimmOpDisassembly.subst(iop)
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exec_output += MicroLimmOpExecute.subst(iop)
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iops = [InstObjParams("limm", "Limm", 'X86MicroopBase',
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{"code" : "DestReg = merge(DestReg, imm, dataSize);"}),
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InstObjParams("limm", "LimmBig", 'X86MicroopBase',
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{"code" : "DestReg = imm & mask(dataSize * 8);"})]
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for iop in iops:
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header_output += MicroLimmOpDeclare.subst(iop)
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decoder_output += MicroLimmOpConstructor.subst(iop)
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decoder_output += MicroLimmOpDisassembly.subst(iop)
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exec_output += MicroLimmOpExecute.subst(iop)
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iop = InstObjParams("lfpimm", "Lfpimm", 'X86MicroopBase',
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{"code" : "FpDestReg.uqw = imm"})
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@ -224,8 +224,8 @@ let {{
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MicroRegOpExecute)
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class RegOpMeta(type):
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def buildCppClasses(self, name, Name, suffix, \
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code, flag_code, cond_check, else_code, cond_control_flag_init):
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def buildCppClasses(self, name, Name, suffix, code, big_code, \
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flag_code, cond_check, else_code, cond_control_flag_init):
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# Globals to stick the output in
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global header_output
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@ -235,11 +235,13 @@ let {{
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# Stick all the code together so it can be searched at once
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allCode = "|".join((code, flag_code, cond_check, else_code,
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cond_control_flag_init))
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allBigCode = "|".join((big_code, flag_code, cond_check, else_code,
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cond_control_flag_init))
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# If op2 is used anywhere, make register and immediate versions
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# of this code.
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matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?")
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match = matcher.search(allCode)
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match = matcher.search(allCode + allBigCode)
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if match:
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typeQual = ""
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if match.group("typeQual"):
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@ -247,6 +249,7 @@ let {{
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src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual)
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self.buildCppClasses(name, Name, suffix,
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matcher.sub(src2_name, code),
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matcher.sub(src2_name, big_code),
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matcher.sub(src2_name, flag_code),
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matcher.sub(src2_name, cond_check),
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matcher.sub(src2_name, else_code),
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@ -254,6 +257,7 @@ let {{
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imm_name = "%simm8" % match.group("prefix")
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self.buildCppClasses(name + "i", Name, suffix + "Imm",
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matcher.sub(imm_name, code),
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matcher.sub(imm_name, big_code),
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matcher.sub(imm_name, flag_code),
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matcher.sub(imm_name, cond_check),
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matcher.sub(imm_name, else_code),
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@ -264,27 +268,32 @@ let {{
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# a version without it and fix up this version to use it.
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if flag_code != "" or cond_check != "true":
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self.buildCppClasses(name, Name, suffix,
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code, "", "true", else_code, "")
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code, big_code, "", "true", else_code, "")
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suffix = "Flags" + suffix
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# If psrc1 or psrc2 is used, we need to actually insert code to
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# compute it.
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matcher = re.compile("(?<!\w)psrc1(?!\w)")
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if matcher.search(allCode):
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code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code
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matcher = re.compile("(?<!\w)psrc2(?!\w)")
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if matcher.search(allCode):
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code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code
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# Also make available versions which do sign extension
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matcher = re.compile("(?<!\w)spsrc1(?!\w)")
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if matcher.search(allCode):
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code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code
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matcher = re.compile("(?<!\w)spsrc2(?!\w)")
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if matcher.search(allCode):
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code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code
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matcher = re.compile("(?<!\w)simm8(?!\w)")
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if matcher.search(allCode):
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code = "int8_t simm8 = imm8;" + code
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for (big, all) in ((False, allCode), (True, allBigCode)):
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prefix = ""
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for (rex, decl) in (
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("(?<!\w)psrc1(?!\w)",
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"uint64_t psrc1 = pick(SrcReg1, 0, dataSize);"),
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("(?<!\w)psrc2(?!\w)",
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"uint64_t psrc2 = pick(SrcReg2, 1, dataSize);"),
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("(?<!\w)spsrc1(?!\w)",
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"int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);"),
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("(?<!\w)spsrc2(?!\w)",
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"int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);"),
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("(?<!\w)simm8(?!\w)",
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"int8_t simm8 = imm8;")):
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matcher = re.compile(rex)
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if matcher.search(all):
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prefix += decl + "\n"
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if big:
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if big_code != "":
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big_code = prefix + big_code
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else:
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code = prefix + code
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base = "X86ISA::RegOp"
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@ -297,17 +306,26 @@ let {{
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templates = immTemplates
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# Get everything ready for the substitution
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iop = InstObjParams(name, Name + suffix, base,
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iops = [InstObjParams(name, Name + suffix, base,
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{"code" : code,
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"flag_code" : flag_code,
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"cond_check" : cond_check,
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"else_code" : else_code,
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"cond_control_flag_init": cond_control_flag_init})
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"cond_control_flag_init" : cond_control_flag_init})]
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if big_code != "":
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iops += [InstObjParams(name, Name + suffix + "Big", base,
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{"code" : big_code,
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"flag_code" : flag_code,
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"cond_check" : cond_check,
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"else_code" : else_code,
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"cond_control_flag_init" :
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cond_control_flag_init})]
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# Generate the actual code (finally!)
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header_output += templates[0].subst(iop)
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decoder_output += templates[1].subst(iop)
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exec_output += templates[2].subst(iop)
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for iop in iops:
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header_output += templates[0].subst(iop)
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decoder_output += templates[1].subst(iop)
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exec_output += templates[2].subst(iop)
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def __new__(mcls, Name, bases, dict):
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@ -322,14 +340,16 @@ let {{
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cls.className = Name
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cls.base_mnemonic = name
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code = cls.code
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big_code = cls.big_code
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flag_code = cls.flag_code
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cond_check = cls.cond_check
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else_code = cls.else_code
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cond_control_flag_init = cls.cond_control_flag_init
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# Set up the C++ classes
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mcls.buildCppClasses(cls, name, Name, "", code, flag_code,
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cond_check, else_code, cond_control_flag_init)
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mcls.buildCppClasses(cls, name, Name, "", code, big_code,
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flag_code, cond_check, else_code,
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cond_control_flag_init)
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# Hook into the microassembler dict
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global microopClasses
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@ -352,6 +372,7 @@ let {{
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abstract = True
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# Default template parameter values
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big_code = ""
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flag_code = ""
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cond_check = "true"
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else_code = ";"
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@ -372,19 +393,41 @@ let {{
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self.className += "Flags"
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def getAllocator(self, microFlags):
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className = self.className
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if self.mnemonic == self.base_mnemonic + 'i':
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className += "Imm"
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allocator = '''new %(class_name)s(machInst, macrocodeBlock,
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%(flags)s, %(src1)s, %(op2)s, %(dest)s,
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%(dataSize)s, %(ext)s)''' % {
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"class_name" : className,
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"flags" : self.microFlagsText(microFlags),
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"src1" : self.src1, "op2" : self.op2,
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"dest" : self.dest,
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"dataSize" : self.dataSize,
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"ext" : self.ext}
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return allocator
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if self.big_code != "":
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className = self.className
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if self.mnemonic == self.base_mnemonic + 'i':
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className += "Imm"
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allocString = '''
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(%(dataSize)s >= 4) ?
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(StaticInstPtr)(new %(class_name)sBig(machInst,
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macrocodeBlock, %(flags)s, %(src1)s, %(op2)s,
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%(dest)s, %(dataSize)s, %(ext)s)) :
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(StaticInstPtr)(new %(class_name)s(machInst,
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macrocodeBlock, %(flags)s, %(src1)s, %(op2)s,
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%(dest)s, %(dataSize)s, %(ext)s))
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'''
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allocator = allocString % {
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"class_name" : className,
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"flags" : self.microFlagsText(microFlags),
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"src1" : self.src1, "op2" : self.op2,
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"dest" : self.dest,
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"dataSize" : self.dataSize,
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"ext" : self.ext}
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return allocator
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else:
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className = self.className
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if self.mnemonic == self.base_mnemonic + 'i':
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className += "Imm"
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allocator = '''new %(class_name)s(machInst, macrocodeBlock,
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%(flags)s, %(src1)s, %(op2)s, %(dest)s,
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%(dataSize)s, %(ext)s)''' % {
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"class_name" : className,
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"flags" : self.microFlagsText(microFlags),
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"src1" : self.src1, "op2" : self.op2,
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"dest" : self.dest,
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"dataSize" : self.dataSize,
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"ext" : self.ext}
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return allocator
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class LogicRegOp(RegOp):
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abstract = True
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@ -429,30 +472,43 @@ let {{
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class Add(FlagRegOp):
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code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);'
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big_code = 'DestReg = (psrc1 + op2) & mask(dataSize * 8);'
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class Or(LogicRegOp):
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code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);'
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big_code = 'DestReg = (psrc1 | op2) & mask(dataSize * 8);'
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class Adc(FlagRegOp):
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code = '''
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CCFlagBits flags = ccFlagBits;
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DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize);
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'''
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big_code = '''
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CCFlagBits flags = ccFlagBits;
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DestReg = (psrc1 + op2 + flags.cf) & mask(dataSize * 8);
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'''
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class Sbb(SubRegOp):
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code = '''
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CCFlagBits flags = ccFlagBits;
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DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize);
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'''
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big_code = '''
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CCFlagBits flags = ccFlagBits;
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DestReg = (psrc1 - op2 - flags.cf) & mask(dataSize * 8);
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'''
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class And(LogicRegOp):
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code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)'
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big_code = 'DestReg = (psrc1 & op2) & mask(dataSize * 8)'
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|
||||
class Sub(SubRegOp):
|
||||
code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)'
|
||||
big_code = 'DestReg = (psrc1 - op2) & mask(dataSize * 8)'
|
||||
|
||||
class Xor(LogicRegOp):
|
||||
code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
|
||||
big_code = 'DestReg = (psrc1 ^ op2) & mask(dataSize * 8)'
|
||||
|
||||
class Mul1s(WrRegOp):
|
||||
code = '''
|
||||
|
|
@ -505,6 +561,7 @@ let {{
|
|||
|
||||
class Mulel(RdRegOp):
|
||||
code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
|
||||
big_code = 'DestReg = ProdLow & mask(dataSize * 8);'
|
||||
|
||||
class Muleh(RdRegOp):
|
||||
def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
|
||||
|
|
@ -513,6 +570,7 @@ let {{
|
|||
super(RdRegOp, self).__init__(dest, src1, \
|
||||
"InstRegIndex(NUM_INTREGS)", flags, dataSize)
|
||||
code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);'
|
||||
big_code = 'DestReg = ProdHi & mask(dataSize * 8);'
|
||||
|
||||
# One or two bit divide
|
||||
class Div1(WrRegOp):
|
||||
|
|
@ -540,7 +598,7 @@ let {{
|
|||
|
||||
# Step divide
|
||||
class Div2(RegOp):
|
||||
code = '''
|
||||
divCode = '''
|
||||
uint64_t dividend = Remainder;
|
||||
uint64_t divisor = Divisor;
|
||||
uint64_t quotient = Quotient;
|
||||
|
|
@ -587,11 +645,13 @@ let {{
|
|||
}
|
||||
}
|
||||
//Keep track of how many bits there are still to pull in.
|
||||
DestReg = merge(DestReg, remaining, dataSize);
|
||||
%s
|
||||
//Record the final results
|
||||
Remainder = remainder;
|
||||
Quotient = quotient;
|
||||
'''
|
||||
code = divCode % "DestReg = merge(DestReg, remaining, dataSize);"
|
||||
big_code = divCode % "DestReg = remaining & mask(dataSize * 8);"
|
||||
flag_code = '''
|
||||
if (remaining == 0)
|
||||
ccFlagBits = ccFlagBits | (ext & EZFBit);
|
||||
|
|
@ -601,9 +661,11 @@ let {{
|
|||
|
||||
class Divq(RdRegOp):
|
||||
code = 'DestReg = merge(SrcReg1, Quotient, dataSize);'
|
||||
big_code = 'DestReg = Quotient & mask(dataSize * 8);'
|
||||
|
||||
class Divr(RdRegOp):
|
||||
code = 'DestReg = merge(SrcReg1, Remainder, dataSize);'
|
||||
big_code = 'DestReg = Remainder & mask(dataSize * 8);'
|
||||
|
||||
class Mov(CondRegOp):
|
||||
code = 'DestReg = merge(SrcReg1, op2, dataSize)'
|
||||
|
|
@ -616,6 +678,10 @@ let {{
|
|||
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
||||
DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize);
|
||||
'''
|
||||
big_code = '''
|
||||
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
||||
DestReg = (psrc1 << shiftAmt) & mask(dataSize * 8);
|
||||
'''
|
||||
flag_code = '''
|
||||
// If the shift amount is zero, no flags should be modified.
|
||||
if (shiftAmt) {
|
||||
|
|
@ -641,14 +707,19 @@ let {{
|
|||
'''
|
||||
|
||||
class Srl(RegOp):
|
||||
# Because what happens to the bits shift -in- on a right shift
|
||||
# is not defined in the C/C++ standard, we have to mask them out
|
||||
# to be sure they're zero.
|
||||
code = '''
|
||||
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
||||
// Because what happens to the bits shift -in- on a right shift
|
||||
// is not defined in the C/C++ standard, we have to mask them out
|
||||
// to be sure they're zero.
|
||||
uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
|
||||
DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize);
|
||||
'''
|
||||
big_code = '''
|
||||
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
||||
uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
|
||||
DestReg = (psrc1 >> shiftAmt) & logicalMask;
|
||||
'''
|
||||
flag_code = '''
|
||||
// If the shift amount is zero, no flags should be modified.
|
||||
if (shiftAmt) {
|
||||
|
|
@ -671,15 +742,21 @@ let {{
|
|||
'''
|
||||
|
||||
class Sra(RegOp):
|
||||
# Because what happens to the bits shift -in- on a right shift
|
||||
# is not defined in the C/C++ standard, we have to sign extend
|
||||
# them manually to be sure.
|
||||
code = '''
|
||||
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
||||
// Because what happens to the bits shift -in- on a right shift
|
||||
// is not defined in the C/C++ standard, we have to sign extend
|
||||
// them manually to be sure.
|
||||
uint64_t arithMask = (shiftAmt == 0) ? 0 :
|
||||
-bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
|
||||
DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize);
|
||||
'''
|
||||
big_code = '''
|
||||
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
||||
uint64_t arithMask = (shiftAmt == 0) ? 0 :
|
||||
-bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
|
||||
DestReg = ((psrc1 >> shiftAmt) | arithMask) & mask(dataSize * 8);
|
||||
'''
|
||||
flag_code = '''
|
||||
// If the shift amount is zero, no flags should be modified.
|
||||
if (shiftAmt) {
|
||||
|
|
@ -704,13 +781,11 @@ let {{
|
|||
uint8_t shiftAmt =
|
||||
(op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
||||
uint8_t realShiftAmt = shiftAmt % (dataSize * 8);
|
||||
if(realShiftAmt)
|
||||
{
|
||||
if (realShiftAmt) {
|
||||
uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt);
|
||||
uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt);
|
||||
DestReg = merge(DestReg, top | bottom, dataSize);
|
||||
}
|
||||
else
|
||||
} else
|
||||
DestReg = merge(DestReg, DestReg, dataSize);
|
||||
'''
|
||||
flag_code = '''
|
||||
|
|
@ -739,16 +814,14 @@ let {{
|
|||
uint8_t shiftAmt =
|
||||
(op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
||||
uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);
|
||||
if(realShiftAmt)
|
||||
{
|
||||
if (realShiftAmt) {
|
||||
CCFlagBits flags = ccFlagBits;
|
||||
uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt);
|
||||
if (realShiftAmt > 1)
|
||||
top |= psrc1 << (dataSize * 8 - realShiftAmt + 1);
|
||||
uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt);
|
||||
DestReg = merge(DestReg, top | bottom, dataSize);
|
||||
}
|
||||
else
|
||||
} else
|
||||
DestReg = merge(DestReg, DestReg, dataSize);
|
||||
'''
|
||||
flag_code = '''
|
||||
|
|
@ -780,14 +853,12 @@ let {{
|
|||
uint8_t shiftAmt =
|
||||
(op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
||||
uint8_t realShiftAmt = shiftAmt % (dataSize * 8);
|
||||
if(realShiftAmt)
|
||||
{
|
||||
if (realShiftAmt) {
|
||||
uint64_t top = psrc1 << realShiftAmt;
|
||||
uint64_t bottom =
|
||||
bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt);
|
||||
DestReg = merge(DestReg, top | bottom, dataSize);
|
||||
}
|
||||
else
|
||||
} else
|
||||
DestReg = merge(DestReg, DestReg, dataSize);
|
||||
'''
|
||||
flag_code = '''
|
||||
|
|
@ -816,8 +887,7 @@ let {{
|
|||
uint8_t shiftAmt =
|
||||
(op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
||||
uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);
|
||||
if(realShiftAmt)
|
||||
{
|
||||
if (realShiftAmt) {
|
||||
CCFlagBits flags = ccFlagBits;
|
||||
uint64_t top = psrc1 << realShiftAmt;
|
||||
uint64_t bottom = flags.cf << (realShiftAmt - 1);
|
||||
|
|
@ -826,8 +896,7 @@ let {{
|
|||
bits(psrc1, dataSize * 8 - 1,
|
||||
dataSize * 8 - realShiftAmt + 1);
|
||||
DestReg = merge(DestReg, top | bottom, dataSize);
|
||||
}
|
||||
else
|
||||
} else
|
||||
DestReg = merge(DestReg, DestReg, dataSize);
|
||||
'''
|
||||
flag_code = '''
|
||||
|
|
@ -853,10 +922,10 @@ let {{
|
|||
'''
|
||||
|
||||
class Sld(RegOp):
|
||||
code = '''
|
||||
sldCode = '''
|
||||
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
||||
uint8_t dataBits = dataSize * 8;
|
||||
uint8_t realShiftAmt = shiftAmt % (2 * dataBits);
|
||||
uint8_t realShiftAmt = shiftAmt %% (2 * dataBits);
|
||||
uint64_t result;
|
||||
if (realShiftAmt == 0) {
|
||||
result = psrc1;
|
||||
|
|
@ -867,8 +936,10 @@ let {{
|
|||
result = (DoubleBits << (realShiftAmt - dataBits)) |
|
||||
(psrc1 >> (2 * dataBits - realShiftAmt));
|
||||
}
|
||||
DestReg = merge(DestReg, result, dataSize);
|
||||
%s
|
||||
'''
|
||||
code = sldCode % "DestReg = merge(DestReg, result, dataSize);"
|
||||
big_code = sldCode % "DestReg = result & mask(dataSize * 8);"
|
||||
flag_code = '''
|
||||
// If the shift amount is zero, no flags should be modified.
|
||||
if (shiftAmt) {
|
||||
|
|
@ -899,10 +970,10 @@ let {{
|
|||
'''
|
||||
|
||||
class Srd(RegOp):
|
||||
code = '''
|
||||
srdCode = '''
|
||||
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
||||
uint8_t dataBits = dataSize * 8;
|
||||
uint8_t realShiftAmt = shiftAmt % (2 * dataBits);
|
||||
uint8_t realShiftAmt = shiftAmt %% (2 * dataBits);
|
||||
uint64_t result;
|
||||
if (realShiftAmt == 0) {
|
||||
result = psrc1;
|
||||
|
|
@ -919,8 +990,10 @@ let {{
|
|||
logicalMask) |
|
||||
(psrc1 << (2 * dataBits - realShiftAmt));
|
||||
}
|
||||
DestReg = merge(DestReg, result, dataSize);
|
||||
%s
|
||||
'''
|
||||
code = srdCode % "DestReg = merge(DestReg, result, dataSize);"
|
||||
big_code = srdCode % "DestReg = result & mask(dataSize * 8);"
|
||||
flag_code = '''
|
||||
// If the shift amount is zero, no flags should be modified.
|
||||
if (shiftAmt) {
|
||||
|
|
@ -986,6 +1059,12 @@ let {{
|
|||
ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
|
||||
(ccFlagBits & ~EZFBit);
|
||||
'''
|
||||
big_code = '''
|
||||
int flag = bits(ccFlagBits, imm8);
|
||||
DestReg = flag & mask(dataSize * 8);
|
||||
ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
|
||||
(ccFlagBits & ~EZFBit);
|
||||
'''
|
||||
def __init__(self, dest, imm, flags=None, \
|
||||
dataSize="env.dataSize"):
|
||||
super(Ruflag, self).__init__(dest, \
|
||||
|
|
@ -1000,6 +1079,14 @@ let {{
|
|||
ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
|
||||
(ccFlagBits & ~EZFBit);
|
||||
'''
|
||||
big_code = '''
|
||||
MiscReg flagMask = 0x3F7FDD5;
|
||||
MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask;
|
||||
int flag = bits(flags, imm8);
|
||||
DestReg = flag & mask(dataSize * 8);
|
||||
ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
|
||||
(ccFlagBits & ~EZFBit);
|
||||
'''
|
||||
def __init__(self, dest, imm, flags=None, \
|
||||
dataSize="env.dataSize"):
|
||||
super(Rflag, self).__init__(dest, \
|
||||
|
|
@ -1015,6 +1102,15 @@ let {{
|
|||
val = sign_bit ? (val | ~maskVal) : (val & maskVal);
|
||||
DestReg = merge(DestReg, val, dataSize);
|
||||
'''
|
||||
big_code = '''
|
||||
IntReg val = psrc1;
|
||||
// Mask the bit position so that it wraps.
|
||||
int bitPos = op2 & (dataSize * 8 - 1);
|
||||
int sign_bit = bits(val, bitPos, bitPos);
|
||||
uint64_t maskVal = mask(bitPos+1);
|
||||
val = sign_bit ? (val | ~maskVal) : (val & maskVal);
|
||||
DestReg = val & mask(dataSize * 8);
|
||||
'''
|
||||
flag_code = '''
|
||||
if (!sign_bit)
|
||||
ccFlagBits = ccFlagBits &
|
||||
|
|
@ -1026,12 +1122,13 @@ let {{
|
|||
|
||||
class Zext(RegOp):
|
||||
code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);'
|
||||
big_code = 'DestReg = bits(psrc1, op2, 0) & mask(dataSize * 8);'
|
||||
|
||||
class Rddr(RegOp):
|
||||
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
|
||||
super(Rddr, self).__init__(dest, \
|
||||
src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
|
||||
code = '''
|
||||
rdrCode = '''
|
||||
CR4 cr4 = CR4Op;
|
||||
DR7 dr7 = DR7Op;
|
||||
if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) {
|
||||
|
|
@ -1039,9 +1136,11 @@ let {{
|
|||
} else if (dr7.gd) {
|
||||
fault = new DebugException();
|
||||
} else {
|
||||
DestReg = merge(DestReg, DebugSrc1, dataSize);
|
||||
%s
|
||||
}
|
||||
'''
|
||||
code = rdrCode % "DestReg = merge(DestReg, DebugSrc1, dataSize);"
|
||||
big_code = rdrCode % "DestReg = DebugSrc1 & mask(dataSize * 8);"
|
||||
|
||||
class Wrdr(RegOp):
|
||||
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
|
||||
|
|
@ -1066,13 +1165,15 @@ let {{
|
|||
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
|
||||
super(Rdcr, self).__init__(dest, \
|
||||
src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
|
||||
code = '''
|
||||
rdcrCode = '''
|
||||
if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) {
|
||||
fault = new InvalidOpcode();
|
||||
} else {
|
||||
DestReg = merge(DestReg, ControlSrc1, dataSize);
|
||||
%s
|
||||
}
|
||||
'''
|
||||
code = rdcrCode % "DestReg = merge(DestReg, ControlSrc1, dataSize);"
|
||||
big_code = rdcrCode % "DestReg = ControlSrc1 & mask(dataSize * 8);"
|
||||
|
||||
class Wrcr(RegOp):
|
||||
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
|
||||
|
|
@ -1154,24 +1255,20 @@ let {{
|
|||
'''
|
||||
|
||||
class Rdbase(SegOp):
|
||||
code = '''
|
||||
DestReg = merge(DestReg, SegBaseSrc1, dataSize);
|
||||
'''
|
||||
code = 'DestReg = merge(DestReg, SegBaseSrc1, dataSize);'
|
||||
big_code = 'DestReg = SegBaseSrc1 & mask(dataSize * 8);'
|
||||
|
||||
class Rdlimit(SegOp):
|
||||
code = '''
|
||||
DestReg = merge(DestReg, SegLimitSrc1, dataSize);
|
||||
'''
|
||||
code = 'DestReg = merge(DestReg, SegLimitSrc1, dataSize);'
|
||||
big_code = 'DestReg = SegLimitSrc1 & mask(dataSize * 8);'
|
||||
|
||||
class RdAttr(SegOp):
|
||||
code = '''
|
||||
DestReg = merge(DestReg, SegAttrSrc1, dataSize);
|
||||
'''
|
||||
code = 'DestReg = merge(DestReg, SegAttrSrc1, dataSize);'
|
||||
big_code = 'DestReg = SegAttrSrc1 & mask(dataSize * 8);'
|
||||
|
||||
class Rdsel(SegOp):
|
||||
code = '''
|
||||
DestReg = merge(DestReg, SegSelSrc1, dataSize);
|
||||
'''
|
||||
code = 'DestReg = merge(DestReg, SegSelSrc1, dataSize);'
|
||||
big_code = 'DestReg = SegSelSrc1 & mask(dataSize * 8);'
|
||||
|
||||
class Rdval(RegOp):
|
||||
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
|
||||
|
|
|
|||
Loading…
Reference in a new issue