2006-10-12 21:04:14 +02:00
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---------- Begin Simulation Statistics ----------
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2010-09-22 08:07:35 +02:00
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host_inst_rate 264030 # Simulator instruction rate (inst/s)
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|
host_mem_usage 193748 # Number of bytes of host memory used
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|
host_seconds 2142.00 # Real time elapsed on the host
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host_tick_rate 77206740 # Simulator tick rate (ticks/s)
|
2006-10-12 21:04:14 +02:00
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|
sim_freq 1000000000000 # Frequency of simulated ticks
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2006-12-05 01:07:00 +01:00
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|
|
sim_insts 565552443 # Number of instructions simulated
|
2010-09-22 08:07:35 +02:00
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sim_seconds 0.165377 # Number of seconds simulated
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|
sim_ticks 165376986500 # Number of ticks simulated
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2009-03-07 23:30:55 +01:00
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|
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2010-09-22 08:07:35 +02:00
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|
system.cpu.BPredUnit.BTBHits 63929788 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 71429024 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 197 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 4120838 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 70454375 # Number of conditional branches predicted
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|
system.cpu.BPredUnit.lookups 76396550 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 1676108 # Number of times the RAS was used to get a target.
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2006-12-05 01:07:00 +01:00
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|
|
system.cpu.commit.COM:branches 62547159 # Number of branches committed
|
2010-09-22 08:07:35 +02:00
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|
system.cpu.commit.COM:bw_lim_events 20033371 # number cycles where commit BW limit reached
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2006-10-12 21:04:14 +02:00
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|
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
2010-09-22 08:07:35 +02:00
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|
|
system.cpu.commit.COM:committed_per_cycle::samples 320816297 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 1.876017 # Number of insts commited each cycle
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|
system.cpu.commit.COM:committed_per_cycle::stdev 2.306184 # Number of insts commited each cycle
|
2009-07-07 00:49:48 +02:00
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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2010-09-22 08:07:35 +02:00
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system.cpu.commit.COM:committed_per_cycle::0 102501444 31.95% 31.95% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1 105613320 32.92% 64.87% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2 36739083 11.45% 76.32% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3 11050019 3.44% 79.77% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4 10174748 3.17% 82.94% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5 21768321 6.79% 89.72% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6 10744082 3.35% 93.07% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7 2191909 0.68% 93.76% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 20033371 6.24% 100.00% # Number of insts commited each cycle
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2009-07-07 00:49:48 +02:00
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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|
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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|
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|
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2010-09-22 08:07:35 +02:00
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|
system.cpu.commit.COM:committed_per_cycle::total 320816297 # Number of insts commited each cycle
|
2006-12-05 01:07:00 +01:00
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system.cpu.commit.COM:count 601856963 # Number of instructions committed
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system.cpu.commit.COM:loads 115049510 # Number of loads committed
|
2006-10-12 21:04:14 +02:00
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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2006-12-05 01:07:00 +01:00
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system.cpu.commit.COM:refs 154862033 # Number of memory references committed
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2006-10-12 21:04:14 +02:00
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|
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
2010-09-22 08:07:35 +02:00
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|
system.cpu.commit.branchMispredicts 4120001 # The number of times a branch was mispredicted
|
2006-12-05 01:07:00 +01:00
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system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
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2006-10-12 21:04:14 +02:00
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system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
|
2010-09-22 08:07:35 +02:00
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system.cpu.commit.commitSquashedInsts 61749735 # The number of squashed insts skipped by commit
|
2006-12-05 01:07:00 +01:00
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system.cpu.committedInsts 565552443 # Number of Instructions Simulated
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system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
|
2010-09-22 08:07:35 +02:00
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system.cpu.cpi 0.584833 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.584833 # CPI: Total CPI of All Threads
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.LoadLockedReq_accesses 4 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_hits 4 # number of LoadLockedReq hits
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2010-09-22 08:07:35 +02:00
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system.cpu.dcache.ReadReq_accesses 115012927 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 14990.355830 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7392.342173 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 114228619 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 11757056000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.006819 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 784308 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 566126 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 1612876000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.001897 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 218182 # number of ReadReq MSHR misses
|
2008-03-18 04:07:22 +01:00
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system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
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2010-09-22 08:07:35 +02:00
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system.cpu.dcache.WriteReq_avg_miss_latency 14906.098057 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11053.696113 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 38301940 # number of WriteReq hits
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|
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system.cpu.dcache.WriteReq_miss_latency 17132785891 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.029134 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 1149381 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 892463 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 2839893498 # number of WriteReq MSHR miss cycles
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|
|
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.006512 # mshr miss rate for WriteReq accesses
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|
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system.cpu.dcache.WriteReq_mshr_misses 256918 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs 6663.699115 # average number of cycles each access was blocked
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|
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system.cpu.dcache.avg_blocked_cycles::no_targets 20363.636364 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 321.049385 # Average number of references to valid blocks.
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2010-09-09 20:40:19 +02:00
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system.cpu.dcache.blocked::no_mshrs 113 # number of cycles access was blocked
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
|
2010-09-22 08:07:35 +02:00
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system.cpu.dcache.blocked_cycles::no_mshrs 752998 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 224000 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2010-09-22 08:07:35 +02:00
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system.cpu.dcache.demand_accesses 154464248 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 14940.273173 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 9372.278463 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 152530559 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 28889841891 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.012519 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 1933689 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 1458589 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 4452769498 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.003076 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 475100 # number of demand (read+write) MSHR misses
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2006-10-12 21:04:14 +02:00
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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2010-09-22 08:07:35 +02:00
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system.cpu.dcache.occ_%::0 0.999558 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 4094.188781 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 154464248 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 14940.273173 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 9372.278463 # average overall mshr miss latency
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2010-09-22 08:07:35 +02:00
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system.cpu.dcache.overall_hits 152530559 # number of overall hits
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system.cpu.dcache.overall_miss_latency 28889841891 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.012519 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 1933689 # number of overall misses
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|
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system.cpu.dcache.overall_mshr_hits 1458589 # number of overall MSHR hits
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|
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system.cpu.dcache.overall_mshr_miss_latency 4452769498 # number of overall MSHR miss cycles
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|
|
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system.cpu.dcache.overall_mshr_miss_rate 0.003076 # mshr miss rate for overall accesses
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|
|
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system.cpu.dcache.overall_mshr_misses 475100 # number of overall MSHR misses
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2006-10-12 21:04:14 +02:00
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|
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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2010-09-22 08:07:35 +02:00
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system.cpu.dcache.replacements 471004 # number of replacements
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system.cpu.dcache.sampled_refs 475100 # Sample count of references to valid blocks.
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2006-10-12 21:04:14 +02:00
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2010-09-22 08:07:35 +02:00
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system.cpu.dcache.tagsinuse 4094.188781 # Cycle average of tags in use
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system.cpu.dcache.total_refs 152530563 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 126404000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 423151 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 48113828 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 871 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 4177876 # Number of times decode resolved a branch
|
|
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system.cpu.decode.DECODE:DecodedInsts 689990711 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 144277716 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 122985866 # Number of cycles decode is running
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|
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system.cpu.decode.DECODE:SquashCycles 9844039 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 3043 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 5438887 # Number of cycles decode is unblocking
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system.cpu.dtb.data_accesses 163094811 # DTB accesses
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2009-04-09 07:21:30 +02:00
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system.cpu.dtb.data_acv 0 # DTB access violations
|
2010-09-22 08:07:35 +02:00
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system.cpu.dtb.data_hits 163045966 # DTB hits
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system.cpu.dtb.data_misses 48845 # DTB misses
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2009-04-09 07:21:30 +02:00
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
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system.cpu.dtb.fetch_hits 0 # ITB hits
|
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|
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
2010-09-22 08:07:35 +02:00
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|
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system.cpu.dtb.read_accesses 122278185 # DTB read accesses
|
2007-08-27 05:27:53 +02:00
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|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.dtb.read_hits 122255138 # DTB read hits
|
|
|
|
|
system.cpu.dtb.read_misses 23047 # DTB read misses
|
|
|
|
|
system.cpu.dtb.write_accesses 40816626 # DTB write accesses
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.dtb.write_hits 40790828 # DTB write hits
|
|
|
|
|
system.cpu.dtb.write_misses 25798 # DTB write misses
|
|
|
|
|
system.cpu.fetch.Branches 76396550 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.CacheLines 65649275 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.Cycles 195872330 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 1325100 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.Insts 699185184 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.SquashCycles 4170349 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.branchRate 0.230977 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.icacheStallCycles 65649275 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.predictedBranches 65605896 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.rate 2.113913 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu.fetch.rateDist::samples 330660336 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::mean 2.114512 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::stdev 3.085107 # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.fetch.rateDist::0 200437318 60.62% 60.62% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::1 10372140 3.14% 63.75% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::2 15863919 4.80% 68.55% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::3 13948828 4.22% 72.77% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::4 12077397 3.65% 76.42% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::5 13850642 4.19% 80.61% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::6 5888624 1.78% 82.39% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::7 3427564 1.04% 83.43% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::8 54793904 16.57% 100.00% # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.fetch.rateDist::total 330660336 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 65649275 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 36269.949066 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35524.725275 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_hits 65648097 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 42726000 # number of ReadReq miss cycles
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.icache.ReadReq_misses 1178 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 268 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 32327500 # number of ReadReq MSHR miss cycles
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses 910 # number of ReadReq MSHR misses
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.icache.avg_refs 72140.765934 # Average number of references to valid blocks.
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.icache.demand_accesses 65649275 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 36269.949066 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 35524.725275 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 65648097 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 42726000 # number of demand (read+write) miss cycles
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.icache.demand_misses 1178 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 268 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 32327500 # number of demand (read+write) MSHR miss cycles
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.icache.demand_mshr_misses 910 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.icache.occ_%::0 0.378879 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_blocks::0 775.944948 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.overall_accesses 65649275 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 36269.949066 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 35524.725275 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.icache.overall_hits 65648097 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 42726000 # number of overall miss cycles
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.icache.overall_misses 1178 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 268 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 32327500 # number of overall MSHR miss cycles
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.icache.overall_mshr_misses 910 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.icache.replacements 32 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 910 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.icache.tagsinuse 775.944948 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 65648097 # Total number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.idleCycles 93638 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 67433622 # Number of branches executed
|
|
|
|
|
system.cpu.iew.EXEC:nop 43234709 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.EXEC:rate 1.811577 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 164032675 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:stores 41211382 # Number of stores executed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iew.WB:consumers 492720055 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 595983189 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.807592 # average fanout of values written-back
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iew.WB:producers 397916939 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 1.801893 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 597091543 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 4603878 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewBlockCycles 1505457 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 126939472 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 3143406 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 43126164 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 663744184 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 122821293 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 6299898 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 599186314 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 2121 # Number of times the IQ has become full, causing a stall
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 28444 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewSquashCycles 9844039 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 43665 # Number of cycles IEW is unblocking
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 720 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 7235686 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 12544 # Number of memory responses ignored because the instruction is squashed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 71476 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 5929 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 11889962 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 3313641 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 71476 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 943110 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 3660768 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.ipc 1.709889 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.709889 # IPC: Total IPC of All Threads
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntAlu 438748901 72.46% 72.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntMult 6682 0.00% 72.46% # Type of FU issued
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 72.46% # Type of FU issued
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 29 0.00% 72.46% # Type of FU issued
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 5 0.00% 72.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% 72.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 72.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.46% # Type of FU issued
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemRead 124774485 20.61% 93.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemWrite 41956101 6.93% 100.00% # Type of FU issued
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::total 605486212 # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 7206090 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.011901 # FU busy rate (busy events/executed inst)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::IntAlu 5226098 72.52% 72.52% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntMult 48 0.00% 72.52% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 72.52% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 72.52% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 72.52% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 72.52% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 72.52% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 72.52% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 72.52% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemRead 1579159 21.91% 94.44% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemWrite 400785 5.56% 100.00% # attempts to use FU when none available
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 330660336 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.831143 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.672265 # Number of insts issued each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0 90539952 27.38% 27.38% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1 66701453 20.17% 47.55% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2 79600053 24.07% 71.63% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3 36541170 11.05% 82.68% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4 31317153 9.47% 92.15% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5 13281184 4.02% 96.17% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6 11041150 3.34% 99.50% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7 1066057 0.32% 99.83% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 572164 0.17% 100.00% # Number of insts issued each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 330660336 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:rate 1.830624 # Inst issue rate
|
|
|
|
|
system.cpu.iq.iqInstsAdded 620509446 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 605486212 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 53535562 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 17232 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 29599324 # Number of squashed operands that are examined and possibly removed from graph
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.itb.fetch_accesses 65649312 # ITB accesses
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.itb.fetch_hits 65649275 # ITB hits
|
|
|
|
|
system.cpu.itb.fetch_misses 37 # ITB misses
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 256918 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34522.310610 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31406.220232 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 197081 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 2065711500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.232903 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 59837 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1879254000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.232903 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 59837 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 219092 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34389.734476 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31018.456070 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 186176 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 1131972500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.150238 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 32916 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1021003500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.150238 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 32916 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 423151 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 423151 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5261.194030 # average number of cycles each access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.avg_refs 5.283534 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.blocked::no_mshrs 67 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 352500 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 476010 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34475.262256 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31268.611258 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_hits 383257 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 3197684000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.194855 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 92753 # number of demand (read+write) misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 2900257500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.194855 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 92753 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.occ_%::0 0.052815 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_%::1 0.488399 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_blocks::0 1730.637326 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 16003.856484 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.overall_accesses 476010 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34475.262256 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31268.611258 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.overall_hits 383257 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 3197684000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.194855 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 92753 # number of overall misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 2900257500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.194855 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 92753 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.replacements 74446 # number of replacements
|
|
|
|
|
system.cpu.l2cache.sampled_refs 90349 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 17734.493810 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 477362 # Total number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.writebacks 59324 # number of writebacks
|
|
|
|
|
system.cpu.memDep0.conflictingLoads 22261692 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 15435128 # Number of conflicting stores.
|
|
|
|
|
system.cpu.memDep0.insertedLoads 126939472 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 43126164 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.numCycles 330753974 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.rename.RENAME:BlockCycles 12738848 # Number of cycles rename is blocking
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.rename.RENAME:IQFullEvents 34708853 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.RENAME:IdleCycles 151708807 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 618719 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RENAME:ROBFullEvents 82 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu.rename.RENAME:RenameLookups 896183749 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 680208714 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 518824645 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 115765657 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 9844039 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 40602289 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 54969756 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 696 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RENAME:serializingInsts 32 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.RENAME:skidInsts 79641546 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 31 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.timesIdled 3516 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
