gem5/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt

---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits                     65739146                       # Number of BTB hits
global.BPredUnit.BTBLookups                  73253175                       # Number of BTB lookups
global.BPredUnit.RASInCorrect                     177                       # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect                4205990                       # Number of conditional branches incorrect
global.BPredUnit.condPredicted               70175548                       # Number of conditional branches predicted
global.BPredUnit.lookups                     76112488                       # Number of BP lookups
global.BPredUnit.usedRAS                      1692573                       # Number of times the RAS was used to get a target.
host_inst_rate                                 185893                       # Simulator instruction rate (inst/s)
host_mem_usage                                 223968                       # Number of bytes of host memory used
host_seconds                                  3042.35                       # Real time elapsed on the host
host_tick_rate                               54375513                       # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads           21896719                       # Number of conflicting loads.
memdepunit.memDep.conflictingStores          16284345                       # Number of conflicting stores.
memdepunit.memDep.insertedLoads             127086189                       # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores             43192001                       # Number of stores inserted to the mem dependence unit.
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                   565552443                       # Number of instructions simulated
sim_seconds                                  0.165429                       # Number of seconds simulated
sim_ticks                                165429421500                       # Number of ticks simulated
system.cpu.commit.COM:branches               62547159                       # Number of branches committed
system.cpu.commit.COM:bw_lim_events          20148945                       # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples    320950455                      
system.cpu.commit.COM:committed_per_cycle.min_value            0                      
                               0    102049912   3179.62%           
                               1    106118520   3306.38%           
                               2     36548740   1138.77%           
                               3     11550344    359.88%           
                               4      9951958    310.08%           
                               5     22152324    690.21%           
                               6     10779065    335.85%           
                               7      1650647     51.43%           
                               8     20148945    627.79%           
system.cpu.commit.COM:committed_per_cycle.max_value            8                      
system.cpu.commit.COM:committed_per_cycle.end_dist

system.cpu.commit.COM:count                 601856963                       # Number of instructions committed
system.cpu.commit.COM:loads                 115049510                       # Number of loads committed
system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
system.cpu.commit.COM:refs                  154862033                       # Number of memory references committed
system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts           4205367                       # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts      601856963                       # The number of committed instructions
system.cpu.commit.commitNonSpecStalls              17                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts        61707712                       # The number of squashed insts skipped by commit
system.cpu.committedInsts                   565552443                       # Number of Instructions Simulated
system.cpu.committedInsts_total             565552443                       # Number of Instructions Simulated
system.cpu.cpi                               0.585019                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.585019                       # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses            1                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits                1                       # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses          114321557                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 26993.890628                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency  3367.177206                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits              114105250                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency     5838967500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.001892                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses               216307                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits            716795                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency    728344000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.001892                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses          216307                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses          37579282                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 48790.597140                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency  7159.473367                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits              37241994                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency   16456482928                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.008975                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses              337288                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits          1872039                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency   2414804453                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.008975                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses         337288                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs  1999.750000                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets         2750                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                 320.196392                       # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs                  4                       # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets                4                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs         7999                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets        11000                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses           151900839                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 40273.937496                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency  5677.703832                       # average overall mshr miss latency
system.cpu.dcache.demand_hits               151347244                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency     22295450428                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.003644                       # miss rate for demand accesses
system.cpu.dcache.demand_misses                553595                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits            2588834                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency   3143148453                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.003644                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses           553595                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses          151900839                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 40273.937496                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency  5677.703832                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits              151347244                       # number of overall hits
system.cpu.dcache.overall_miss_latency    22295450428                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.003644                       # miss rate for overall accesses
system.cpu.dcache.overall_misses               553595                       # number of overall misses
system.cpu.dcache.overall_mshr_hits           2588834                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency   3143148453                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.003644                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses          553595                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements                 468826                       # number of replacements
system.cpu.dcache.sampled_refs                 472922                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse               4095.170465                       # Cycle average of tags in use
system.cpu.dcache.total_refs                151427918                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle               50285000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                   334126                       # number of writebacks
system.cpu.decode.DECODE:BlockedCycles       46422286                       # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred            645                       # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved       4161088                       # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts       690019158                       # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles         145191324                       # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles          123829448                       # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles         9907520                       # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts           1984                       # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles        5507398                       # Number of cycles decode is unblocking
system.cpu.dtb.accesses                     163087430                       # DTB accesses
system.cpu.dtb.acv                                  0                       # DTB access violations
system.cpu.dtb.hits                         163038163                       # DTB hits
system.cpu.dtb.misses                           49267                       # DTB misses
system.cpu.dtb.read_accesses                122338189                       # DTB read accesses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_hits                    122317544                       # DTB read hits
system.cpu.dtb.read_misses                      20645                       # DTB read misses
system.cpu.dtb.write_accesses                40749241                       # DTB write accesses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_hits                    40720619                       # DTB write hits
system.cpu.dtb.write_misses                     28622                       # DTB write misses
system.cpu.fetch.Branches                    76112488                       # Number of branches that fetch encountered
system.cpu.fetch.CacheLines                  66025670                       # Number of cache lines fetched
system.cpu.fetch.Cycles                     197184214                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes               1351502                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts                      699221634                       # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles                 4235220                       # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate                  0.230045                       # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles           66025670                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches           67431719                       # Number of branches that fetch has predicted taken
system.cpu.fetch.rate                        2.113353                       # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist                           # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples           330857976                      
system.cpu.fetch.rateDist.min_value                 0                      
                               0    199699470   6035.81%           
                               1     10371896    313.48%           
                               2     15863038    479.45%           
                               3     14602598    441.36%           
                               4     12358229    373.52%           
                               5     14818818    447.89%           
                               6      6010699    181.67%           
                               7      3341156    100.98%           
                               8     53792072   1625.84%           
system.cpu.fetch.rateDist.max_value                 8                      
system.cpu.fetch.rateDist.end_dist

system.cpu.icache.ReadReq_accesses           66025546                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 10641.352550                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency  6819.290466                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits               66024644                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency        9598500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.000014                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                  902                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits               124                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency      6151000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.000014                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses             902                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs               73198.053215                       # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses            66025546                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 10641.352550                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency  6819.290466                       # average overall mshr miss latency
system.cpu.icache.demand_hits                66024644                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency         9598500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.000014                       # miss rate for demand accesses
system.cpu.icache.demand_misses                   902                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                124                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency      6151000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.000014                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses              902                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.overall_accesses           66025546                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 10641.352550                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency  6819.290466                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits               66024644                       # number of overall hits
system.cpu.icache.overall_miss_latency        9598500                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.000014                       # miss rate for overall accesses
system.cpu.icache.overall_misses                  902                       # number of overall misses
system.cpu.icache.overall_mshr_hits               124                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency      6151000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.000014                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses             902                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements                     32                       # number of replacements
system.cpu.icache.sampled_refs                    902                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse                769.239178                       # Cycle average of tags in use
system.cpu.icache.total_refs                 66024644                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.idleCycles                             868                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches                 67336673                       # Number of branches executed
system.cpu.iew.EXEC:nop                      43018581                       # number of nop insts executed
system.cpu.iew.EXEC:rate                     1.810881                       # Inst execution rate
system.cpu.iew.EXEC:refs                    164027135                       # number of memory reference insts executed
system.cpu.iew.EXEC:stores                   41145337                       # Number of stores executed
system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
system.cpu.iew.WB:consumers                 491694974                       # num instructions consuming a value
system.cpu.iew.WB:count                     595952322                       # cumulative count of insts written-back
system.cpu.iew.WB:fanout                     0.808476                       # average fanout of values written-back
system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers                 397523802                       # num instructions producing a value
system.cpu.iew.WB:rate                       1.801228                       # insts written-back per cycle
system.cpu.iew.WB:sent                      597113280                       # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts              4671395                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles                   85472                       # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts             127086189                       # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts                 22                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts           3259094                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts             43192001                       # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts           663707703                       # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts             122881798                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           6536173                       # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts             599145915                       # Number of executed instructions
system.cpu.iew.iewIQFullEvents                   1317                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents                    10                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles                9907520                       # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles                  4668                       # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked         4162                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads         7269203                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses        14266                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation        32461                       # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads         5902                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads     12036679                       # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores      3379478                       # Number of stores squashed
system.cpu.iew.memOrderViolationEvents          32461                       # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect       540781                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect        4130614                       # Number of branches that were predicted taken incorrectly
system.cpu.ipc                               1.709347                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.709347                       # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0               605682088                       # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
                      No_OpClass            0      0.00%            # Type of FU issued
                          IntAlu    438760030     72.44%            # Type of FU issued
                         IntMult         6517      0.00%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd           29      0.00%            # Type of FU issued
                        FloatCmp            5      0.00%            # Type of FU issued
                        FloatCvt            5      0.00%            # Type of FU issued
                       FloatMult            4      0.00%            # Type of FU issued
                        FloatDiv            0      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead    124950238     20.63%            # Type of FU issued
                        MemWrite     41965260      6.93%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt               6912738                       # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate             0.011413                       # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
                      No_OpClass            0      0.00%            # attempts to use FU when none available
                          IntAlu      5342591     77.29%            # attempts to use FU when none available
                         IntMult           72      0.00%            # attempts to use FU when none available
                          IntDiv            0      0.00%            # attempts to use FU when none available
                        FloatAdd            0      0.00%            # attempts to use FU when none available
                        FloatCmp            0      0.00%            # attempts to use FU when none available
                        FloatCvt            0      0.00%            # attempts to use FU when none available
                       FloatMult            0      0.00%            # attempts to use FU when none available
                        FloatDiv            0      0.00%            # attempts to use FU when none available
                       FloatSqrt            0      0.00%            # attempts to use FU when none available
                         MemRead       924602     13.38%            # attempts to use FU when none available
                        MemWrite       645473      9.34%            # attempts to use FU when none available
                       IprAccess            0      0.00%            # attempts to use FU when none available
                    InstPrefetch            0      0.00%            # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples    330857976                      
system.cpu.iq.ISSUE:issued_per_cycle.min_value            0                      
                               0     90630363   2739.25%           
                               1     66723730   2016.69%           
                               2     79382589   2399.30%           
                               3     36274593   1096.38%           
                               4     32477730    981.62%           
                               5     12845074    388.24%           
                               6     10946309    330.85%           
                               7      1065447     32.20%           
                               8       512141     15.48%           
system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
system.cpu.iq.ISSUE:issued_per_cycle.end_dist

system.cpu.iq.ISSUE:rate                     1.830636                       # Inst issue rate
system.cpu.iq.iqInstsAdded                  620689100                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued                 605682088                       # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded                  22                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined        53858401                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued             17774                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved              5                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined     29864580                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses                      66025708                       # ITB accesses
system.cpu.itb.acv                                  0                       # ITB acv
system.cpu.itb.hits                          66025670                       # ITB hits
system.cpu.itb.misses                              38                       # ITB misses
system.cpu.l2cache.ReadExReq_accesses          256615                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency  5221.239990                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency  2221.239990                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency   1339848500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses            256615                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency    570003500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses       256615                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses            217209                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency  5324.201615                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  2324.201615                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits                181418                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency     190558500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate         0.164777                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses               35791                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency     83185500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.164777                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses          35791                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses          80676                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency  5165.743220                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency  2166.071694                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency    416751500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses            80676                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency    174750000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses        80676                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses          334126                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits              334126                       # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                  3.724082                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses             473824                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency  5233.842671                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency  2233.842671                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                 181418                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency     1530407000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate          0.617119                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses               292406                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency    653189000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate     0.617119                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses          292406                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses            473824                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency  5233.842671                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency  2233.842671                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits                181418                       # number of overall hits
system.cpu.l2cache.overall_miss_latency    1530407000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate         0.617119                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses              292406                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency    653189000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate     0.617119                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses         292406                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements                 85250                       # number of replacements
system.cpu.l2cache.sampled_refs                100885                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse             16355.319881                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                  375704                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                   63237                       # number of writebacks
system.cpu.numCycles                        330858844                       # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles         11109833                       # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps      463854889                       # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents        34908767                       # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles         152607206                       # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents         316634                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups      896955924                       # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts       680550426                       # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands    519573186                       # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles          116670528                       # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles         9907520                       # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles       40562533                       # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps          55718297                       # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles          356                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts           27                       # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts           79715664                       # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts           25                       # count of temporary serializing insts renamed
system.cpu.timesIdled                             189                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls

---------- End Simulation Statistics   ----------