2006-10-12 21:04:14 +02:00
|
|
|
|
|
|
|
|
---------- Begin Simulation Statistics ----------
|
|
|
|
|
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2007-04-16 04:29:37 +02:00
|
|
|
global.BPredUnit.BTBHits 71631614 # Number of BTB hits
|
|
|
|
|
global.BPredUnit.BTBLookups 80215513 # Number of BTB lookups
|
|
|
|
|
global.BPredUnit.RASInCorrect 194 # Number of incorrect RAS predictions.
|
|
|
|
|
global.BPredUnit.condIncorrect 4366377 # Number of conditional branches incorrect
|
|
|
|
|
global.BPredUnit.condPredicted 76991765 # Number of conditional branches predicted
|
|
|
|
|
global.BPredUnit.lookups 83232960 # Number of BP lookups
|
|
|
|
|
global.BPredUnit.usedRAS 1776050 # Number of times the RAS was used to get a target.
|
|
|
|
|
host_inst_rate 91613 # Simulator instruction rate (inst/s)
|
|
|
|
|
host_mem_usage 151676 # Number of bytes of host memory used
|
|
|
|
|
host_seconds 6173.25 # Real time elapsed on the host
|
|
|
|
|
host_tick_rate 271486 # Simulator tick rate (ticks/s)
|
|
|
|
|
memdepunit.memDep.conflictingLoads 26015543 # Number of conflicting loads.
|
|
|
|
|
memdepunit.memDep.conflictingStores 23632204 # Number of conflicting stores.
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|
|
|
|
memdepunit.memDep.insertedLoads 134244919 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
memdepunit.memDep.insertedStores 44983310 # Number of stores inserted to the mem dependence unit.
|
2006-10-12 21:04:14 +02:00
|
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
2006-12-05 01:07:00 +01:00
|
|
|
sim_insts 565552443 # Number of instructions simulated
|
2007-04-16 04:29:37 +02:00
|
|
|
sim_seconds 0.001676 # Number of seconds simulated
|
|
|
|
|
sim_ticks 1675949017 # Number of ticks simulated
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.commit.COM:branches 62547159 # Number of branches committed
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.commit.COM:bw_lim_events 16353031 # number cycles where commit BW limit reached
|
2006-10-12 21:04:14 +02:00
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|
|
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.samples 801372491
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
2007-04-16 04:29:37 +02:00
|
|
|
0 580782547 7247.35%
|
|
|
|
|
1 101892793 1271.48%
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|
|
|
|
2 41339172 515.85%
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|
|
|
|
3 11939444 148.99%
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|
|
|
|
4 15719123 196.15%
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|
|
|
|
5 17754998 221.56%
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|
|
|
|
6 10147917 126.63%
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|
|
|
|
7 5443466 67.93%
|
|
|
|
|
8 16353031 204.06%
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.max_value 8
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|
|
|
|
system.cpu.commit.COM:committed_per_cycle.end_dist
|
|
|
|
|
|
2006-12-05 01:07:00 +01:00
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|
|
system.cpu.commit.COM:count 601856963 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.COM:loads 115049510 # Number of loads committed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.commit.COM:refs 154862033 # Number of memory references committed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.commit.branchMispredicts 4365734 # The number of times a branch was mispredicted
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 90079827 # The number of squashed insts skipped by commit
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.committedInsts 565552443 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.cpi 2.963384 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 2.963384 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 120253770 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 3927.286441 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3434.366579 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 119156440 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 4309529230 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.009125 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 1097330 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 872988 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 770472667 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001866 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 224342 # number of ReadReq MSHR misses
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 9089.303046 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9344.661839 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 37503702 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 17702499310 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.049368 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 1947619 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 1690762 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 2400241806 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006511 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 256857 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_mshrs 327.941025 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_targets 3498.764706 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_refs 325.562069 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.blocked_no_mshrs 3493 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_no_targets 17 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles_no_mshrs 1145498 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles_no_targets 59479 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.dcache.demand_accesses 159705091 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 7229.030286 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 6589.195890 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_hits 156660142 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 22012028540 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.019066 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_misses 3044949 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 2563750 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 3170714473 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.003013 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 481199 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.dcache.overall_accesses 159705091 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 7229.030286 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 6589.195890 # average overall mshr miss latency
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.dcache.overall_hits 156660142 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 22012028540 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.019066 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_misses 3044949 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 2563750 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 3170714473 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.003013 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 481199 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.dcache.replacements 477103 # number of replacements
|
|
|
|
|
system.cpu.dcache.sampled_refs 481199 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.dcache.tagsinuse 4063.174314 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 156660142 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 20910000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.writebacks 338217 # number of writebacks
|
|
|
|
|
system.cpu.decode.DECODE:BlockedCycles 515310439 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.DECODE:BranchMispred 681 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu.decode.DECODE:BranchResolved 4340917 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu.decode.DECODE:DecodedInsts 740208637 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.DECODE:IdleCycles 161139948 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.DECODE:RunCycles 116871564 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.DECODE:SquashCycles 14453620 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.DECODE:SquashedInsts 2001 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu.decode.DECODE:UnblockCycles 8050541 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.fetch.Branches 83232960 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.CacheLines 72135284 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.Cycles 198811102 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 1485258 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.Insts 751818937 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.SquashCycles 5990379 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.branchRate 0.102023 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.icacheStallCycles 72135284 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.predictedBranches 73407664 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.rate 0.921543 # Number of inst fetches per cycle
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.fetch.rateDist.samples 815826112
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.fetch.rateDist.min_value 0
|
2007-04-16 04:29:37 +02:00
|
|
|
0 689150299 8447.27%
|
|
|
|
|
1 10579353 129.68%
|
|
|
|
|
2 12110332 148.44%
|
|
|
|
|
3 11560507 141.70%
|
|
|
|
|
4 9007686 110.41%
|
|
|
|
|
5 3425511 41.99%
|
|
|
|
|
6 3768928 46.20%
|
|
|
|
|
7 3222436 39.50%
|
|
|
|
|
8 73001060 894.81%
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.fetch.rateDist.max_value 8
|
|
|
|
|
system.cpu.fetch.rateDist.end_dist
|
|
|
|
|
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.icache.ReadReq_accesses 72135284 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 5699.600162 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4917.297556 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_hits 72134046 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 7056105 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000017 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses 1238 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 297 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 4627177 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000013 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 941 # number of ReadReq MSHR misses
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles_no_targets 3783 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_refs 76656.797024 # Average number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.icache.blocked_no_targets 1 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.icache.blocked_cycles_no_targets 3783 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.icache.demand_accesses 72135284 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 5699.600162 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 4917.297556 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 72134046 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 7056105 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000017 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 1238 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 297 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 4627177 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000013 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 941 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.icache.overall_accesses 72135284 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 5699.600162 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 4917.297556 # average overall mshr miss latency
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.icache.overall_hits 72134046 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 7056105 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000017 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 1238 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 297 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 4627177 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000013 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 941 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.icache.replacements 44 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 941 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.icache.tagsinuse 749.515669 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 72134046 # Total number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.idleCycles 860122906 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 67691806 # Number of branches executed
|
|
|
|
|
system.cpu.iew.EXEC:nop 43795429 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.EXEC:rate 0.748142 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 168635664 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:stores 41396142 # Number of stores executed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.iew.WB:consumers 508232399 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 603225060 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.792920 # average fanout of values written-back
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.iew.WB:producers 402987686 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 0.739404 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 604785539 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 4695315 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewBlockCycles 442855270 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 134244919 # Number of dispatched load instructions
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.iew.iewDispSquashedInsts 5961708 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 44983310 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 691933738 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 127239522 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 6754480 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 610353566 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 42801 # Number of times the IQ has become full, causing a stall
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 120734 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewSquashCycles 14453620 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 431168 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 1871526 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 4575118 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 24838 # Number of memory responses ignored because the instruction is squashed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 1001889 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 5578 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 19195409 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 5170787 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 1001889 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 542024 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 4153291 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.ipc 0.337452 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.337452 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0 617108046 # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
2006-12-05 01:07:00 +01:00
|
|
|
(null) 0 0.00% # Type of FU issued
|
2007-04-16 04:29:37 +02:00
|
|
|
IntAlu 445691749 72.22% # Type of FU issued
|
|
|
|
|
IntMult 6563 0.00% # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
IntDiv 0 0.00% # Type of FU issued
|
2006-12-05 01:07:00 +01:00
|
|
|
FloatAdd 33 0.00% # Type of FU issued
|
|
|
|
|
FloatCmp 6 0.00% # Type of FU issued
|
|
|
|
|
FloatCvt 5 0.00% # Type of FU issued
|
|
|
|
|
FloatMult 5 0.00% # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
|
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
2007-04-16 04:29:37 +02:00
|
|
|
MemRead 129192933 20.94% # Type of FU issued
|
|
|
|
|
MemWrite 42216752 6.84% # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
|
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 3402065 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.005513 # FU busy rate (busy events/executed inst)
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
|
|
|
(null) 0 0.00% # attempts to use FU when none available
|
2007-04-16 04:29:37 +02:00
|
|
|
IntAlu 2626203 77.19% # attempts to use FU when none available
|
2006-10-12 21:04:14 +02:00
|
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
2007-04-16 04:29:37 +02:00
|
|
|
MemRead 644339 18.94% # attempts to use FU when none available
|
|
|
|
|
MemWrite 131523 3.87% # attempts to use FU when none available
|
2006-10-12 21:04:14 +02:00
|
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
|
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 815826112
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
2007-04-16 04:29:37 +02:00
|
|
|
0 553114491 6779.81%
|
|
|
|
|
1 85371128 1046.44%
|
|
|
|
|
2 77782451 953.42%
|
|
|
|
|
3 52154516 639.28%
|
|
|
|
|
4 28098332 344.42%
|
|
|
|
|
5 10103046 123.84%
|
|
|
|
|
6 7930576 97.21%
|
|
|
|
|
7 956122 11.72%
|
|
|
|
|
8 315450 3.87%
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
|
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.iq.ISSUE:rate 0.756421 # Inst issue rate
|
|
|
|
|
system.cpu.iq.iqInstsAdded 648138284 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 617108046 # Number of instructions issued
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.iq.iqSquashedInstsExamined 80438129 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 1088392 # Number of squashed instructions issued
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 57507029 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 482140 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 8078.944187 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2363.998861 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 455802 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 212783232 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.054627 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 26338 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 62263002 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054627 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 26338 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 338217 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 338217 # number of Writeback hits
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.l2cache.avg_refs 30.147278 # Average number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 482140 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 8078.944187 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 2363.998861 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_hits 455802 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 212783232 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.054627 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 26338 # number of demand (read+write) misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 62263002 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.054627 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 26338 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.l2cache.overall_accesses 820357 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 8078.944187 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 2363.998861 # average overall mshr miss latency
|
2007-02-14 19:05:20 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.l2cache.overall_hits 794019 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 212783232 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.032106 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 26338 # number of overall misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 62263002 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.032106 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 26338 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.l2cache.replacements 935 # number of replacements
|
|
|
|
|
system.cpu.l2cache.sampled_refs 26338 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 24391.955858 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 794019 # Total number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.l2cache.writebacks 908 # number of writebacks
|
|
|
|
|
system.cpu.numCycles 815826112 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.rename.RENAME:BlockCycles 467231804 # Number of cycles rename is blocking
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.rename.RENAME:IQFullEvents 38638370 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.RENAME:IdleCycles 170863189 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 8553533 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RENAME:ROBFullEvents 36121 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu.rename.RENAME:RenameLookups 961623776 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 729244091 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 554812455 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 115192044 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 14453620 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 48042805 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 90957566 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 42650 # count of cycles rename stalled for serializing inst
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.rename.RENAME:serializingInsts 30 # count of serializing insts renamed
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.rename.RENAME:skidInsts 77555696 # count of insts added to the skid buffer
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 28 # count of temporary serializing insts renamed
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.timesIdled 308219 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
