2006-10-12 21:04:14 +02:00
|
|
|
|
|
|
|
|
---------- Begin Simulation Statistics ----------
|
|
|
|
|
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2007-04-27 20:35:58 +02:00
|
|
|
global.BPredUnit.BTBHits 74294088 # Number of BTB hits
|
|
|
|
|
global.BPredUnit.BTBLookups 83217138 # Number of BTB lookups
|
|
|
|
|
global.BPredUnit.RASInCorrect 175 # Number of incorrect RAS predictions.
|
|
|
|
|
global.BPredUnit.condIncorrect 4320797 # Number of conditional branches incorrect
|
|
|
|
|
global.BPredUnit.condPredicted 79655810 # Number of conditional branches predicted
|
|
|
|
|
global.BPredUnit.lookups 86600861 # Number of BP lookups
|
|
|
|
|
global.BPredUnit.usedRAS 1992384 # Number of times the RAS was used to get a target.
|
|
|
|
|
host_inst_rate 121760 # Simulator instruction rate (inst/s)
|
|
|
|
|
host_mem_usage 154560 # Number of bytes of host memory used
|
|
|
|
|
host_seconds 4644.82 # Real time elapsed on the host
|
|
|
|
|
host_tick_rate 28265671 # Simulator tick rate (ticks/s)
|
|
|
|
|
memdepunit.memDep.conflictingLoads 20253948 # Number of conflicting loads.
|
|
|
|
|
memdepunit.memDep.conflictingStores 12668807 # Number of conflicting stores.
|
|
|
|
|
memdepunit.memDep.insertedLoads 134508955 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
memdepunit.memDep.insertedStores 44216516 # Number of stores inserted to the mem dependence unit.
|
2006-10-12 21:04:14 +02:00
|
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
2006-12-05 01:07:00 +01:00
|
|
|
sim_insts 565552443 # Number of instructions simulated
|
2007-04-27 20:35:58 +02:00
|
|
|
sim_seconds 0.131289 # Number of seconds simulated
|
|
|
|
|
sim_ticks 131288904500 # Number of ticks simulated
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.commit.COM:branches 62547159 # Number of branches committed
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.commit.COM:bw_lim_events 25836005 # number cycles where commit BW limit reached
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.samples 248547939
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
2007-04-27 20:35:58 +02:00
|
|
|
0 64112537 2579.48%
|
|
|
|
|
1 73997996 2977.21%
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|
|
|
|
2 29649485 1192.91%
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|
|
|
|
3 7413919 298.29%
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|
|
|
|
4 16299890 655.80%
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|
|
|
|
5 20436719 822.24%
|
|
|
|
|
6 3362671 135.29%
|
|
|
|
|
7 7438717 299.29%
|
|
|
|
|
8 25836005 1039.48%
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle.end_dist
|
|
|
|
|
|
2006-12-05 01:07:00 +01:00
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|
|
system.cpu.commit.COM:count 601856963 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.COM:loads 115049510 # Number of loads committed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.commit.COM:refs 154862033 # Number of memory references committed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.commit.branchMispredicts 4320164 # The number of times a branch was mispredicted
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 94497449 # The number of squashed insts skipped by commit
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.committedInsts 565552443 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.cpi 0.464286 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.464286 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 115538611 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 2723.249468 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2089.628248 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 114910502 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 1710497500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.005436 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 628109 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 403470 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 469412000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001944 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 224639 # number of ReadReq MSHR misses
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 3076.718619 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2314.396461 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 38683248 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 2363144500 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.019469 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 768073 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 511246 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 594399500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006510 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 256827 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_mshrs 539.249147 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_targets 250 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_refs 319.012661 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.blocked_no_mshrs 1172 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_no_targets 4 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles_no_mshrs 632000 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles_no_targets 1000 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.dcache.demand_accesses 154989932 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 2917.701274 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 2209.525699 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_hits 153593750 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 4073642000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.009008 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_misses 1396182 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 914716 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 1063811500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.003106 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 481466 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.dcache.overall_accesses 154989932 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 2917.701274 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 2209.525699 # average overall mshr miss latency
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.dcache.overall_hits 153593750 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 4073642000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.009008 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_misses 1396182 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 914716 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 1063811500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.003106 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 481466 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.dcache.replacements 477370 # number of replacements
|
|
|
|
|
system.cpu.dcache.sampled_refs 481466 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.dcache.tagsinuse 4095.510322 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 153593750 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 24474000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.writebacks 338333 # number of writebacks
|
|
|
|
|
system.cpu.decode.DECODE:BlockedCycles 34835558 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.DECODE:BranchMispred 676 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu.decode.DECODE:BranchResolved 4837262 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu.decode.DECODE:DecodedInsts 747469994 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.DECODE:IdleCycles 87926948 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.DECODE:RunCycles 115162373 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.DECODE:SquashCycles 14029871 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.DECODE:SquashedInsts 2002 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu.decode.DECODE:UnblockCycles 10623061 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.fetch.Branches 86600861 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.CacheLines 72219408 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.Cycles 200341434 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 435 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.Insts 760297798 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.SquashCycles 4883794 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.branchRate 0.329810 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.icacheStallCycles 72219408 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.predictedBranches 76286472 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.rate 2.895514 # Number of inst fetches per cycle
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.fetch.rateDist.samples 262577811
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.fetch.rateDist.min_value 0
|
2007-04-27 20:35:58 +02:00
|
|
|
0 134455787 5120.61%
|
|
|
|
|
1 11289278 429.94%
|
|
|
|
|
2 12199345 464.60%
|
|
|
|
|
3 11605085 441.97%
|
|
|
|
|
4 7894720 300.66%
|
|
|
|
|
5 3823699 145.62%
|
|
|
|
|
6 3913283 149.03%
|
|
|
|
|
7 3555410 135.40%
|
|
|
|
|
8 73841204 2812.16%
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.fetch.rateDist.max_value 8
|
|
|
|
|
system.cpu.fetch.rateDist.end_dist
|
|
|
|
|
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.icache.ReadReq_accesses 72219408 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 4241.833509 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3311.810155 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_hits 72218459 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 4025500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses 949 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 3000500 # number of ReadReq MSHR miss cycles
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000013 # mshr miss rate for ReadReq accesses
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses 906 # number of ReadReq MSHR misses
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_refs 79711.323400 # Average number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.icache.demand_accesses 72219408 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 4241.833509 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 3311.810155 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 72218459 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 4025500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 949 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 43 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 3000500 # number of demand (read+write) MSHR miss cycles
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000013 # mshr miss rate for demand accesses
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.icache.demand_mshr_misses 906 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.icache.overall_accesses 72219408 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 4241.833509 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 3311.810155 # average overall mshr miss latency
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.icache.overall_hits 72218459 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 4025500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 949 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 43 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 3000500 # number of overall MSHR miss cycles
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000013 # mshr miss rate for overall accesses
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.icache.overall_mshr_misses 906 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.icache.replacements 34 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 906 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.icache.tagsinuse 774.513861 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 72218459 # Total number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.idleCycles 997 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 69153659 # Number of branches executed
|
|
|
|
|
system.cpu.iew.EXEC:nop 45896023 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.EXEC:rate 2.341699 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 168426251 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:stores 41748280 # Number of stores executed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.iew.WB:consumers 525987328 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 611675009 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.792003 # average fanout of values written-back
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.iew.WB:producers 416583352 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 2.329500 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 613682130 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 4878985 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewBlockCycles 11826 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 134508955 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 2507193 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 44216516 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 696353635 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 126677971 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 11034988 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 614878076 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewSquashCycles 14029871 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 4036 # Number of cycles IEW is unblocking
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 4056 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 10594878 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 23131 # Number of memory responses ignored because the instruction is squashed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 1076564 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 5809 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 19459445 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 4403993 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 1076564 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 574744 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 4304241 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.ipc 2.153847 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 2.153847 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0 625913064 # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
2006-12-05 01:07:00 +01:00
|
|
|
(null) 0 0.00% # Type of FU issued
|
2007-04-27 20:35:58 +02:00
|
|
|
IntAlu 452893161 72.36% # Type of FU issued
|
|
|
|
|
IntMult 6537 0.00% # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
IntDiv 0 0.00% # Type of FU issued
|
2007-04-27 20:35:58 +02:00
|
|
|
FloatAdd 27 0.00% # Type of FU issued
|
|
|
|
|
FloatCmp 5 0.00% # Type of FU issued
|
2006-12-05 01:07:00 +01:00
|
|
|
FloatCvt 5 0.00% # Type of FU issued
|
2007-04-27 20:35:58 +02:00
|
|
|
FloatMult 4 0.00% # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
|
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
2007-04-27 20:35:58 +02:00
|
|
|
MemRead 130507417 20.85% # Type of FU issued
|
|
|
|
|
MemWrite 42505908 6.79% # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
|
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 6267821 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.010014 # FU busy rate (busy events/executed inst)
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
|
|
|
(null) 0 0.00% # attempts to use FU when none available
|
2007-04-27 20:35:58 +02:00
|
|
|
IntAlu 5230779 83.45% # attempts to use FU when none available
|
|
|
|
|
IntMult 183 0.00% # attempts to use FU when none available
|
2006-10-12 21:04:14 +02:00
|
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
2007-04-27 20:35:58 +02:00
|
|
|
MemRead 663118 10.58% # attempts to use FU when none available
|
|
|
|
|
MemWrite 373741 5.96% # attempts to use FU when none available
|
2006-10-12 21:04:14 +02:00
|
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
|
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 262577811
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
2007-04-27 20:35:58 +02:00
|
|
|
0 49543053 1886.80%
|
|
|
|
|
1 42653619 1624.42%
|
|
|
|
|
2 65996372 2513.40%
|
|
|
|
|
3 28722982 1093.88%
|
|
|
|
|
4 36210264 1379.03%
|
|
|
|
|
5 20379063 776.12%
|
|
|
|
|
6 16095665 612.99%
|
|
|
|
|
7 2026950 77.19%
|
|
|
|
|
8 949843 36.17%
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
|
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.iq.ISSUE:rate 2.383724 # Inst issue rate
|
|
|
|
|
system.cpu.iq.iqInstsAdded 650457589 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 625913064 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 83477196 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 265708 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 44589775 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 482372 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 5974.559204 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2202.761362 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 456056 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 157226500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.054555 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 26316 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 57967868 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054555 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 26316 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 338333 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 338333 # number of Writeback hits
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.l2cache.avg_refs 30.186541 # Average number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 482372 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 5974.559204 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 2202.761362 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_hits 456056 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 157226500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.054555 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 26316 # number of demand (read+write) misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 57967868 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.054555 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 26316 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.l2cache.overall_accesses 820705 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 5974.559204 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 2202.761362 # average overall mshr miss latency
|
2007-02-14 19:05:20 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.l2cache.overall_hits 794389 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 157226500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.032065 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 26316 # number of overall misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 57967868 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.032065 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 26316 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.l2cache.replacements 932 # number of replacements
|
|
|
|
|
system.cpu.l2cache.sampled_refs 26316 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 25073.756706 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 794389 # Total number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.l2cache.writebacks 904 # number of writebacks
|
|
|
|
|
system.cpu.numCycles 262577811 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.rename.RENAME:BlockCycles 2682297 # Number of cycles rename is blocking
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.rename.RENAME:IQFullEvents 30243185 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.RENAME:IdleCycles 96498295 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 1942834 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RENAME:RenameLookups 952429183 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 727912324 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 552445892 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 117213862 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 14029871 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 32153216 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 88591003 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 270 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RENAME:serializingInsts 33 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.RENAME:skidInsts 50706382 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 31 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
