Update Alpha reference stats for clock changes.
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr:
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini:
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out:
tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout:
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini:
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out:
tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr:
tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr:
Update refs for clock changes.
--HG--
extra : convert_revision : 7c32a3362da60fd12b7bf9219842f707319cda42
This commit is contained in:
Kevin Lim
parent
522e59840f
commit
7f39291c81
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@ -23,7 +23,7 @@ activity=0
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backComSize=5
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choiceCtrBits=2
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choicePredictorSize=8192
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clock=1
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clock=500
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commitToDecodeDelay=1
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commitToFetchDelay=1
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commitToIEWDelay=1
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@ -167,7 +167,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
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[system.cpu]
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type=DerivO3CPU
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clock=1
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clock=500
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phase=0
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numThreads=1
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cpu_id=0
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@ -1,40 +1,40 @@
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 71631614 # Number of BTB hits
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global.BPredUnit.BTBLookups 80215513 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 194 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 4366377 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 76991765 # Number of conditional branches predicted
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global.BPredUnit.lookups 83232960 # Number of BP lookups
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global.BPredUnit.usedRAS 1776050 # Number of times the RAS was used to get a target.
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host_inst_rate 91613 # Simulator instruction rate (inst/s)
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host_mem_usage 151676 # Number of bytes of host memory used
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host_seconds 6173.25 # Real time elapsed on the host
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host_tick_rate 271486 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 26015543 # Number of conflicting loads.
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||||
memdepunit.memDep.conflictingStores 23632204 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 134244919 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 44983310 # Number of stores inserted to the mem dependence unit.
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global.BPredUnit.BTBHits 74294088 # Number of BTB hits
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global.BPredUnit.BTBLookups 83217138 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 175 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 4320797 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 79655810 # Number of conditional branches predicted
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global.BPredUnit.lookups 86600861 # Number of BP lookups
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global.BPredUnit.usedRAS 1992384 # Number of times the RAS was used to get a target.
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host_inst_rate 121760 # Simulator instruction rate (inst/s)
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host_mem_usage 154560 # Number of bytes of host memory used
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host_seconds 4644.82 # Real time elapsed on the host
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host_tick_rate 28265671 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 20253948 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 12668807 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 134508955 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 44216516 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 565552443 # Number of instructions simulated
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sim_seconds 0.001676 # Number of seconds simulated
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sim_ticks 1675949017 # Number of ticks simulated
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sim_seconds 0.131289 # Number of seconds simulated
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sim_ticks 131288904500 # Number of ticks simulated
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system.cpu.commit.COM:branches 62547159 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 16353031 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_lim_events 25836005 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 801372491
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system.cpu.commit.COM:committed_per_cycle.samples 248547939
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 580782547 7247.35%
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1 101892793 1271.48%
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2 41339172 515.85%
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3 11939444 148.99%
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4 15719123 196.15%
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5 17754998 221.56%
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6 10147917 126.63%
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7 5443466 67.93%
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8 16353031 204.06%
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0 64112537 2579.48%
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1 73997996 2977.21%
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2 29649485 1192.91%
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3 7413919 298.29%
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4 16299890 655.80%
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5 20436719 822.24%
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6 3362671 135.29%
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7 7438717 299.29%
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8 25836005 1039.48%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 115049510 # Nu
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 154862033 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 4365734 # The number of times a branch was mispredicted
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system.cpu.commit.branchMispredicts 4320164 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 90079827 # The number of squashed insts skipped by commit
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system.cpu.commit.commitSquashedInsts 94497449 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 565552443 # Number of Instructions Simulated
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system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
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system.cpu.cpi 2.963384 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 2.963384 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 120253770 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 3927.286441 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3434.366579 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 119156440 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 4309529230 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.009125 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 1097330 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 872988 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 770472667 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.001866 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 224342 # number of ReadReq MSHR misses
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system.cpu.cpi 0.464286 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.464286 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 115538611 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 2723.249468 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2089.628248 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 114910502 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 1710497500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.005436 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 628109 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 403470 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 469412000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.001944 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 224639 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 9089.303046 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9344.661839 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 37503702 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 17702499310 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.049368 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 1947619 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1690762 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 2400241806 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.006511 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 256857 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs 327.941025 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets 3498.764706 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 325.562069 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 3493 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 17 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 1145498 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 59479 # number of cycles access was blocked
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system.cpu.dcache.WriteReq_avg_miss_latency 3076.718619 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2314.396461 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 38683248 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 2363144500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.019469 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 768073 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 511246 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 594399500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.006510 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 256827 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs 539.249147 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets 250 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 319.012661 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 1172 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 4 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 632000 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 1000 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 159705091 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 7229.030286 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 6589.195890 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 156660142 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 22012028540 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.019066 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 3044949 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 2563750 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 3170714473 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.003013 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 481199 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_accesses 154989932 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 2917.701274 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 2209.525699 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 153593750 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 4073642000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.009008 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 1396182 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 914716 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 1063811500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.003106 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 481466 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 159705091 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 7229.030286 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 6589.195890 # average overall mshr miss latency
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system.cpu.dcache.overall_accesses 154989932 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 2917.701274 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 2209.525699 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 156660142 # number of overall hits
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system.cpu.dcache.overall_miss_latency 22012028540 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.019066 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 3044949 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 2563750 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 3170714473 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.003013 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 481199 # number of overall MSHR misses
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system.cpu.dcache.overall_hits 153593750 # number of overall hits
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system.cpu.dcache.overall_miss_latency 4073642000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.009008 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1396182 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 914716 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 1063811500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.003106 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 481466 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 477103 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 481199 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 477370 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 481466 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4063.174314 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 156660142 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 20910000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 338217 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 515310439 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 681 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 4340917 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 740208637 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 161139948 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 116871564 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 14453620 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 2001 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 8050541 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 83232960 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 72135284 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 198811102 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1485258 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 751818937 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 5990379 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.102023 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 72135284 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 73407664 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.921543 # Number of inst fetches per cycle
|
||||
system.cpu.dcache.tagsinuse 4095.510322 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 153593750 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 24474000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 338333 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 34835558 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 676 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 4837262 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 747469994 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 87926948 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 115162373 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 14029871 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 2002 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 10623061 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 86600861 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 72219408 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 200341434 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 435 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 760297798 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 4883794 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.329810 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 72219408 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 76286472 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.895514 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 815826112
|
||||
system.cpu.fetch.rateDist.samples 262577811
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 689150299 8447.27%
|
||||
1 10579353 129.68%
|
||||
2 12110332 148.44%
|
||||
3 11560507 141.70%
|
||||
4 9007686 110.41%
|
||||
5 3425511 41.99%
|
||||
6 3768928 46.20%
|
||||
7 3222436 39.50%
|
||||
8 73001060 894.81%
|
||||
0 134455787 5120.61%
|
||||
1 11289278 429.94%
|
||||
2 12199345 464.60%
|
||||
3 11605085 441.97%
|
||||
4 7894720 300.66%
|
||||
5 3823699 145.62%
|
||||
6 3913283 149.03%
|
||||
7 3555410 135.40%
|
||||
8 73841204 2812.16%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 72135284 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 5699.600162 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4917.297556 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 72134046 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 7056105 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000017 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 1238 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 297 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 4627177 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 72219408 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 4241.833509 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3311.810155 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 72218459 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 4025500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 949 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 3000500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000013 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 941 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses 906 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets 3783 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 76656.797024 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 79711.323400 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 1 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 3783 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 72135284 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 5699.600162 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 4917.297556 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 72134046 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 7056105 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000017 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 1238 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 297 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 4627177 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_accesses 72219408 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 4241.833509 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 3311.810155 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 72218459 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 4025500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 949 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 43 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 3000500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000013 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 941 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 906 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 72135284 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 5699.600162 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 4917.297556 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 72219408 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 4241.833509 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 3311.810155 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 72134046 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 7056105 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000017 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 1238 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 297 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 4627177 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_hits 72218459 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 4025500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 949 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 43 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 3000500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000013 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 941 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 906 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -215,81 +215,81 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 44 # number of replacements
|
||||
system.cpu.icache.sampled_refs 941 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 34 # number of replacements
|
||||
system.cpu.icache.sampled_refs 906 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 749.515669 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 72134046 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 774.513861 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 72218459 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 860122906 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 67691806 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 43795429 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.748142 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 168635664 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 41396142 # Number of stores executed
|
||||
system.cpu.idleCycles 997 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 69153659 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 45896023 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 2.341699 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 168426251 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 41748280 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 508232399 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 603225060 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.792920 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 525987328 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 611675009 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.792003 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 402987686 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.739404 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 604785539 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 4695315 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 442855270 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 134244919 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 5961708 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 44983310 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 691933738 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 127239522 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 6754480 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 610353566 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 42801 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 416583352 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 2.329500 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 613682130 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 4878985 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 11826 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 134508955 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 2507193 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 44216516 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 696353635 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 126677971 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 11034988 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 614878076 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 120734 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 14453620 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 431168 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 14029871 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 4036 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 1871526 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 4575118 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 24838 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 4056 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 10594878 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 23131 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 1001889 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 5578 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 19195409 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 5170787 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 1001889 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 542024 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 4153291 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.337452 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.337452 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 617108046 # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 1076564 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 5809 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 19459445 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 4403993 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 1076564 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 574744 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 4304241 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 2.153847 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 2.153847 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 625913064 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
(null) 0 0.00% # Type of FU issued
|
||||
IntAlu 445691749 72.22% # Type of FU issued
|
||||
IntMult 6563 0.00% # Type of FU issued
|
||||
IntAlu 452893161 72.36% # Type of FU issued
|
||||
IntMult 6537 0.00% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 33 0.00% # Type of FU issued
|
||||
FloatCmp 6 0.00% # Type of FU issued
|
||||
FloatAdd 27 0.00% # Type of FU issued
|
||||
FloatCmp 5 0.00% # Type of FU issued
|
||||
FloatCvt 5 0.00% # Type of FU issued
|
||||
FloatMult 5 0.00% # Type of FU issued
|
||||
FloatMult 4 0.00% # Type of FU issued
|
||||
FloatDiv 0 0.00% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 129192933 20.94% # Type of FU issued
|
||||
MemWrite 42216752 6.84% # Type of FU issued
|
||||
MemRead 130507417 20.85% # Type of FU issued
|
||||
MemWrite 42505908 6.79% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 3402065 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.005513 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 6267821 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.010014 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
(null) 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 2626203 77.19% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 5230779 83.45% # attempts to use FU when none available
|
||||
IntMult 183 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 0 0.00% # attempts to use FU when none available
|
||||
FloatCmp 0 0.00% # attempts to use FU when none available
|
||||
|
|
@ -297,80 +297,80 @@ system.cpu.iq.ISSUE:fu_full.start_dist
|
|||
FloatMult 0 0.00% # attempts to use FU when none available
|
||||
FloatDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 644339 18.94% # attempts to use FU when none available
|
||||
MemWrite 131523 3.87% # attempts to use FU when none available
|
||||
MemRead 663118 10.58% # attempts to use FU when none available
|
||||
MemWrite 373741 5.96% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 815826112
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 262577811
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 553114491 6779.81%
|
||||
1 85371128 1046.44%
|
||||
2 77782451 953.42%
|
||||
3 52154516 639.28%
|
||||
4 28098332 344.42%
|
||||
5 10103046 123.84%
|
||||
6 7930576 97.21%
|
||||
7 956122 11.72%
|
||||
8 315450 3.87%
|
||||
0 49543053 1886.80%
|
||||
1 42653619 1624.42%
|
||||
2 65996372 2513.40%
|
||||
3 28722982 1093.88%
|
||||
4 36210264 1379.03%
|
||||
5 20379063 776.12%
|
||||
6 16095665 612.99%
|
||||
7 2026950 77.19%
|
||||
8 949843 36.17%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 0.756421 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 648138284 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 617108046 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 80438129 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 1088392 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 57507029 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadReq_accesses 482140 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 8078.944187 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2363.998861 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 455802 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 212783232 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.054627 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 26338 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 62263002 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054627 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 26338 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 338217 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 338217 # number of Writeback hits
|
||||
system.cpu.iq.ISSUE:rate 2.383724 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 650457589 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 625913064 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 83477196 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 265708 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 44589775 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadReq_accesses 482372 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 5974.559204 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2202.761362 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 456056 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 157226500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.054555 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 26316 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 57967868 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054555 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 26316 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 338333 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 338333 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 30.147278 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 30.186541 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 482140 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 8078.944187 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2363.998861 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 455802 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 212783232 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.054627 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 26338 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 482372 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 5974.559204 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2202.761362 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 456056 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 157226500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.054555 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 26316 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 62263002 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.054627 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 26338 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 57967868 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.054555 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 26316 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 820357 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 8078.944187 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2363.998861 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_accesses 820705 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 5974.559204 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2202.761362 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 794019 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 212783232 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.032106 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 26338 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 794389 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 157226500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.032065 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 26316 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 62263002 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.032106 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 26338 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 57967868 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.032065 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 26316 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -382,32 +382,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 935 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 26338 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 932 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 26316 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 24391.955858 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 794019 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 25073.756706 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 794389 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 908 # number of writebacks
|
||||
system.cpu.numCycles 815826112 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 467231804 # Number of cycles rename is blocking
|
||||
system.cpu.l2cache.writebacks 904 # number of writebacks
|
||||
system.cpu.numCycles 262577811 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 2682297 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 38638370 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 170863189 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 8553533 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 36121 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 961623776 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 729244091 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 554812455 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 115192044 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 14453620 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 48042805 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 90957566 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 42650 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 30 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 77555696 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 28 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 308219 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:IQFullEvents 30243185 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 96498295 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 1942834 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 952429183 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 727912324 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 552445892 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 117213862 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 14029871 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 32153216 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 88591003 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 270 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 33 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 50706382 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 31 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,48 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
checkpoint=
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
print_data=true
|
||||
print_effaddr=true
|
||||
print_fetchseq=false
|
||||
print_iregs=false
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
speculative=true
|
||||
trace_system=client
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
dir=cpt.%012d
|
||||
period=0
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
|
||||
ignore_events=
|
||||
mysql_db=
|
||||
mysql_host=
|
||||
mysql_password=
|
||||
mysql_user=
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_compat=true
|
||||
text_file=m5stats.txt
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -53,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
@ -74,7 +33,7 @@ icache_port=system.membus.port[1]
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-atomic
|
||||
cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
euid=100
|
||||
|
|
@ -100,14 +59,6 @@ type=PhysicalMemory
|
|||
file=
|
||||
latency=1
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
ignore=
|
||||
start=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,15 +1,13 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
dummy=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
range=[0,134217727]
|
||||
latency=1
|
||||
zero=false
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -30,7 +28,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
|
|||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-atomic
|
||||
cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
|
|
@ -49,7 +47,7 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
width=1
|
||||
|
|
@ -57,51 +55,3 @@ function_trace=false
|
|||
function_trace_start=0
|
||||
simulate_stalls=false
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
ignore=
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[random]
|
||||
seed=1
|
||||
|
||||
[exetrace]
|
||||
speculative=true
|
||||
print_cycle=true
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
print_effaddr=true
|
||||
print_data=true
|
||||
print_iregs=false
|
||||
print_fetchseq=false
|
||||
print_cpseq=false
|
||||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 970342 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 144620 # Number of bytes of host memory used
|
||||
host_seconds 620.25 # Real time elapsed on the host
|
||||
host_tick_rate 970342 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 964119 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 148524 # Number of bytes of host memory used
|
||||
host_seconds 624.26 # Real time elapsed on the host
|
||||
host_tick_rate 482059313 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 601856965 # Number of instructions simulated
|
||||
sim_seconds 0.000602 # Number of seconds simulated
|
||||
sim_ticks 601856964 # Number of ticks simulated
|
||||
sim_seconds 0.300928 # Number of seconds simulated
|
||||
sim_ticks 300928482000 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 601856965 # number of cpu cycles simulated
|
||||
|
|
|
|||
|
|
@ -1 +1,2 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -1,48 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
checkpoint=
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
print_data=true
|
||||
print_effaddr=true
|
||||
print_fetchseq=false
|
||||
print_iregs=false
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
speculative=true
|
||||
trace_system=client
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
dir=cpt.%012d
|
||||
period=0
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
|
||||
ignore_events=
|
||||
mysql_db=
|
||||
mysql_host=
|
||||
mysql_password=
|
||||
mysql_user=
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_compat=true
|
||||
text_file=m5stats.txt
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -53,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache icache l2cache toL2Bus workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
@ -197,7 +156,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-timing
|
||||
cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
euid=100
|
||||
|
|
@ -223,14 +182,6 @@ type=PhysicalMemory
|
|||
file=
|
||||
latency=1
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
ignore=
|
||||
start=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,15 +1,13 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
dummy=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
range=[0,134217727]
|
||||
latency=1
|
||||
zero=false
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -30,7 +28,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
|
|||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-timing
|
||||
cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
|
|
@ -49,7 +47,7 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
// width not specified
|
||||
|
|
@ -178,51 +176,3 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
ignore=
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[random]
|
||||
seed=1
|
||||
|
||||
[exetrace]
|
||||
speculative=true
|
||||
print_cycle=true
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
print_effaddr=true
|
||||
print_data=true
|
||||
print_iregs=false
|
||||
print_fetchseq=false
|
||||
print_cpseq=false
|
||||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 549029 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 300652 # Number of bytes of host memory used
|
||||
host_seconds 1096.22 # Real time elapsed on the host
|
||||
host_tick_rate 1916109 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 642291 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 153996 # Number of bytes of host memory used
|
||||
host_seconds 937.05 # Real time elapsed on the host
|
||||
host_tick_rate 404322160 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 601856965 # Number of instructions simulated
|
||||
sim_seconds 0.002100 # Number of seconds simulated
|
||||
sim_ticks 2100480012 # Number of ticks simulated
|
||||
sim_seconds 0.378869 # Number of seconds simulated
|
||||
sim_ticks 378869140000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 2845.396229 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1845.396229 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 2584.255983 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1584.255983 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 572584774 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 520035000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 371352774 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 318803000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3026.723012 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2026.723012 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 2608.788455 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 1608.788455 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 39197158 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 769281001 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 663057500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.006442 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 254163 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 515118001 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 408894500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 2946.597514 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 1946.597514 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 2597.947935 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 1597.947935 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 153509968 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 1341865775 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 1183092500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.002958 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 455395 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 886470775 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 727697500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 2946.597514 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 1946.597514 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 2597.947935 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 1597.947935 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 153509968 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 1341865775 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 1183092500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.002958 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 455395 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 886470775 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 727697500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 451299 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4053.427393 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4095.423304 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 33693000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.warmup_cycle 102411000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 325723 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 601856966 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 4085.659119 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3085.659119 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3746.540881 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2746.540881 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 601856171 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 3248099 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 2978500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 2453099 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 2183500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 601856966 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 4085.659119 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 3085.659119 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 3746.540881 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2746.540881 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 601856171 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 3248099 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 2978500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 795 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 2453099 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 2183500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 601856966 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 4085.659119 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 3085.659119 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 3746.540881 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2746.540881 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 601856171 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 3248099 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 2978500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 795 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 2453099 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 2183500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -138,23 +138,23 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 24 # number of replacements
|
||||
system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 642.094524 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 674.110982 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 601856171 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 456190 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 3251.348149 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1946.946471 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2564.564334 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1563.181738 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 430092 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 84853684 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 66930000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.057209 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 26098 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 50811409 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 40795917 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.057209 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 26098 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 325723 # number of WriteReqNoAck|Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.WriteReqNoAck|Writeback_hits 325723 # number of WriteReqNoAck|Writeback hits
|
||||
system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 325723 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 28.960648 # Average number of references to valid blocks.
|
||||
|
|
@ -164,29 +164,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 3251.348149 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1946.946471 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2564.564334 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1563.181738 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 430092 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 84853684 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 66930000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.057209 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 26098 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 50811409 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 40795917 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.057209 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 26098 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 781913 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 3251.348149 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1946.946471 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2564.564334 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1563.181738 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 755815 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 84853684 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 66930000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.033377 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 26098 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 50811409 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 40795917 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.033377 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 26098 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -203,12 +203,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 903 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 26098 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 24085.007455 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 24878.910085 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 755815 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 883 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 2100480012 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 378869140000 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 601856965 # Number of instructions executed
|
||||
system.cpu.num_refs 154862034 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1 +1,2 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ activity=0
|
|||
backComSize=5
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
clock=1
|
||||
clock=500
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
|
|||
|
|
@ -167,7 +167,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
numThreads=1
|
||||
cpu_id=0
|
||||
|
|
|
|||
|
|
@ -1,112 +1,112 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 36573856 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 48300104 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 1110 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 6040473 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 37489973 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 66376995 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 13616030 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 78938 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 153528 # Number of bytes of host memory used
|
||||
host_seconds 4757.83 # Real time elapsed on the host
|
||||
host_tick_rate 66128 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 89962751 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 64024234 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 131935591 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 95765344 # Number of stores inserted to the mem dependence unit.
|
||||
global.BPredUnit.BTBHits 38358431 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 50162851 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 1146 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 6112182 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 38942362 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 68824046 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 14094584 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 88313 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 157144 # Number of bytes of host memory used
|
||||
host_seconds 4252.75 # Real time elapsed on the host
|
||||
host_tick_rate 26084457 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 79078987 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 58020753 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 131723270 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 96432918 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 375574675 # Number of instructions simulated
|
||||
sim_seconds 0.000315 # Number of seconds simulated
|
||||
sim_ticks 314625027 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 44587523 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 13381546 # number cycles where commit BW limit reached
|
||||
sim_insts 375574812 # Number of instructions simulated
|
||||
sim_seconds 0.110931 # Number of seconds simulated
|
||||
sim_ticks 110930737500 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 44587533 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 15191652 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 276331431
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 203296876
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 148231465 5364.26%
|
||||
1 40756250 1474.90%
|
||||
2 28135615 1018.18%
|
||||
3 18140880 656.49%
|
||||
4 10622787 384.42%
|
||||
5 8112500 293.58%
|
||||
6 5544405 200.64%
|
||||
7 3405983 123.26%
|
||||
8 13381546 484.26%
|
||||
0 83055980 4085.45%
|
||||
1 37801777 1859.44%
|
||||
2 20090473 988.23%
|
||||
3 18525905 911.27%
|
||||
4 11216575 551.73%
|
||||
5 8853752 435.51%
|
||||
6 5489461 270.02%
|
||||
7 3071301 151.07%
|
||||
8 15191652 747.26%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
system.cpu.commit.COM:count 398664447 # Number of instructions committed
|
||||
system.cpu.commit.COM:loads 100651988 # Number of loads committed
|
||||
system.cpu.commit.COM:count 398664587 # Number of instructions committed
|
||||
system.cpu.commit.COM:loads 100651995 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 174183388 # Number of memory references committed
|
||||
system.cpu.commit.COM:refs 174183397 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 6036288 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 398664447 # The number of committed instructions
|
||||
system.cpu.commit.branchMispredicts 6107953 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 398664587 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 118579541 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 375574675 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 375574675 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.837716 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.837716 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 96374626 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 5603.456853 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5219.612576 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 96372656 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 11038810 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000020 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1970 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 984 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 5146538 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.commit.commitSquashedInsts 122897297 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 375574812 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 375574812 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.590725 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.590725 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 96817111 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 4478.552279 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3669.007021 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 96815619 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 6682000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000015 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1492 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 495 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3658000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 986 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 73520727 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 6647.641993 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6867.316020 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 73501543 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 127528364 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000261 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 19184 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 15988 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 21947942 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_misses 997 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 4580.037179 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3751.017852 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 73511046 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 44348500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000132 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 9683 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 6490 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 11977000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 3196 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs 2800 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.WriteReq_mshr_misses 3193 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 40620.324964 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 19 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_refs 40650.755370 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 53200 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 169895353 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 6550.400586 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 6478.833094 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 169874199 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 138567174 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000125 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 21154 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 16972 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 27094480 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_accesses 170337840 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 4566.487696 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 3731.503580 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 170326665 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 51030500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000066 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 11175 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 6985 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 15635000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 4182 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 4190 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 169895353 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 6550.400586 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 6478.833094 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_accesses 170337840 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 4566.487696 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 3731.503580 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 169874199 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 138567174 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000125 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 21154 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 16972 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 27094480 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_hits 170326665 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 51030500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000066 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 11175 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 6985 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 15635000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 4182 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 4190 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 786 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 4182 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 787 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 4190 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 3211.654167 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 169874199 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 3304.118717 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 170326665 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 639 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 32658535 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 4257 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 11810746 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 562730439 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 143183566 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 99541453 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 18560140 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 12611 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 947878 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 66376995 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 68531131 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 171584130 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1722712 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 577337575 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 6483468 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.225089 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 68531131 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 50189886 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.957796 # Number of inst fetches per cycle
|
||||
system.cpu.dcache.writebacks 642 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 19129336 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 4391 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 12122968 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 582055742 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 80258799 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 100428895 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 18564601 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 12469 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 3479847 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 68824046 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 70113587 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 177754526 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1413 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 605291130 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 6551564 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.310212 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 70113587 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 52453015 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.728239 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 294891572
|
||||
system.cpu.fetch.rateDist.samples 221861478
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 191838575 6505.39%
|
||||
1 8000057 271.29%
|
||||
2 8353997 283.29%
|
||||
3 6793291 230.37%
|
||||
4 15387795 521.81%
|
||||
5 8442060 286.28%
|
||||
6 8794810 298.24%
|
||||
7 2528585 85.75%
|
||||
8 44752402 1517.59%
|
||||
0 114220541 5148.28%
|
||||
1 8239331 371.37%
|
||||
2 8549373 385.35%
|
||||
3 6969058 314.12%
|
||||
4 16046109 723.25%
|
||||
5 8875051 400.03%
|
||||
6 9195050 414.45%
|
||||
7 2819832 127.10%
|
||||
8 46947133 2116.06%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 68531131 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 4689.224645 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3850.973049 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 68526132 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 23441434 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000073 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 4999 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 1103 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 15003391 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000057 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 3896 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_accesses 70113587 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3851.773227 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2889.186432 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 70109583 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 15422500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000057 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 4004 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 83 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 11328500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000056 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 3921 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 17588.842916 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 17880.536343 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 68531131 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 4689.224645 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 3850.973049 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 68526132 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 23441434 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000073 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 4999 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 1103 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 15003391 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000057 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 3896 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 70113587 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 3851.773227 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2889.186432 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 70109583 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 15422500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000057 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 4004 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 83 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 11328500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000056 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 3921 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 68531131 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 4689.224645 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 3850.973049 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 70113587 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 3851.773227 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2889.186432 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 68526132 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 23441434 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000073 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 4999 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 1103 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 15003391 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000057 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 3896 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 70109583 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 15422500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000057 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 4004 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 83 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 11328500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000056 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 3921 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -215,162 +215,162 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 1976 # number of replacements
|
||||
system.cpu.icache.sampled_refs 3896 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 1998 # number of replacements
|
||||
system.cpu.icache.sampled_refs 3921 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1786.777118 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 68526132 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1828.295849 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 70109583 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 19733456 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 52475714 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 28200659 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.439607 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 190729803 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 78992420 # Number of stores executed
|
||||
system.cpu.idleCycles -2 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 52992725 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 29946505 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.944645 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 194719104 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 80042784 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 302582293 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 419651187 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.683002 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 297392817 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 427980775 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.704330 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 206664160 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.423069 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 420984328 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 6525670 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 4581779 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 131935591 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 243 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 8433935 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 95765344 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 517242480 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 111737383 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 7591261 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 424527920 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 366722 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 209462789 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.929045 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 430386834 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 6770153 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 2285856 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 131723270 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 248 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 6165269 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 96432918 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 521561792 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 114676320 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 13198323 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 431441879 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 131901 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 32377 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 18560140 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 737234 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 25295 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 18564601 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 554549 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 8882 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 8984961 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 39727 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 10646448 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 56371 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 675434 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 175954 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 31283603 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 22233944 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 675434 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 1009222 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 5516448 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.193722 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.193722 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 432119181 # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 636490 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 215134 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 31071275 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 22901516 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 636490 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 1000963 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 5769190 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.692835 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.692835 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 444640202 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
(null) 33581 0.01% # Type of FU issued
|
||||
IntAlu 171100299 39.60% # Type of FU issued
|
||||
IntMult 2148839 0.50% # Type of FU issued
|
||||
IntAlu 177043734 39.82% # Type of FU issued
|
||||
IntMult 2204532 0.50% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 35472672 8.21% # Type of FU issued
|
||||
FloatCmp 7906658 1.83% # Type of FU issued
|
||||
FloatCvt 2966336 0.69% # Type of FU issued
|
||||
FloatMult 16725823 3.87% # Type of FU issued
|
||||
FloatDiv 1566508 0.36% # Type of FU issued
|
||||
FloatAdd 36105087 8.12% # Type of FU issued
|
||||
FloatCmp 7997969 1.80% # Type of FU issued
|
||||
FloatCvt 3013999 0.68% # Type of FU issued
|
||||
FloatMult 17176525 3.86% # Type of FU issued
|
||||
FloatDiv 1578480 0.36% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 113251606 26.21% # Type of FU issued
|
||||
MemWrite 80946859 18.73% # Type of FU issued
|
||||
MemRead 116850777 26.28% # Type of FU issued
|
||||
MemWrite 82635518 18.58% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 9237965 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.021378 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 12556872 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.028241 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
(null) 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 31984 0.35% # attempts to use FU when none available
|
||||
IntAlu 57761 0.46% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 74124 0.80% # attempts to use FU when none available
|
||||
FloatCmp 35886 0.39% # attempts to use FU when none available
|
||||
FloatCvt 5384 0.06% # attempts to use FU when none available
|
||||
FloatMult 1393766 15.09% # attempts to use FU when none available
|
||||
FloatDiv 1142138 12.36% # attempts to use FU when none available
|
||||
FloatAdd 28133 0.22% # attempts to use FU when none available
|
||||
FloatCmp 21849 0.17% # attempts to use FU when none available
|
||||
FloatCvt 3461 0.03% # attempts to use FU when none available
|
||||
FloatMult 3478872 27.70% # attempts to use FU when none available
|
||||
FloatDiv 916669 7.30% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 5413419 58.60% # attempts to use FU when none available
|
||||
MemWrite 1141264 12.35% # attempts to use FU when none available
|
||||
MemRead 6621449 52.73% # attempts to use FU when none available
|
||||
MemWrite 1428678 11.38% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 294891572
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 221861478
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 116554693 3952.46%
|
||||
1 58404803 1980.55%
|
||||
2 49059967 1663.66%
|
||||
3 31805455 1078.55%
|
||||
4 23494336 796.71%
|
||||
5 9548381 323.79%
|
||||
6 4038173 136.94%
|
||||
7 1656320 56.17%
|
||||
8 329444 11.17%
|
||||
0 66879354 3014.46%
|
||||
1 37689855 1698.80%
|
||||
2 36617552 1650.47%
|
||||
3 29239458 1317.92%
|
||||
4 27293259 1230.19%
|
||||
5 13755301 620.00%
|
||||
6 5789291 260.94%
|
||||
7 3467682 156.30%
|
||||
8 1129726 50.92%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 1.465349 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 489041578 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 432119181 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 243 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 113088119 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 1629891 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 97430194 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadReq_accesses 8078 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 4922.926872 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2406.841240 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 721 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 36217973 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.910745 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 7357 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 17707131 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.910745 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 7357 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 639 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 639 # number of Writeback hits
|
||||
system.cpu.iq.ISSUE:rate 2.004134 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 491615039 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 444640202 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 248 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 114649126 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 1134366 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 33 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 83844967 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadReq_accesses 8108 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 3327.551159 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1909.064236 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 729 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 24554000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.910089 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 7379 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 14086985 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.910089 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 7379 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 642 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 642 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.184858 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.185798 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 8078 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 4922.926872 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2406.841240 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 721 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 36217973 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.910745 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 7357 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 8108 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 3327.551159 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1909.064236 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 729 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 24554000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.910089 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 7379 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 17707131 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.910745 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 7357 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 14086985 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.910089 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 7379 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 8717 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 4922.926872 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2406.841240 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_accesses 8750 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 3327.551159 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1909.064236 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 1360 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 36217973 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.843983 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 7357 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 1371 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 24554000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.843314 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 7379 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 17707131 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.843983 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 7357 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 14086985 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.843314 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 7379 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -383,31 +383,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 7357 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 7379 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 6462.850486 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1360 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 6669.459869 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1371 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.numCycles 294891572 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 14686909 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 259532206 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 2446116 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 148616326 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 11769281 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 32 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 721460314 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 549210935 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 355537016 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 94743971 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 18560140 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 15563294 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 96004810 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 2720932 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 38133 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 34543353 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 264 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 6492 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.numCycles 221861478 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 6569281 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 259532333 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 1971772 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 86889182 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 8681438 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 731270765 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 559458182 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 360795698 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 96896401 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 18564601 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 12635219 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 101263365 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 306794 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 37801 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 32486829 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 267 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
Eon, Version 1.1
|
||||
OO-style eon Time= 0.000000
|
||||
OO-style eon Time= 0.100000
|
||||
|
|
|
|||
|
|
@ -1,48 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
checkpoint=
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
print_data=true
|
||||
print_effaddr=true
|
||||
print_fetchseq=false
|
||||
print_iregs=false
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
speculative=true
|
||||
trace_system=client
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
dir=cpt.%012d
|
||||
period=0
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
|
||||
ignore_events=
|
||||
mysql_db=
|
||||
mysql_host=
|
||||
mysql_password=
|
||||
mysql_user=
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_compat=true
|
||||
text_file=m5stats.txt
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -53,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
@ -74,7 +33,7 @@ icache_port=system.membus.port[1]
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
|
||||
cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-atomic
|
||||
cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
euid=100
|
||||
|
|
@ -100,14 +59,6 @@ type=PhysicalMemory
|
|||
file=
|
||||
latency=1
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
ignore=
|
||||
start=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,15 +1,13 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
dummy=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
range=[0,134217727]
|
||||
latency=1
|
||||
zero=false
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -30,7 +28,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
|||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-atomic
|
||||
cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
|
|
@ -49,7 +47,7 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
width=1
|
||||
|
|
@ -57,51 +55,3 @@ function_trace=false
|
|||
function_trace_start=0
|
||||
simulate_stalls=false
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
ignore=
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[random]
|
||||
seed=1
|
||||
|
||||
[exetrace]
|
||||
speculative=true
|
||||
print_cycle=true
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
print_effaddr=true
|
||||
print_data=true
|
||||
print_iregs=false
|
||||
print_fetchseq=false
|
||||
print_cpseq=false
|
||||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,18 +1,18 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 841426 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 147172 # Number of bytes of host memory used
|
||||
host_seconds 473.80 # Real time elapsed on the host
|
||||
host_tick_rate 841425 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 844104 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 151076 # Number of bytes of host memory used
|
||||
host_seconds 472.29 # Real time elapsed on the host
|
||||
host_tick_rate 422051705 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 398664450 # Number of instructions simulated
|
||||
sim_seconds 0.000399 # Number of seconds simulated
|
||||
sim_ticks 398664449 # Number of ticks simulated
|
||||
sim_insts 398664597 # Number of instructions simulated
|
||||
sim_seconds 0.199332 # Number of seconds simulated
|
||||
sim_ticks 199332298000 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 398664450 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 398664450 # Number of instructions executed
|
||||
system.cpu.num_refs 174183390 # Number of memory references
|
||||
system.cpu.numCycles 398664597 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 398664597 # Number of instructions executed
|
||||
system.cpu.num_refs 174183399 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,9 +1,11 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
getting pixel output filename pixels_out.cook
|
||||
opening control file chair.control.cook
|
||||
opening camera file chair.camera
|
||||
opening surfaces file chair.surfaces
|
||||
reading data
|
||||
warn: Increasing stack size by one page.
|
||||
processing 8parts
|
||||
Grid measure is 6 by 3.0001 by 6
|
||||
cell dimension is 0.863065
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
Eon, Version 1.1
|
||||
OO-style eon Time= 0.000000
|
||||
OO-style eon Time= 0.183333
|
||||
|
|
|
|||
|
|
@ -1,33 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
checkpoint=
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
dir=cpt.%012d
|
||||
period=0
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
|
||||
ignore_events=
|
||||
mysql_db=
|
||||
mysql_host=
|
||||
mysql_password=
|
||||
mysql_user=
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_compat=true
|
||||
text_file=m5stats.txt
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -38,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache icache l2cache toL2Bus workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
@ -182,11 +156,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
|
||||
cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/simple-timing
|
||||
cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
euid=100
|
||||
executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
gid=100
|
||||
input=cin
|
||||
output=cout
|
||||
|
|
|
|||
|
|
@ -1,9 +1,6 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
dummy=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -27,11 +24,11 @@ responder_set=false
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
|
||||
executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/simple-timing
|
||||
cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
|
|
@ -50,7 +47,7 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
// width not specified
|
||||
|
|
@ -179,23 +176,3 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,65 +1,65 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 689508 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 185012 # Number of bytes of host memory used
|
||||
host_seconds 578.19 # Real time elapsed on the host
|
||||
host_tick_rate 1033135 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 557007 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 156576 # Number of bytes of host memory used
|
||||
host_seconds 715.73 # Real time elapsed on the host
|
||||
host_tick_rate 396092779 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 398664450 # Number of instructions simulated
|
||||
sim_seconds 0.000597 # Number of seconds simulated
|
||||
sim_ticks 597346012 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 94754482 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3956.610526 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2956.610526 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 94753532 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 3758780 # number of ReadReq miss cycles
|
||||
sim_insts 398664597 # Number of instructions simulated
|
||||
sim_seconds 0.283494 # Number of seconds simulated
|
||||
sim_ticks 283494379000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 94754489 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3630.526316 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2630.526316 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 94753539 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 3449000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2808780 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2499000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 73520727 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3940.471580 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2940.471580 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 73517525 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 12617390 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3618.988132 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2618.988132 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 73517527 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 11588000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 3202 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 9415390 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 8386000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 40527.711224 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 40527.713391 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 168275209 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3944.164258 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2944.164258 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 168271057 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 16376170 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_accesses 168275218 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3621.628131 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2621.628131 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 168271066 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 15037000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 4152 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 12224170 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 10885000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 168275209 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3944.164258 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2944.164258 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 168271057 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 16376170 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_accesses 168275218 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3621.628131 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2621.628131 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 168271066 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 15037000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 4152 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 12224170 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 10885000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,54 +76,54 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 764 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 3222.413784 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 168271057 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 3289.772430 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 168271066 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 625 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 398664451 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3820.906097 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2820.906097 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 398660777 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 14038009 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 398664598 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3633.814321 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2633.814321 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 398660925 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 13347000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 3674 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 10364009 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 9674000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 3674 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 108508.649156 # Average number of references to valid blocks.
|
||||
system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 108538.231691 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 398664451 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 3820.906097 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2820.906097 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 398660777 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 14038009 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_accesses 398664598 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 3633.814321 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2633.814321 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 398660925 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 13347000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 3674 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 10364009 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 9674000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 3674 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 3673 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 398664451 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 3820.906097 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2820.906097 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 398660777 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 14038009 # number of overall miss cycles
|
||||
system.cpu.icache.overall_accesses 398664598 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 3633.814321 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2633.814321 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 398660925 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 13347000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 3674 # number of overall misses
|
||||
system.cpu.icache.overall_misses 3673 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 10364009 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 9674000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 3674 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -135,60 +135,60 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 1770 # number of replacements
|
||||
system.cpu.icache.sampled_refs 3674 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 1769 # number of replacements
|
||||
system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1765.882838 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 398660777 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1795.510184 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 398660925 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 7826 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2983.265505 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1924.984530 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_accesses 7825 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2707.276275 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1705.023697 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 651 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 21404930 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.916816 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 7175 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 13811764 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916816 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 7175 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 19422000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.916805 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 7174 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 12231840 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916805 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 7174 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.177840 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.177865 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 7826 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2983.265505 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1924.984530 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2707.276275 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1705.023697 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 651 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 21404930 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.916816 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 7175 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_miss_latency 19422000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.916805 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 7174 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 13811764 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.916816 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 7175 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 12231840 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.916805 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 7174 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 8451 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2983.265505 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1924.984530 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_accesses 8450 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2707.276275 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1705.023697 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 1276 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 21404930 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.849012 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 7175 # number of overall misses
|
||||
system.cpu.l2cache.overall_miss_latency 19422000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.848994 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 7174 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 13811764 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.849012 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 7175 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 12231840 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.848994 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 7174 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -201,16 +201,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 7175 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 7174 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 6344.042673 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 6483.699084 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1276 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 597346012 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 398664450 # Number of instructions executed
|
||||
system.cpu.num_refs 174183390 # Number of memory references
|
||||
system.cpu.numCycles 283494379000 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 398664597 # Number of instructions executed
|
||||
system.cpu.num_refs 174183399 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
getting pixel output filename pixels_out.cook
|
||||
opening control file chair.control.cook
|
||||
opening camera file chair.camera
|
||||
opening surfaces file chair.surfaces
|
||||
reading data
|
||||
warn: Increasing stack size by one page.
|
||||
processing 8parts
|
||||
Grid measure is 6 by 3.0001 by 6
|
||||
cell dimension is 0.863065
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
Eon, Version 1.1
|
||||
OO-style eon Time= 0.000000
|
||||
OO-style eon Time= 0.283333
|
||||
|
|
|
|||
|
|
@ -1,33 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
checkpoint=
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
dir=cpt.%012d
|
||||
period=0
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
|
||||
ignore_events=
|
||||
mysql_db=
|
||||
mysql_host=
|
||||
mysql_password=
|
||||
mysql_user=
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_compat=true
|
||||
text_file=m5stats.txt
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -38,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
@ -59,11 +33,11 @@ icache_port=system.membus.port[1]
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
||||
cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-atomic
|
||||
cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
euid=100
|
||||
executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
gid=100
|
||||
input=cin
|
||||
output=cout
|
||||
|
|
|
|||
|
|
@ -1,9 +1,6 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
dummy=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -27,11 +24,11 @@ responder_set=false
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
||||
executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-atomic
|
||||
cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
|
|
@ -50,7 +47,7 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
width=1
|
||||
|
|
@ -58,23 +55,3 @@ function_trace=false
|
|||
function_trace_start=0
|
||||
simulate_stalls=false
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1149393 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 177516 # Number of bytes of host memory used
|
||||
host_seconds 1747.87 # Real time elapsed on the host
|
||||
host_tick_rate 1149393 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 855453 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 151192 # Number of bytes of host memory used
|
||||
host_seconds 2348.45 # Real time elapsed on the host
|
||||
host_tick_rate 427726617 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 2008987607 # Number of instructions simulated
|
||||
sim_seconds 0.002009 # Number of seconds simulated
|
||||
sim_ticks 2008987606 # Number of ticks simulated
|
||||
sim_seconds 1.004494 # Number of seconds simulated
|
||||
sim_ticks 1004493803000 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 2008987607 # number of cpu cycles simulated
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
warn: ignoring syscall sigprocmask(1, 0, ...)
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -1,33 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
checkpoint=
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
dir=cpt.%012d
|
||||
period=0
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
|
||||
ignore_events=
|
||||
mysql_db=
|
||||
mysql_host=
|
||||
mysql_password=
|
||||
mysql_user=
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_compat=true
|
||||
text_file=m5stats.txt
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -38,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache icache l2cache toL2Bus workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
@ -182,11 +156,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
||||
cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-timing
|
||||
cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
euid=100
|
||||
executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
gid=100
|
||||
input=cin
|
||||
output=cout
|
||||
|
|
|
|||
|
|
@ -1,9 +1,6 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
dummy=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -27,11 +24,11 @@ responder_set=false
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
||||
executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-timing
|
||||
cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
|
|
@ -50,7 +47,7 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
// width not specified
|
||||
|
|
@ -179,23 +176,3 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,35 +1,35 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 752631 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 230876 # Number of bytes of host memory used
|
||||
host_seconds 2669.29 # Real time elapsed on the host
|
||||
host_tick_rate 2836913 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 594701 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 156660 # Number of bytes of host memory used
|
||||
host_seconds 3378.14 # Real time elapsed on the host
|
||||
host_tick_rate 405574512 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 2008987607 # Number of instructions simulated
|
||||
sim_seconds 0.007573 # Number of seconds simulated
|
||||
sim_ticks 7572532003 # Number of ticks simulated
|
||||
sim_seconds 1.370090 # Number of seconds simulated
|
||||
sim_ticks 1370089513500 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3107.171986 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2107.171986 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3511.656558 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2511.656558 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 4530853333 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 5120669500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3072661333 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3662477500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3884.267929 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2884.267929 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3914.581944 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2914.581944 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 210722944 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 279480846 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 281662000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000341 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 71952 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 207528846 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 209710000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000341 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 71952 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3143.713388 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2143.713388 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 3530.603329 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2530.603329 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 720334778 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 4810334179 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 5402331500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.002120 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1530144 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3280190179 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3872187500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002120 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1530144 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3143.713388 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2143.713388 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 3530.603329 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2530.603329 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 720334778 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 4810334179 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 5402331500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.002120 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1530144 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3280190179 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3872187500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002120 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1530144 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,22 +76,22 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 1526048 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4087.479154 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4095.457388 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 35165000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.warmup_cycle 325153000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 74589 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 2008987608 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3103.627312 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2103.627312 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 2952.765194 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 1952.765194 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 2008977012 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 32886035 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 31287500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 22290035 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 20691500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 189597.679502 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
|
|
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 2008987608 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 3103.627312 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2103.627312 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 2952.765194 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 1952.765194 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 2008977012 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 32886035 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 31287500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 22290035 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 20691500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 10596 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 2008987608 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 3103.627312 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2103.627312 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_miss_latency 2952.765194 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 1952.765194 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 2008977012 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 32886035 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 31287500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 10596 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 22290035 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 20691500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 9046 # number of replacements
|
||||
system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1471.254279 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1478.638648 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 2008977012 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 1540740 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2153.828221 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1111.659139 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2545.120588 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1544.109658 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 33878 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 3245521901 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 3835145500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.978012 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1506862 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1675116913 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 2326760167 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.978012 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1506862 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses)
|
||||
|
|
@ -159,8 +159,8 @@ system.cpu.l2cache.Writeback_miss_rate 0.014399 # mi
|
|||
system.cpu.l2cache.Writeback_misses 1074 # number of Writeback misses
|
||||
system.cpu.l2cache.Writeback_mshr_miss_rate 0.014399 # mshr miss rate for Writeback accesses
|
||||
system.cpu.l2cache.Writeback_mshr_misses 1074 # number of Writeback MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.071269 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
|
|
@ -168,29 +168,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2153.828221 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1111.659139 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2545.120588 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1544.109658 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 33878 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 3245521901 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 3835145500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.978012 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 1506862 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 1675116913 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 2326760167 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.978012 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 1506862 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 1615329 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2152.294196 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1111.659139 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2543.307872 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1544.109658 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 107393 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 3245521901 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 3835145500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.933516 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 1507936 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 1675116913 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 2326760167 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.932851 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 1506862 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -207,12 +207,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 1474094 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 1506862 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 32444.706916 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 32754.836517 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 107393 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 164189000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.warmup_cycle 1084960000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 66804 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 7572532003 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1370089513500 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 2008987607 # Number of instructions executed
|
||||
system.cpu.num_refs 722390435 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
warn: ignoring syscall sigprocmask(1, 0, ...)
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ activity=0
|
|||
backComSize=5
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
clock=1
|
||||
clock=500
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
|
|||
|
|
@ -167,7 +167,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
numThreads=1
|
||||
cpu_id=0
|
||||
|
|
|
|||
|
|
@ -1,40 +1,40 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 7945230 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 13714223 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 29001 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 454297 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 10141226 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 15617287 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 1851141 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 91600 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 155864 # Number of bytes of host memory used
|
||||
host_seconds 868.91 # Real time elapsed on the host
|
||||
host_tick_rate 1051887 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 16262618 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 12842437 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 22199501 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 16236124 # Number of stores inserted to the mem dependence unit.
|
||||
global.BPredUnit.BTBHits 7744324 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 13591046 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 32932 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 452723 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 10077718 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 15489897 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 1844517 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 108228 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 159488 # Number of bytes of host memory used
|
||||
host_seconds 735.41 # Real time elapsed on the host
|
||||
host_tick_rate 23792996 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 12942665 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 11520420 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 21780362 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 15866784 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 79591756 # Number of instructions simulated
|
||||
sim_seconds 0.000914 # Number of seconds simulated
|
||||
sim_ticks 913992014 # Number of ticks simulated
|
||||
sim_seconds 0.017498 # Number of seconds simulated
|
||||
sim_ticks 17497602000 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 13754477 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 3798224 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 4260073 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 61093189
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 33996100
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 33945527 5556.35%
|
||||
1 9263496 1516.29%
|
||||
2 5234944 856.88%
|
||||
3 3369457 551.53%
|
||||
4 2068681 338.61%
|
||||
5 1423240 232.96%
|
||||
6 1205139 197.26%
|
||||
7 784481 128.41%
|
||||
8 3798224 621.71%
|
||||
0 8358440 2458.65%
|
||||
1 8230566 2421.03%
|
||||
2 4712162 1386.09%
|
||||
3 3108634 914.41%
|
||||
4 2121957 624.18%
|
||||
5 1131901 332.95%
|
||||
6 1374606 404.34%
|
||||
7 697761 205.25%
|
||||
8 4260073 1253.11%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
|
|
@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 20379399 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 35224018 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 359791 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 356682 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 8215609 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 6565781 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
|
||||
system.cpu.cpi 11.483501 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 11.483501 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 19669616 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 4470.389268 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3240.793422 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 19511676 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 706053281 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.008030 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 157940 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 96341 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 199629634 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003132 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 61599 # number of ReadReq MSHR misses
|
||||
system.cpu.cpi 0.439684 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.439684 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 19603173 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 4020.633151 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2686.323277 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 19458721 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 580788500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.007369 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 144452 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 82734 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 165794500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003148 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 61718 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 9707.501078 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9477.511675 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 13569879 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 10129757960 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.071407 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1043498 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 900030 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1359719645 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009818 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 143468 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs 3321.963636 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets 3975 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 161.320715 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 110 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 365416 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 3975 # number of cycles access was blocked
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 2642.114676 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3379.334983 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 13777457 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 2208596500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.057202 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 835920 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 692465 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 484782500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009817 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 143455 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 161.990993 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 34282993 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 9019.034891 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 7604.096607 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 33081555 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 10835811241 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.035045 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1201438 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 996371 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 1559349279 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.005982 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 205067 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 34216550 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 2845.231198 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 3170.870436 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 33236178 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 2789385000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.028652 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 980372 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 775199 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 650577000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.005996 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 205173 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 34282993 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 9019.034891 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 7604.096607 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_accesses 34216550 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 2845.231198 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 3170.870436 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 33081555 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 10835811241 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.035045 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1201438 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 996371 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 1559349279 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.005982 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 205067 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 33236178 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 2789385000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.028652 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 980372 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 775199 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 650577000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.005996 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 205173 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 200971 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 205067 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 201077 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 205173 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4063.517542 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 33081555 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 17025000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 147753 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 13116101 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 95141 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 3521692 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 99189601 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 29616630 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 18020228 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 1276894 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 291919 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 340231 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 15617287 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 13002150 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 31529148 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 124397 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 100725428 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 547316 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.250397 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 13002150 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 9796371 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.614964 # Number of inst fetches per cycle
|
||||
system.cpu.dcache.tagsinuse 4079.993551 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 33236178 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 90338000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 147781 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 1516721 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 98391 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 3463978 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 98144908 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 14320248 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 17547399 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 999107 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 287801 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 611733 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 15489897 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 12778073 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 31147667 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 14471 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 99913909 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 465674 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.442629 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 12778073 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 9588841 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.855074 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 62370084
|
||||
system.cpu.fetch.rateDist.samples 34995208
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 43843090 7029.51%
|
||||
1 1383259 221.78%
|
||||
2 1262238 202.38%
|
||||
3 1426265 228.68%
|
||||
4 3918105 628.20%
|
||||
5 1724208 276.45%
|
||||
6 613107 98.30%
|
||||
7 1031700 165.42%
|
||||
8 7168112 1149.29%
|
||||
0 16625619 4750.83%
|
||||
1 1365816 390.29%
|
||||
2 1258616 359.65%
|
||||
3 1410956 403.19%
|
||||
4 3900976 1114.72%
|
||||
5 1678758 479.71%
|
||||
6 612174 174.93%
|
||||
7 1011089 288.92%
|
||||
8 7131204 2037.77%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 13002150 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3387.778909 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2412.580892 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 12899943 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 346254719 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.007861 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 102207 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 14535 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 211515792 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.006743 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 87672 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_accesses 12778073 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 2888.242687 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 1894.538715 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 12690553 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 252779000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.006849 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 87520 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 654 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 164571000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.006798 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 86866 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets 5804 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 147.140366 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 146.093443 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 1 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 5804 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 13002150 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 3387.778909 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2412.580892 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 12899943 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 346254719 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.007861 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 102207 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 14535 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 211515792 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.006743 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 87672 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 12778073 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 2888.242687 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 1894.538715 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 12690553 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 252779000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.006849 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 87520 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 654 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 164571000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.006798 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 86866 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 13002150 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 3387.778909 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2412.580892 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 12778073 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 2888.242687 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 1894.538715 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 12899943 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 346254719 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.007861 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 102207 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 14535 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 211515792 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.006743 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 87672 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 12690553 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 252779000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.006849 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 87520 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 654 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 164571000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.006798 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 86866 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -215,80 +215,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 85624 # number of replacements
|
||||
system.cpu.icache.sampled_refs 87671 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 84818 # number of replacements
|
||||
system.cpu.icache.sampled_refs 86866 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1862.743229 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 12899943 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tagsinuse 1921.828467 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 12690553 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 15230287000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 851621931 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 14377755 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 9220461 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.335296 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 36382036 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 15204952 # Number of stores executed
|
||||
system.cpu.idleCycles 6484 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 14304724 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 9152219 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 2.363053 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 36160680 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 15116998 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 46748099 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 82847738 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.736514 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 43283574 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 82548148 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.757836 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 34430613 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.328325 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 82914162 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 396555 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 4917376 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 22199501 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 4762 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 311974 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 16236124 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 96553237 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 21177084 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 433562 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 83282498 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 37202 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 32801872 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 2.358841 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 82621578 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 398195 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 20355 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 21780362 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 4681 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 352010 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 15866784 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 94903979 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 21043682 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 752566 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 82695525 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 5889 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 11594 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 1276894 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 204710 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 132 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 999107 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 7135 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 98563 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 1300046 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 1230 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 1325562 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 2239 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 27684 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1255 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 1820102 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 1391505 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 27684 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 103251 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 293304 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.087081 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.087081 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 83716060 # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 16849 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1491 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 1400963 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 1022165 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 16849 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 105190 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 293005 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 2.274362 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 2.274362 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 83448091 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
(null) 0 0.00% # Type of FU issued
|
||||
IntAlu 46816661 55.92% # Type of FU issued
|
||||
IntMult 44502 0.05% # Type of FU issued
|
||||
IntAlu 46687810 55.95% # Type of FU issued
|
||||
IntMult 45238 0.05% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 125345 0.15% # Type of FU issued
|
||||
FloatCmp 86 0.00% # Type of FU issued
|
||||
FloatCvt 122997 0.15% # Type of FU issued
|
||||
FloatMult 51 0.00% # Type of FU issued
|
||||
FloatDiv 37854 0.05% # Type of FU issued
|
||||
FloatAdd 120004 0.14% # Type of FU issued
|
||||
FloatCmp 87 0.00% # Type of FU issued
|
||||
FloatCvt 122290 0.15% # Type of FU issued
|
||||
FloatMult 50 0.00% # Type of FU issued
|
||||
FloatDiv 37770 0.05% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 21285503 25.43% # Type of FU issued
|
||||
MemWrite 15283061 18.26% # Type of FU issued
|
||||
MemRead 21206489 25.41% # Type of FU issued
|
||||
MemWrite 15228353 18.25% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 1123822 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.013424 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 1422206 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.017043 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
(null) 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 98385 8.75% # attempts to use FU when none available
|
||||
IntAlu 169452 11.91% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 0 0.00% # attempts to use FU when none available
|
||||
|
|
@ -297,84 +297,84 @@ system.cpu.iq.ISSUE:fu_full.start_dist
|
|||
FloatMult 0 0.00% # attempts to use FU when none available
|
||||
FloatDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 476117 42.37% # attempts to use FU when none available
|
||||
MemWrite 549320 48.88% # attempts to use FU when none available
|
||||
MemRead 649726 45.68% # attempts to use FU when none available
|
||||
MemWrite 603028 42.40% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 62370084
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 34995208
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 25315225 4058.87%
|
||||
1 13800975 2212.76%
|
||||
2 10743054 1722.47%
|
||||
3 5596398 897.29%
|
||||
4 4388925 703.69%
|
||||
5 1495414 239.76%
|
||||
6 664039 106.47%
|
||||
7 305653 49.01%
|
||||
8 60401 9.68%
|
||||
0 5876071 1679.11%
|
||||
1 8518834 2434.29%
|
||||
2 6419045 1834.26%
|
||||
3 4436708 1267.80%
|
||||
4 4423684 1264.08%
|
||||
5 2554091 729.84%
|
||||
6 1512126 432.10%
|
||||
7 794096 226.92%
|
||||
8 460553 131.60%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 1.342247 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 87328014 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 83716060 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 4762 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 7507881 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 113500 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 179 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 6033024 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadReq_accesses 292729 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 7766.621627 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2997.837795 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 123055 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1317793758 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.579628 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 169674 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 508655130 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.579628 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 169674 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 147753 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 147285 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_miss_rate 0.003167 # miss rate for Writeback accesses
|
||||
system.cpu.l2cache.Writeback_misses 468 # number of Writeback misses
|
||||
system.cpu.l2cache.Writeback_mshr_miss_rate 0.003167 # mshr miss rate for Writeback accesses
|
||||
system.cpu.l2cache.Writeback_mshr_misses 468 # number of Writeback MSHR misses
|
||||
system.cpu.iq.ISSUE:rate 2.384558 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 85747079 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 83448091 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 4681 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 5951026 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 23998 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 98 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 4012087 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadReq_accesses 291992 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 3325.548649 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1922.235296 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 122257 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 564462000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.581300 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 169735 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 326270608 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.581300 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 169735 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 147781 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 147317 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_miss_rate 0.003140 # miss rate for Writeback accesses
|
||||
system.cpu.l2cache.Writeback_misses 464 # number of Writeback misses
|
||||
system.cpu.l2cache.Writeback_mshr_miss_rate 0.003140 # mshr miss rate for Writeback accesses
|
||||
system.cpu.l2cache.Writeback_mshr_misses 464 # number of Writeback MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 1.593300 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 1.588205 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 292729 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 7766.621627 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2997.837795 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 123055 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 1317793758 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.579628 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 169674 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 291992 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 3325.548649 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1922.235296 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 122257 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 564462000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.581300 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 169735 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 508655130 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.579628 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 169674 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 326270608 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.581300 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 169735 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 440482 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 7745.258419 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2997.837795 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_accesses 439773 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 3316.482471 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1922.235296 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 270340 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 1317793758 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.386263 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 170142 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 269574 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 564462000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.387016 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 170199 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 508655130 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.385201 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 169674 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 326270608 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.385960 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 169735 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -386,32 +386,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 136905 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 169673 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 136967 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 169735 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 30821.723437 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 270340 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 468003000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 115935 # number of writebacks
|
||||
system.cpu.numCycles 62370084 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 8787185 # Number of cycles rename is blocking
|
||||
system.cpu.l2cache.tagsinuse 32064.700481 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 269574 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 8508988000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 115938 # number of writebacks
|
||||
system.cpu.numCycles 34995208 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 201241 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 113083 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 30263464 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 3026568 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 587 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 118807787 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 98380136 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 59048113 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 17777635 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 1276894 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 3354217 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 6501232 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 910689 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 4741 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 5955323 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 4739 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 280733 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:IQFullEvents 31178 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 14721876 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 1110145 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 117085470 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 96973574 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 58152082 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 17754494 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 999107 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 1242602 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 5605201 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 75888 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 4701 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 2792735 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 4699 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 16 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -134,7 +134,7 @@
|
|||
DB Handle Chunk's StackPtr = 20797
|
||||
|
||||
DB[ 1] LOADED; Handles= 20797
|
||||
KERNEL in CORE[ 1] Restored @ 40054800
|
||||
KERNEL in CORE[ 1] Restored @ 4005c800
|
||||
|
||||
OPEN File ./input/lendian.wnv
|
||||
*Status = 0
|
||||
|
|
|
|||
|
|
@ -1,33 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
checkpoint=
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
dir=cpt.%012d
|
||||
period=0
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
|
||||
ignore_events=
|
||||
mysql_db=
|
||||
mysql_host=
|
||||
mysql_password=
|
||||
mysql_user=
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_compat=true
|
||||
text_file=m5stats.txt
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -38,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
@ -59,11 +33,11 @@ icache_port=system.membus.port[1]
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=vortex lendian.raw
|
||||
cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-atomic
|
||||
cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
euid=100
|
||||
executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
output=cout
|
||||
|
|
|
|||
|
|
@ -1,9 +1,6 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
dummy=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -27,11 +24,11 @@ responder_set=false
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=vortex lendian.raw
|
||||
executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-atomic
|
||||
cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
|
|
@ -50,7 +47,7 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
width=1
|
||||
|
|
@ -58,23 +55,3 @@ function_trace=false
|
|||
function_trace_start=0
|
||||
simulate_stalls=false
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1347543 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 179988 # Number of bytes of host memory used
|
||||
host_seconds 65.56 # Real time elapsed on the host
|
||||
host_tick_rate 1347535 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 842354 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 152996 # Number of bytes of host memory used
|
||||
host_seconds 104.87 # Real time elapsed on the host
|
||||
host_tick_rate 421175511 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 88340674 # Number of instructions simulated
|
||||
sim_seconds 0.000088 # Number of seconds simulated
|
||||
sim_ticks 88340673 # Number of ticks simulated
|
||||
sim_seconds 0.044170 # Number of seconds simulated
|
||||
sim_ticks 44170336500 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 88340674 # number of cpu cycles simulated
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -1,33 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
checkpoint=
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
dir=cpt.%012d
|
||||
period=0
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
|
||||
ignore_events=
|
||||
mysql_db=
|
||||
mysql_host=
|
||||
mysql_password=
|
||||
mysql_user=
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_compat=true
|
||||
text_file=m5stats.txt
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -38,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache icache l2cache toL2Bus workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
@ -182,11 +156,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=vortex lendian.raw
|
||||
cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing
|
||||
cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
euid=100
|
||||
executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
output=cout
|
||||
|
|
|
|||
|
|
@ -1,9 +1,6 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
dummy=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -27,11 +24,11 @@ responder_set=false
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=vortex lendian.raw
|
||||
executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing
|
||||
cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
|
|
@ -50,7 +47,7 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
// width not specified
|
||||
|
|
@ -179,23 +176,3 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,35 +1,35 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 704446 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 275648 # Number of bytes of host memory used
|
||||
host_seconds 125.40 # Real time elapsed on the host
|
||||
host_tick_rate 9716991 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 562157 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 158620 # Number of bytes of host memory used
|
||||
host_seconds 157.15 # Real time elapsed on the host
|
||||
host_tick_rate 396922606 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 88340674 # Number of instructions simulated
|
||||
sim_seconds 0.001219 # Number of seconds simulated
|
||||
sim_ticks 1218558003 # Number of ticks simulated
|
||||
sim_seconds 0.062375 # Number of seconds simulated
|
||||
sim_ticks 62374966500 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3613.021476 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2613.021476 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3130.058422 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2130.058422 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 219545250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 190198000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 158780250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 129433000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 4540.238491 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3540.238491 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3436.431765 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2436.431765 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 651878362 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 493396000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 508300362 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 349818000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 169.742404 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 4264.514136 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 3345.326241 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2345.326241 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 34685672 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 871423612 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 683594000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 204343 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 667080612 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 479251000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 204343 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 4264.514136 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 3345.326241 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2345.326241 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 34685672 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 871423612 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 683594000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 204343 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 667080612 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 479251000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 204343 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,22 +76,22 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 200247 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4056.438323 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4082.118898 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 28900000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.warmup_cycle 307192000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 147714 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 88340675 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 2932.969818 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 1932.969818 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 2831.355644 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 1831.355644 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 88264239 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 224184481 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 216417500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000865 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 147748481 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 139981500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000865 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 1154.746965 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
|
|
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 88340675 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 2932.969818 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 2831.355644 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 1831.355644 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 88264239 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 224184481 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 216417500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000865 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 147748481 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 139981500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000865 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 88340675 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 2932.969818 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_miss_latency 2831.355644 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 1831.355644 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 88264239 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 224184481 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 216417500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000865 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 76436 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 147748481 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 139981500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000865 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 74391 # number of replacements
|
||||
system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1796.106842 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1880.010701 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 88264239 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 280779 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 3650.218185 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1972.851350 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2532.769537 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1531.091909 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 112101 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 615711503 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 427222500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.600750 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 168678 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 332776620 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 258261521 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.600750 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 168678 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses)
|
||||
|
|
@ -159,8 +159,8 @@ system.cpu.l2cache.Writeback_miss_rate 0.002965 # mi
|
|||
system.cpu.l2cache.Writeback_misses 438 # number of Writeback misses
|
||||
system.cpu.l2cache.Writeback_mshr_miss_rate 0.002965 # mshr miss rate for Writeback accesses
|
||||
system.cpu.l2cache.Writeback_mshr_misses 438 # number of Writeback MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 1.537705 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
|
|
@ -168,29 +168,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 3650.218185 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2532.769537 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1531.091909 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 112101 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 615711503 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 427222500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.600750 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 168678 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 332776620 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 258261521 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.600750 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 168678 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 428493 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 3640.764345 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2526.209820 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1531.091909 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 259377 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 615711503 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 427222500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.394676 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 169116 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 332776620 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 258261521 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.393654 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 168678 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -207,12 +207,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 135910 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 168678 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 30401.731729 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 32002.173981 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 259377 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 667816000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.warmup_cycle 30452104000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 115911 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1218558003 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 62374966500 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 88340674 # Number of instructions executed
|
||||
system.cpu.num_refs 35224019 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ activity=0
|
|||
backComSize=5
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
clock=1
|
||||
clock=500
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
|
|||
|
|
@ -167,7 +167,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
numThreads=1
|
||||
cpu_id=0
|
||||
|
|
|
|||
|
|
@ -1,40 +1,40 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 929108954 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 938262248 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 21205625 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 887467305 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 962390884 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 21400461 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 41899 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 150980 # Number of bytes of host memory used
|
||||
host_seconds 41434.26 # Real time elapsed on the host
|
||||
host_tick_rate 599461 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 138710917 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 68670490 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 815007661 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 388931456 # Number of stores inserted to the mem dependence unit.
|
||||
global.BPredUnit.BTBHits 264221270 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 273071573 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 122 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 19541079 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 228439261 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 295748685 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 20371548 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 108663 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 154628 # Number of bytes of host memory used
|
||||
host_seconds 15976.47 # Real time elapsed on the host
|
||||
host_tick_rate 25821276 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 80477635 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 37646176 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 533254174 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 186471924 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1736043781 # Number of instructions simulated
|
||||
sim_seconds 0.024838 # Number of seconds simulated
|
||||
sim_ticks 24838210102 # Number of ticks simulated
|
||||
sim_seconds 0.412533 # Number of seconds simulated
|
||||
sim_ticks 412532848500 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 214632552 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 66487461 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 78248119 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 7112101736
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 772086758
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 6522703166 9171.27%
|
||||
1 208562151 293.25%
|
||||
2 123042509 173.00%
|
||||
3 62023833 87.21%
|
||||
4 51435586 72.32%
|
||||
5 40600313 57.09%
|
||||
6 22309158 31.37%
|
||||
7 14937559 21.00%
|
||||
8 66487461 93.48%
|
||||
0 242551958 3141.51%
|
||||
1 161050324 2085.91%
|
||||
2 101638189 1316.41%
|
||||
3 63812257 826.49%
|
||||
4 43982002 569.65%
|
||||
5 37612088 487.15%
|
||||
6 28299494 366.53%
|
||||
7 14892327 192.88%
|
||||
8 78248119 1013.46%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
|
|
@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 445666361 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 606571343 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 21205131 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 19540581 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 2701603860 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 358953852 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
|
||||
system.cpu.cpi 14.307364 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 14.307364 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 489384352 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 5253.286413 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5452.839977 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 474368420 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 78882991559 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.030683 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 15015932 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 7713263 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 39820285465 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.014922 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 7302669 # number of ReadReq MSHR misses
|
||||
system.cpu.cpi 0.475256 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.475256 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 463286594 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3710.591477 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2550.415742 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 454594407 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 32253155000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.018762 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 8692187 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 1395111 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 18610577500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.015751 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 7297076 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 8690.039906 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 14121.575874 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 155407108 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 46243126214 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.033108 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 5321394 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 3438755 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 26585829481 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011713 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1882639 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs 985.727671 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets 3841.099983 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 68.563354 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 637482 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 65141 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 628383647 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 250213094 # number of cycles access was blocked
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 6275.157749 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 8072.319138 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 157494886 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 20291450500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.020118 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 3233616 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 1350145 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 15203979000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011718 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1883471 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs 1064.957356 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets 500 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 66.672421 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 75157 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 5468 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 80039000 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 2734000 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 650112854 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 6152.535381 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 7229.601331 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 629775528 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 125126117773 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.031283 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 20337326 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 11152018 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 66406114946 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.014129 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 9185308 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 624015096 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 4405.959540 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 3683.283414 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 612089293 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 52544605500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.019111 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 11925803 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 2745256 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 33814556500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.014712 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 9180547 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 650112854 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 6152.535381 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 7229.601331 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_accesses 624015096 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 4405.959540 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 3683.283414 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 629775528 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 125126117773 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.031283 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 20337326 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 11152018 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 66406114946 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.014129 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 9185308 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 612089293 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 52544605500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.019111 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 11925803 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 2745256 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 33814556500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.014712 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 9180547 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 9181212 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 9185308 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 9176451 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 9180547 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4093.052798 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 629775528 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 39780000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 2244995 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 5295615421 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 511 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 51642597 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 5750899999 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 834310560 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 972356636 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 417727902 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 1635 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 9819120 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 962390884 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 341574441 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 1454523625 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 5354005 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 6616091478 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 145044249 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.127810 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 341574441 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 950509415 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.878651 # Number of inst fetches per cycle
|
||||
system.cpu.dcache.tagsinuse 4083.178096 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 612089293 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 4996762000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 2245686 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 22551440 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 546 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 44940582 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 2380682647 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 322635695 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 423064703 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 52978940 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 1700 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 3834921 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 295748685 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 302488728 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 741391553 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 441 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 2447585283 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 20057035 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.358455 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 302488728 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 284592818 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.966534 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 7529829639
|
||||
system.cpu.fetch.rateDist.samples 825065699
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 6416880458 8521.95%
|
||||
1 35027129 46.52%
|
||||
2 21417088 28.44%
|
||||
3 34363919 45.64%
|
||||
4 372287950 494.42%
|
||||
5 53476407 71.02%
|
||||
6 32781145 43.54%
|
||||
7 26846633 35.65%
|
||||
8 536748910 712.83%
|
||||
0 386162878 4680.39%
|
||||
1 30694739 372.03%
|
||||
2 18778429 227.60%
|
||||
3 29987039 363.45%
|
||||
4 87656406 1062.42%
|
||||
5 50975460 617.84%
|
||||
6 28097158 340.54%
|
||||
7 26422023 320.24%
|
||||
8 166291567 2015.49%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 341574441 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 5436.849282 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4708.305648 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 341573187 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 6817809 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 1254 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 351 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 4251600 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 302488728 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 4286.486486 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3340.579710 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 302487803 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 3965000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 925 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 28 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 2996500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 903 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses 897 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets 4779 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 378264.880399 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 337221.630992 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 1 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 4779 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 341574441 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 5436.849282 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 4708.305648 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 341573187 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 6817809 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 1254 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 351 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 4251600 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_accesses 302488728 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 4286.486486 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 3340.579710 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 302487803 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 3965000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 925 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 28 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 2996500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 903 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 897 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 341574441 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 5436.849282 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 4708.305648 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 302488728 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 4286.486486 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 3340.579710 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 341573187 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 6817809 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 1254 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 351 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 4251600 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_hits 302487803 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 3965000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 925 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 28 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 2996500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 903 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 897 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -216,79 +216,79 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 1 # number of replacements
|
||||
system.cpu.icache.sampled_refs 903 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 897 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 719.119159 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 341573187 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 700.392428 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 302487803 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 17308380464 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 264199071 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 130726584 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.347587 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 833351854 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 181613826 # Number of stores executed
|
||||
system.cpu.idleCycles 498 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 240658046 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 109011682 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 2.343638 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 670450767 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 171332493 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 1860973502 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 2467010272 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.791148 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 1329316260 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 1919496913 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.807674 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 1472305742 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.327632 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 2471732034 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 22834368 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 4630364405 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 815007661 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 46 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 31860417 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 388931456 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 4520549939 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 651738028 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 279876672 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 2617267318 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 2938028 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 1073654377 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 2.326478 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 1925768214 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 21262198 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 271227 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 533254174 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 16376681 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 186471924 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2178733969 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 499118274 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 42707495 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 1933655185 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 3473 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 161905 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 417727902 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 6385903 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 253 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 52978940 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 31539 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 122063096 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 39544757 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 151090 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 331862 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 34494542 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 128095 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 4644371 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 12 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 369341300 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 228026474 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 4644371 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 832035 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 22002333 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.069894 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.069894 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 2897143990 # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 361683 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 9 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 87587813 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 25566942 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 361683 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 691850 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 20570348 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 2.104128 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 2.104128 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 1976362680 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
(null) 0 0.00% # Type of FU issued
|
||||
IntAlu 1942173026 67.04% # Type of FU issued
|
||||
IntMult 100 0.00% # Type of FU issued
|
||||
IntAlu 1288510764 65.20% # Type of FU issued
|
||||
IntMult 78 0.00% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 210 0.00% # Type of FU issued
|
||||
FloatAdd 234 0.00% # Type of FU issued
|
||||
FloatCmp 15 0.00% # Type of FU issued
|
||||
FloatCvt 140 0.00% # Type of FU issued
|
||||
FloatMult 13 0.00% # Type of FU issued
|
||||
FloatCvt 154 0.00% # Type of FU issued
|
||||
FloatMult 14 0.00% # Type of FU issued
|
||||
FloatDiv 24 0.00% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 770673405 26.60% # Type of FU issued
|
||||
MemWrite 184297057 6.36% # Type of FU issued
|
||||
MemRead 513015840 25.96% # Type of FU issued
|
||||
MemWrite 174835557 8.85% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 12298143 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.004245 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 18092397 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.009154 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
(null) 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 765509 6.22% # attempts to use FU when none available
|
||||
IntAlu 2424231 13.40% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 0 0.00% # attempts to use FU when none available
|
||||
|
|
@ -297,84 +297,84 @@ system.cpu.iq.ISSUE:fu_full.start_dist
|
|||
FloatMult 0 0.00% # attempts to use FU when none available
|
||||
FloatDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 9714303 78.99% # attempts to use FU when none available
|
||||
MemWrite 1818331 14.79% # attempts to use FU when none available
|
||||
MemRead 11434785 63.20% # attempts to use FU when none available
|
||||
MemWrite 4233381 23.40% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 7529829639
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 825065699
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 6294390011 8359.27%
|
||||
1 325228389 431.92%
|
||||
2 480486573 638.11%
|
||||
3 243738023 323.70%
|
||||
4 97825007 129.92%
|
||||
5 51561666 68.48%
|
||||
6 27659179 36.73%
|
||||
7 6861374 9.11%
|
||||
8 2079417 2.76%
|
||||
0 201043450 2436.70%
|
||||
1 117715520 1426.74%
|
||||
2 151671107 1838.29%
|
||||
3 100094924 1213.18%
|
||||
4 99857816 1210.30%
|
||||
5 89528622 1085.11%
|
||||
6 51943929 629.57%
|
||||
7 9400422 113.94%
|
||||
8 3809909 46.18%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 0.384756 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 4389823309 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 2897143990 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 2623608231 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 10330579 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 2673985156 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadReq_accesses 9186210 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 7225.224344 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2102.004971 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 7015727 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 15682226609 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.236276 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 2170483 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 4562366056 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236276 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 2170483 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 2244995 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 2215762 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_miss_rate 0.013021 # miss rate for Writeback accesses
|
||||
system.cpu.l2cache.Writeback_misses 29233 # number of Writeback misses
|
||||
system.cpu.l2cache.Writeback_mshr_miss_rate 0.013021 # mshr miss rate for Writeback accesses
|
||||
system.cpu.l2cache.Writeback_mshr_misses 29233 # number of Writeback MSHR misses
|
||||
system.cpu.iq.ISSUE:rate 2.395400 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 2069722245 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 1976362680 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 42 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 325012863 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 1550012 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 175292310 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadReq_accesses 9181444 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 4578.076271 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1904.625556 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 7012219 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 9930877500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.236262 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 2169225 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 4131561371 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236262 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 2169225 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 2245686 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 2216531 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_miss_rate 0.012983 # miss rate for Writeback accesses
|
||||
system.cpu.l2cache.Writeback_misses 29155 # number of Writeback misses
|
||||
system.cpu.l2cache.Writeback_mshr_miss_rate 0.012983 # mshr miss rate for Writeback accesses
|
||||
system.cpu.l2cache.Writeback_mshr_misses 29155 # number of Writeback MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 4.253196 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.254400 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 9186210 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 7225.224344 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2102.004971 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 7015727 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 15682226609 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.236276 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 2170483 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 9181444 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 4578.076271 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1904.625556 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 7012219 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 9930877500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.236262 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 2169225 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 4562366056 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.236276 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 2170483 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 4131561371 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.236262 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 2169225 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 11431205 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 7129.205138 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2102.004971 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_accesses 11427130 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 4517.361648 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1904.625556 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 9231489 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 15682226609 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.192431 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 2199716 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 9228750 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 9930877500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.192383 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 2198380 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 4562366056 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.189874 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 2170483 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 4131561371 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.189831 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 2169225 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -386,32 +386,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 2137715 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 2170483 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 2136457 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 2169225 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 32622.966749 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 9231489 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 513093000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 1039675 # number of writebacks
|
||||
system.cpu.numCycles 7529829639 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 5035061268 # Number of cycles rename is blocking
|
||||
system.cpu.l2cache.tagsinuse 31578.699946 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 9228750 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 29958824000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 1039499 # number of writebacks
|
||||
system.cpu.numCycles 825065699 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 6100420 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 12523289 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 970889170 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 234469237 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 2022618 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 7453165021 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 5328451425 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 4004220538 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 843247999 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 417727902 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 262813407 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 2628017575 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 89893 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 51 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 1009480859 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 49 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 6494671 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:IQFullEvents 4850719 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 338099779 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 9291025 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 1319 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 2964381647 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 2307795213 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 1730632745 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 411108509 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 52978940 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 16777593 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 354429782 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 458 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 47 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 42678716 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 45 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,48 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
checkpoint=
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
print_data=true
|
||||
print_effaddr=true
|
||||
print_fetchseq=false
|
||||
print_iregs=false
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
speculative=true
|
||||
trace_system=client
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
dir=cpt.%012d
|
||||
period=0
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
|
||||
ignore_events=
|
||||
mysql_db=
|
||||
mysql_host=
|
||||
mysql_password=
|
||||
mysql_user=
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_compat=true
|
||||
text_file=m5stats.txt
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -53,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
@ -74,7 +33,7 @@ icache_port=system.membus.port[1]
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=bzip2 input.source 1
|
||||
cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-atomic
|
||||
cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
euid=100
|
||||
|
|
@ -100,14 +59,6 @@ type=PhysicalMemory
|
|||
file=
|
||||
latency=1
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
ignore=
|
||||
start=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,15 +1,13 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
dummy=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
range=[0,134217727]
|
||||
latency=1
|
||||
zero=false
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -30,7 +28,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
|
|||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-atomic
|
||||
cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
|
|
@ -49,7 +47,7 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
width=1
|
||||
|
|
@ -57,51 +55,3 @@ function_trace=false
|
|||
function_trace_start=0
|
||||
simulate_stalls=false
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
ignore=
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[random]
|
||||
seed=1
|
||||
|
||||
[exetrace]
|
||||
speculative=true
|
||||
print_cycle=true
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
print_effaddr=true
|
||||
print_data=true
|
||||
print_iregs=false
|
||||
print_fetchseq=false
|
||||
print_cpseq=false
|
||||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 927424 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 144704 # Number of bytes of host memory used
|
||||
host_seconds 1962.19 # Real time elapsed on the host
|
||||
host_tick_rate 927424 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 929031 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 148624 # Number of bytes of host memory used
|
||||
host_seconds 1958.79 # Real time elapsed on the host
|
||||
host_tick_rate 464515386 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1819780129 # Number of instructions simulated
|
||||
sim_seconds 0.001820 # Number of seconds simulated
|
||||
sim_ticks 1819780128 # Number of ticks simulated
|
||||
sim_seconds 0.909890 # Number of seconds simulated
|
||||
sim_ticks 909890064000 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1819780129 # number of cpu cycles simulated
|
||||
|
|
|
|||
|
|
@ -1 +1,3 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -1,48 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
checkpoint=
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
print_data=true
|
||||
print_effaddr=true
|
||||
print_fetchseq=false
|
||||
print_iregs=false
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
speculative=true
|
||||
trace_system=client
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
dir=cpt.%012d
|
||||
period=0
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
|
||||
ignore_events=
|
||||
mysql_db=
|
||||
mysql_host=
|
||||
mysql_password=
|
||||
mysql_user=
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_compat=true
|
||||
text_file=m5stats.txt
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -53,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache icache l2cache toL2Bus workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
@ -197,7 +156,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=bzip2 input.source 1
|
||||
cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing
|
||||
cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
euid=100
|
||||
|
|
@ -223,14 +182,6 @@ type=PhysicalMemory
|
|||
file=
|
||||
latency=1
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
ignore=
|
||||
start=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,15 +1,13 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
dummy=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
range=[0,134217727]
|
||||
latency=1
|
||||
zero=false
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -30,7 +28,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
|
|||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing
|
||||
cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
|
|
@ -49,7 +47,7 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
// width not specified
|
||||
|
|
@ -178,51 +176,3 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
ignore=
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[random]
|
||||
seed=1
|
||||
|
||||
[exetrace]
|
||||
speculative=true
|
||||
print_cycle=true
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
print_effaddr=true
|
||||
print_data=true
|
||||
print_iregs=false
|
||||
print_fetchseq=false
|
||||
print_cpseq=false
|
||||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 486900 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 1198232 # Number of bytes of host memory used
|
||||
host_seconds 3737.50 # Real time elapsed on the host
|
||||
host_tick_rate 8500130 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 623968 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 154076 # Number of bytes of host memory used
|
||||
host_seconds 2916.46 # Real time elapsed on the host
|
||||
host_tick_rate 423514548 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1819780129 # Number of instructions simulated
|
||||
sim_seconds 0.031769 # Number of seconds simulated
|
||||
sim_ticks 31769223012 # Number of ticks simulated
|
||||
sim_seconds 1.235165 # Number of seconds simulated
|
||||
sim_ticks 1235165291000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3121.340330 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2121.340330 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 2978.629098 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1978.629098 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 22543612099 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 21512892500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 15321198099 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 14290478500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3602.533807 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2602.533807 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 2992.340366 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 1992.340366 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 158839182 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 6806339173 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 5653488500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.011755 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1889320 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 4917019173 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 3764168500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3221.115901 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2221.115901 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 2981.472133 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 1981.472133 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 596212431 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 29349951272 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 27166381000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.015053 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 9111734 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 20238217272 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 18054647000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 9111734 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3221.115901 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2221.115901 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 2981.472133 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 1981.472133 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 596212431 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 29349951272 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 27166381000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.015053 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 9111734 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 20238217272 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 18054647000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 9111734 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 9107638 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4091.845274 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4078.615858 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 75264000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.warmup_cycle 20287970000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 2244708 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 1819780130 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 4089.753117 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3089.753117 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3779.301746 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2779.301746 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1819779328 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 3279982 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 3031000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 2477982 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 2229000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 1819780130 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 4089.753117 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 3089.753117 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 3779.301746 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2779.301746 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1819779328 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 3279982 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 3031000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 802 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 2477982 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 2229000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 1819780130 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 4089.753117 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 3089.753117 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 3779.301746 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2779.301746 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 1819779328 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 3279982 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 3031000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 802 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 2477982 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 2229000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -138,27 +138,27 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 1 # number of replacements
|
||||
system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 625.996248 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 611.013893 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1819779328 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 9112536 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 3215.890455 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1919.394872 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2722.045846 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1719.036352 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 6952383 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 6946815413 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 5880035500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.237053 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 2160153 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 4146186590 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 3713381532 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.237053 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 2160153 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 2244708 # number of WriteReqNoAck|Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.WriteReqNoAck|Writeback_hits 2215611 # number of WriteReqNoAck|Writeback hits
|
||||
system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.012962 # miss rate for WriteReqNoAck|Writeback accesses
|
||||
system.cpu.l2cache.WriteReqNoAck|Writeback_misses 29097 # number of WriteReqNoAck|Writeback misses
|
||||
system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.012962 # mshr miss rate for WriteReqNoAck|Writeback accesses
|
||||
system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 29097 # number of WriteReqNoAck|Writeback MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 2244708 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 2215611 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_miss_rate 0.012962 # miss rate for Writeback accesses
|
||||
system.cpu.l2cache.Writeback_misses 29097 # number of Writeback misses
|
||||
system.cpu.l2cache.Writeback_mshr_miss_rate 0.012962 # mshr miss rate for Writeback accesses
|
||||
system.cpu.l2cache.Writeback_mshr_misses 29097 # number of Writeback MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 4.244141 # Average number of references to valid blocks.
|
||||
|
|
@ -168,29 +168,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 3215.890455 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1919.394872 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2722.045846 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1719.036352 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 6952383 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 6946815413 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 5880035500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.237053 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 2160153 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 4146186590 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 3713381532 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.237053 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 2160153 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 11357244 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 3173.148527 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1919.394872 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2685.867535 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1719.036352 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 9167994 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 6946815413 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 5880035500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.192762 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 2189250 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 4146186590 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 3713381532 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.190200 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 2160153 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -207,12 +207,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 2127385 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 2160153 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 32563.117941 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 31158.106837 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 9167994 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 748591000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.warmup_cycle 122436614000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 1038202 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 31769223012 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1235165291000 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 1819780129 # Number of instructions executed
|
||||
system.cpu.num_refs 606571345 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1 +1,3 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ activity=0
|
|||
backComSize=5
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
clock=1
|
||||
clock=500
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
|
|||
|
|
@ -167,7 +167,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
numThreads=1
|
||||
cpu_id=0
|
||||
|
|
|
|||
|
|
@ -1,40 +1,40 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 13130842 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 17054746 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 1205 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 1949700 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 14620230 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 19607486 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 1766776 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 70212 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 153248 # Number of bytes of host memory used
|
||||
host_seconds 1198.94 # Real time elapsed on the host
|
||||
host_tick_rate 95357 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 19046664 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 5327434 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 34568849 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 10915344 # Number of stores inserted to the mem dependence unit.
|
||||
global.BPredUnit.BTBHits 14247678 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 18312009 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 1187 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 1953985 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 15742663 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 20998495 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 1857732 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 58248 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 156992 # Number of bytes of host memory used
|
||||
host_seconds 1445.19 # Real time elapsed on the host
|
||||
host_tick_rate 23712867 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 20592604 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 6080799 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 35412339 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 11200166 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 84179709 # Number of instructions simulated
|
||||
sim_seconds 0.000114 # Number of seconds simulated
|
||||
sim_ticks 114327081 # Number of ticks simulated
|
||||
sim_seconds 0.034270 # Number of seconds simulated
|
||||
sim_ticks 34269677000 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 10240685 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 2895131 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 3363462 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 73926385
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 59572652
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 37511035 5074.11%
|
||||
1 16507127 2232.91%
|
||||
2 8529257 1153.75%
|
||||
3 3749717 507.22%
|
||||
4 1879220 254.20%
|
||||
5 1361115 184.12%
|
||||
6 851721 115.21%
|
||||
7 642062 86.85%
|
||||
8 2895131 391.62%
|
||||
0 25280039 4243.56%
|
||||
1 15284536 2565.70%
|
||||
2 7326530 1229.85%
|
||||
3 3334393 559.72%
|
||||
4 2152142 361.26%
|
||||
5 1242273 208.53%
|
||||
6 890288 149.45%
|
||||
7 698989 117.33%
|
||||
8 3363462 564.60%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
|
|
@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 20034413 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 26537108 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 1937238 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 1941454 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 58539227 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 63250167 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
|
||||
system.cpu.cpi 1.358131 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 1.358131 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 23376895 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 5393.890593 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4863.252964 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 23375917 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 5275225 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000042 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 978 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 472 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2460806 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.cpi 0.814203 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.814203 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 23612894 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 4229.600000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3389.648438 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 23612269 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 2643500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000026 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 625 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 113 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1735500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 512 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 6579.789722 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6507.873418 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 6492638 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 55697920 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.001302 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 8465 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 6727 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 11310684 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3064.490759 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3618.087558 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 6493474 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 23379000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.001173 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 7629 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 5893 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 6281000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1738 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs 2809.444444 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1736 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 13310.407754 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 9 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_refs 13392.234431 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 25285 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 29877998 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 6456.967595 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 6137.027629 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 29868555 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 60973145 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000316 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 9443 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 7199 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 13771490 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_accesses 30113997 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3152.713836 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 3566.058719 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 30105743 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 26022500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000274 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 8254 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 6006 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 8016500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 2244 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 2248 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 29877998 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 6456.967595 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 6137.027629 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_accesses 30113997 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3152.713836 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 3566.058719 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 29868555 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 60973145 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000316 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 9443 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 7199 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 13771490 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_hits 30105743 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 26022500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000274 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 8254 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 6006 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 8016500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 2244 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 2248 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 160 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 2244 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 162 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 2248 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 1415.957077 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 29868555 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 1463.572116 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 30105743 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 106 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 5155486 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 12562 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 3109369 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 165294506 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 40322652 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 28299602 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 8350763 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 41264 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 148646 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 19607486 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 19380281 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 48705122 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 491925 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 170506876 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 2058666 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.238310 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 19380281 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 14897618 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.072348 # Number of inst fetches per cycle
|
||||
system.cpu.decode.DECODE:BlockedCycles 6099480 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 13208 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 3247204 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 173741531 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 23444029 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 28861256 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 8966698 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 40444 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 1167888 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 20998495 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 20206829 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 51475298 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 3593 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 180749377 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 2035048 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.306371 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 20206829 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 16105410 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.637162 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 82277149
|
||||
system.cpu.fetch.rateDist.samples 68539351
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 52952312 6435.85%
|
||||
1 3129610 380.37%
|
||||
2 1369966 166.51%
|
||||
3 2017219 245.17%
|
||||
4 3854384 468.46%
|
||||
5 1357405 164.98%
|
||||
6 1550178 188.41%
|
||||
7 1288552 156.61%
|
||||
8 14757523 1793.64%
|
||||
0 37270886 5437.88%
|
||||
1 3420236 499.02%
|
||||
2 1457458 212.65%
|
||||
3 2151808 313.95%
|
||||
4 4198050 612.50%
|
||||
5 1495508 218.20%
|
||||
6 1665097 242.94%
|
||||
7 1343985 196.09%
|
||||
8 15536323 2266.77%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 19380281 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3416.377011 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2534.518183 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 19366483 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 47139170 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000712 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 13798 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 3761 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 25438959 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000518 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 10037 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_accesses 20206829 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3070.200019 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2096.460002 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 20196480 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 31773500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000512 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 10349 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 236 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 21201500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000500 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 10113 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 1929.509116 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1997.080985 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 19380281 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 3416.377011 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2534.518183 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 19366483 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 47139170 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000712 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 13798 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 3761 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 25438959 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000518 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 10037 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 20206829 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 3070.200019 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2096.460002 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 20196480 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 31773500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000512 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 10349 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 236 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 21201500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000500 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 10113 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 19380281 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 3416.377011 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2534.518183 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 20206829 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 3070.200019 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2096.460002 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 19366483 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 47139170 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000712 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 13798 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 3761 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 25438959 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000518 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 10037 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 20196480 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 31773500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000512 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 10349 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 236 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 21201500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000500 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 10113 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -215,162 +215,162 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 8123 # number of replacements
|
||||
system.cpu.icache.sampled_refs 10037 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 8192 # number of replacements
|
||||
system.cpu.icache.sampled_refs 10113 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1498.249784 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 19366483 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1564.702526 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 20196480 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 32049933 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 12923262 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 13162253 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.241494 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 31990682 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 7220394 # Number of stores executed
|
||||
system.cpu.idleCycles 2998 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 13347594 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 13508406 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.523954 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 32463851 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 7352116 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 91915926 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 100065162 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.718590 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 95064439 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 103132878 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.721353 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 66049838 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.216196 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 100916733 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 2084205 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 596692 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 34568849 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 437 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 864110 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 10915344 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 150440832 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 24770288 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 2226727 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 102146587 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 177017 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 68574976 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.504725 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 104172184 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 2117203 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 606505 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 35412339 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 444 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 632938 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 11200166 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 155150547 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 25111735 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 2600272 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 104450796 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 226857 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 827 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 8350763 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 211777 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 8966698 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 304686 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 3149 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 865223 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 1107 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 1001916 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 10875 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 167324 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 9618 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 14534436 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 4412649 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 167324 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 194984 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 1889221 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.736306 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.736306 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 104373314 # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 88969 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 9698 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 15377926 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 4697471 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 88969 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 207130 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 1910073 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.228195 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.228195 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 107051068 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
(null) 7 0.00% # Type of FU issued
|
||||
IntAlu 64752207 62.04% # Type of FU issued
|
||||
IntMult 471285 0.45% # Type of FU issued
|
||||
IntAlu 66598699 62.21% # Type of FU issued
|
||||
IntMult 478232 0.45% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 2789912 2.67% # Type of FU issued
|
||||
FloatCmp 115515 0.11% # Type of FU issued
|
||||
FloatCvt 2364267 2.27% # Type of FU issued
|
||||
FloatMult 305289 0.29% # Type of FU issued
|
||||
FloatDiv 755087 0.72% # Type of FU issued
|
||||
FloatAdd 2814666 2.63% # Type of FU issued
|
||||
FloatCmp 115604 0.11% # Type of FU issued
|
||||
FloatCvt 2391391 2.23% # Type of FU issued
|
||||
FloatMult 308778 0.29% # Type of FU issued
|
||||
FloatDiv 755076 0.71% # Type of FU issued
|
||||
FloatSqrt 324 0.00% # Type of FU issued
|
||||
MemRead 25418322 24.35% # Type of FU issued
|
||||
MemWrite 7401099 7.09% # Type of FU issued
|
||||
MemRead 26034990 24.32% # Type of FU issued
|
||||
MemWrite 7553301 7.06% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 1952486 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.018707 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 2233247 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.020862 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
(null) 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 163325 8.36% # attempts to use FU when none available
|
||||
IntAlu 352978 15.81% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 1017 0.05% # attempts to use FU when none available
|
||||
FloatCmp 0 0.00% # attempts to use FU when none available
|
||||
FloatCvt 12505 0.64% # attempts to use FU when none available
|
||||
FloatMult 2432 0.12% # attempts to use FU when none available
|
||||
FloatDiv 905685 46.39% # attempts to use FU when none available
|
||||
FloatAdd 856 0.04% # attempts to use FU when none available
|
||||
FloatCmp 8 0.00% # attempts to use FU when none available
|
||||
FloatCvt 3654 0.16% # attempts to use FU when none available
|
||||
FloatMult 2325 0.10% # attempts to use FU when none available
|
||||
FloatDiv 987087 44.20% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 774173 39.65% # attempts to use FU when none available
|
||||
MemWrite 93349 4.78% # attempts to use FU when none available
|
||||
MemRead 766963 34.34% # attempts to use FU when none available
|
||||
MemWrite 119376 5.35% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 82277149
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 68539351
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 35738506 4343.67%
|
||||
1 18264427 2219.87%
|
||||
2 12740961 1548.54%
|
||||
3 6961052 846.05%
|
||||
4 4806764 584.22%
|
||||
5 2441659 296.76%
|
||||
6 994924 120.92%
|
||||
7 291934 35.48%
|
||||
8 36922 4.49%
|
||||
0 25564605 3729.92%
|
||||
1 14833050 2164.17%
|
||||
2 10859904 1584.48%
|
||||
3 6945297 1013.33%
|
||||
4 5154135 752.00%
|
||||
5 2881350 420.39%
|
||||
6 1567848 228.75%
|
||||
7 633355 92.41%
|
||||
8 99807 14.56%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 1.268558 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 137278142 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 104373314 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 437 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 52505275 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 293840 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 48 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 49588547 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadReq_accesses 12278 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 4378.207161 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2293.937242 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 7195 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 22254427 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.413993 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 5083 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 11660083 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.413993 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 5083 # number of ReadReq MSHR misses
|
||||
system.cpu.iq.ISSUE:rate 1.561892 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 141641697 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 107051068 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 444 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 56891185 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 501220 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 55 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 52161048 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadReq_accesses 12360 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 3103.922717 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1864.884465 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 7236 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 15904500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.414563 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 5124 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 9555668 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.414563 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 5124 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 106 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 1.436356 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 1.432865 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 12278 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 4378.207161 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2293.937242 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 7195 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 22254427 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.413993 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 5083 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 12360 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 3103.922717 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1864.884465 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 7236 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 15904500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.414563 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 5124 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 11660083 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.413993 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 5083 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 9555668 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.414563 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 5124 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 12384 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 4378.207161 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2293.937242 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_accesses 12466 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 3103.922717 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1864.884465 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 7301 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 22254427 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.410449 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 5083 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 7342 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 15904500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.411038 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 5124 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 11660083 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.410449 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 5083 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 9555668 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.411038 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 5124 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -383,31 +383,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 5083 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 5124 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 3292.223620 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 7301 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 3431.784338 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 7342 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.numCycles 82277149 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 2387077 # Number of cycles rename is blocking
|
||||
system.cpu.numCycles 68539351 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 2079138 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 1473927 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 41553511 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 1059964 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 61 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 206590907 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 160246119 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 117849091 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 27232157 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 8350763 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 2654523 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 49421730 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 99118 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 461 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 5497153 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 451 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 10204 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:IQFullEvents 1661115 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 25239317 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 1954833 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 215732838 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 167129936 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 122925813 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 28288722 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 8966698 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 3960770 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 54498452 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 4706 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 484 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 9920797 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 473 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,33 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
checkpoint=
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
dir=cpt.%012d
|
||||
period=0
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
|
||||
ignore_events=
|
||||
mysql_db=
|
||||
mysql_host=
|
||||
mysql_password=
|
||||
mysql_user=
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_compat=true
|
||||
text_file=m5stats.txt
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -38,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
@ -59,7 +33,7 @@ icache_port=system.membus.port[1]
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=twolf smred
|
||||
cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-atomic
|
||||
cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
euid=100
|
||||
|
|
|
|||
|
|
@ -1,9 +1,6 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
dummy=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -31,7 +28,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
|
|||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-atomic
|
||||
cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
|
|
@ -50,7 +47,7 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
width=1
|
||||
|
|
@ -58,23 +55,3 @@ function_trace=false
|
|||
function_trace_start=0
|
||||
simulate_stalls=false
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1013473 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 151596 # Number of bytes of host memory used
|
||||
host_seconds 90.68 # Real time elapsed on the host
|
||||
host_tick_rate 1013469 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 754988 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 150624 # Number of bytes of host memory used
|
||||
host_seconds 121.73 # Real time elapsed on the host
|
||||
host_tick_rate 377492666 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 91903057 # Number of instructions simulated
|
||||
sim_seconds 0.000092 # Number of seconds simulated
|
||||
sim_ticks 91903056 # Number of ticks simulated
|
||||
sim_seconds 0.045952 # Number of seconds simulated
|
||||
sim_ticks 45951528000 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 91903057 # number of cpu cycles simulated
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ The rand generator seed was at utemp() : 1
|
|||
I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
|
||||
1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
|
||||
2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
|
||||
3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
|
||||
3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46
|
||||
4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
|
||||
5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
|
||||
6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
|
||||
|
|
@ -103,7 +103,7 @@ The rand generator seed was at utemp() : 1
|
|||
37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
|
||||
38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
|
||||
39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
|
||||
40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
|
||||
40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48
|
||||
41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
|
||||
42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
|
||||
43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -1,33 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
checkpoint=
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
dir=cpt.%012d
|
||||
period=0
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
|
||||
ignore_events=
|
||||
mysql_db=
|
||||
mysql_host=
|
||||
mysql_password=
|
||||
mysql_user=
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_compat=true
|
||||
text_file=m5stats.txt
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -38,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache icache l2cache toL2Bus workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
@ -182,7 +156,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=twolf smred
|
||||
cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-timing
|
||||
cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
euid=100
|
||||
|
|
|
|||
|
|
@ -1,9 +1,6 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
dummy=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -31,7 +28,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
|
|||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-timing
|
||||
cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
|
|
@ -50,7 +47,7 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
// width not specified
|
||||
|
|
@ -179,23 +176,3 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 607322 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 157212 # Number of bytes of host memory used
|
||||
host_seconds 151.33 # Real time elapsed on the host
|
||||
host_tick_rate 1013960 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 335846 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 156240 # Number of bytes of host memory used
|
||||
host_seconds 273.71 # Real time elapsed on the host
|
||||
host_tick_rate 216396349 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 91903057 # Number of instructions simulated
|
||||
sim_seconds 0.000153 # Number of seconds simulated
|
||||
sim_ticks 153438012 # Number of ticks simulated
|
||||
sim_seconds 0.059229 # Number of seconds simulated
|
||||
sim_ticks 59229023000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3701.356540 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2701.356540 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3629.746835 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2629.746835 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 19995724 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 1754443 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 1720500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 474 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1280443 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1246500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 474 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3869.070366 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2869.070366 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3602.116705 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2602.116705 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 6763135 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 6296500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5015135 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 4548500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3833.293429 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2833.293429 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 3608.010801 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2608.010801 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 26495079 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 8517578 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 8017000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2222 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 6295578 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 5795000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 2222 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3833.293429 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2833.293429 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 3608.010801 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2608.010801 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 26495079 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 8517578 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 8017000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2222 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 6295578 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 5795000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 2222 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 157 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 1398.130089 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 1441.710869 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 104 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 91903058 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3117.603760 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2117.603760 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3077.908343 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2077.908343 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 91894548 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 26530808 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 26193000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 18020808 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 17683000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 91903058 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 3117.603760 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2117.603760 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 3077.908343 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2077.908343 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 91894548 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 26530808 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 26193000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 18020808 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 17683000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 91903058 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 3117.603760 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2117.603760 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 3077.908343 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2077.908343 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 91894548 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 26530808 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 26193000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 8510 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 18020808 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 17683000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 6681 # number of replacements
|
||||
system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1374.520503 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1418.735069 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 91894548 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 10732 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2892.483207 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1885.503778 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2703.820319 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1702.820319 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 5968 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 13779790 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 12881000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.443906 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 4764 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 8982540 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 8112236 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.443906 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 4764 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses)
|
||||
|
|
@ -164,29 +164,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 10732 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2892.483207 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1885.503778 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2703.820319 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1702.820319 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 13779790 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 12881000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.443906 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 4764 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 8982540 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 8112236 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.443906 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 4764 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 10836 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2892.483207 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1885.503778 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2703.820319 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1702.820319 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 6072 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 13779790 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 12881000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.439646 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 4764 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 8982540 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 8112236 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.439646 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 4764 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -203,12 +203,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 4764 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 3073.845977 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 3173.029647 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 6072 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 153438012 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 59229023000 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 91903057 # Number of instructions executed
|
||||
system.cpu.num_refs 26537109 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ The rand generator seed was at utemp() : 1
|
|||
I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
|
||||
1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
|
||||
2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
|
||||
3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
|
||||
3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46
|
||||
4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
|
||||
5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
|
||||
6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
|
||||
|
|
@ -103,7 +103,7 @@ The rand generator seed was at utemp() : 1
|
|||
37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
|
||||
38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
|
||||
39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
|
||||
40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
|
||||
40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48
|
||||
41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
|
||||
42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
|
||||
43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
Loading…
Reference in a new issue