7f39291c81
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr:
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini:
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out:
tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout:
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini:
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out:
tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr:
tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr:
Update refs for clock changes.
--HG--
extra : convert_revision : 7c32a3362da60fd12b7bf9219842f707319cda42
417 lines
45 KiB
Text
417 lines
45 KiB
Text
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 264221270 # Number of BTB hits
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global.BPredUnit.BTBLookups 273071573 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 122 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 19541079 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 228439261 # Number of conditional branches predicted
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global.BPredUnit.lookups 295748685 # Number of BP lookups
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global.BPredUnit.usedRAS 20371548 # Number of times the RAS was used to get a target.
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host_inst_rate 108663 # Simulator instruction rate (inst/s)
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host_mem_usage 154628 # Number of bytes of host memory used
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host_seconds 15976.47 # Real time elapsed on the host
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host_tick_rate 25821276 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 80477635 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 37646176 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 533254174 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 186471924 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1736043781 # Number of instructions simulated
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sim_seconds 0.412533 # Number of seconds simulated
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sim_ticks 412532848500 # Number of ticks simulated
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system.cpu.commit.COM:branches 214632552 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 78248119 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 772086758
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 242551958 3141.51%
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1 161050324 2085.91%
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2 101638189 1316.41%
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3 63812257 826.49%
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4 43982002 569.65%
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5 37612088 487.15%
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6 28299494 366.53%
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7 14892327 192.88%
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8 78248119 1013.46%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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system.cpu.commit.COM:count 1819780126 # Number of instructions committed
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system.cpu.commit.COM:loads 445666361 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 606571343 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 19540581 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 358953852 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
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system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
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system.cpu.cpi 0.475256 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.475256 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 463286594 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 3710.591477 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2550.415742 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 454594407 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 32253155000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.018762 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 8692187 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 1395111 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 18610577500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.015751 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 7297076 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 6275.157749 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 8072.319138 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 157494886 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 20291450500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.020118 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 3233616 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1350145 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 15203979000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.011718 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 1883471 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs 1064.957356 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets 500 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 66.672421 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 75157 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 5468 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 80039000 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 2734000 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 624015096 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 4405.959540 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 3683.283414 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 612089293 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 52544605500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.019111 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 11925803 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 2745256 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 33814556500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.014712 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 9180547 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 624015096 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 4405.959540 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 3683.283414 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 612089293 # number of overall hits
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system.cpu.dcache.overall_miss_latency 52544605500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.019111 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 11925803 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 2745256 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 33814556500 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.014712 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 9180547 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 9176451 # number of replacements
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system.cpu.dcache.sampled_refs 9180547 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4083.178096 # Cycle average of tags in use
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system.cpu.dcache.total_refs 612089293 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 4996762000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 2245686 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 22551440 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 546 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 44940582 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 2380682647 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 322635695 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 423064703 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 52978940 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 1700 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 3834921 # Number of cycles decode is unblocking
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system.cpu.fetch.Branches 295748685 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 302488728 # Number of cache lines fetched
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system.cpu.fetch.Cycles 741391553 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 441 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 2447585283 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 20057035 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.358455 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 302488728 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 284592818 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 2.966534 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist.samples 825065699
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system.cpu.fetch.rateDist.min_value 0
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0 386162878 4680.39%
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1 30694739 372.03%
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2 18778429 227.60%
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3 29987039 363.45%
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4 87656406 1062.42%
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5 50975460 617.84%
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6 28097158 340.54%
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7 26422023 320.24%
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8 166291567 2015.49%
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system.cpu.fetch.rateDist.max_value 8
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system.cpu.fetch.rateDist.end_dist
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system.cpu.icache.ReadReq_accesses 302488728 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 4286.486486 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 3340.579710 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 302487803 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 3965000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 925 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 28 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 2996500 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 897 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 337221.630992 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 302488728 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 4286.486486 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 3340.579710 # average overall mshr miss latency
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system.cpu.icache.demand_hits 302487803 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 3965000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
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system.cpu.icache.demand_misses 925 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 28 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 2996500 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 897 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 302488728 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 4286.486486 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 3340.579710 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 302487803 # number of overall hits
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system.cpu.icache.overall_miss_latency 3965000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
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|
system.cpu.icache.overall_misses 925 # number of overall misses
|
|
system.cpu.icache.overall_mshr_hits 28 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_miss_latency 2996500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_misses 897 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu.icache.replacements 1 # number of replacements
|
|
system.cpu.icache.sampled_refs 897 # Sample count of references to valid blocks.
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.tagsinuse 700.392428 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 302487803 # Total number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
|
system.cpu.idleCycles 498 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.iew.EXEC:branches 240658046 # Number of branches executed
|
|
system.cpu.iew.EXEC:nop 109011682 # number of nop insts executed
|
|
system.cpu.iew.EXEC:rate 2.343638 # Inst execution rate
|
|
system.cpu.iew.EXEC:refs 670450767 # number of memory reference insts executed
|
|
system.cpu.iew.EXEC:stores 171332493 # Number of stores executed
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
|
system.cpu.iew.WB:consumers 1329316260 # num instructions consuming a value
|
|
system.cpu.iew.WB:count 1919496913 # cumulative count of insts written-back
|
|
system.cpu.iew.WB:fanout 0.807674 # average fanout of values written-back
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.WB:producers 1073654377 # num instructions producing a value
|
|
system.cpu.iew.WB:rate 2.326478 # insts written-back per cycle
|
|
system.cpu.iew.WB:sent 1925768214 # cumulative count of insts sent to commit
|
|
system.cpu.iew.branchMispredicts 21262198 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewBlockCycles 271227 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewDispLoadInsts 533254174 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewDispSquashedInsts 16376681 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispStoreInsts 186471924 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispatchedInsts 2178733969 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewExecLoadInsts 499118274 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 42707495 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.iewExecutedInsts 1933655185 # Number of executed instructions
|
|
system.cpu.iew.iewIQFullEvents 3473 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewLSQFullEvents 253 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.iewSquashCycles 52978940 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewUnblockCycles 31539 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 331862 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.0.forwLoads 34494542 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 128095 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 361683 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 9 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 87587813 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 25566942 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 361683 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 691850 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 20570348 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.ipc 2.104128 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 2.104128 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0 1976362680 # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|
(null) 0 0.00% # Type of FU issued
|
|
IntAlu 1288510764 65.20% # Type of FU issued
|
|
IntMult 78 0.00% # Type of FU issued
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
FloatAdd 234 0.00% # Type of FU issued
|
|
FloatCmp 15 0.00% # Type of FU issued
|
|
FloatCvt 154 0.00% # Type of FU issued
|
|
FloatMult 14 0.00% # Type of FU issued
|
|
FloatDiv 24 0.00% # Type of FU issued
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
MemRead 513015840 25.96% # Type of FU issued
|
|
MemWrite 174835557 8.85% # Type of FU issued
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 18092397 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.009154 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
(null) 0 0.00% # attempts to use FU when none available
|
|
IntAlu 2424231 13.40% # attempts to use FU when none available
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
|
MemRead 11434785 63.20% # attempts to use FU when none available
|
|
MemWrite 4233381 23.40% # attempts to use FU when none available
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 825065699
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
|
0 201043450 2436.70%
|
|
1 117715520 1426.74%
|
|
2 151671107 1838.29%
|
|
3 100094924 1213.18%
|
|
4 99857816 1210.30%
|
|
5 89528622 1085.11%
|
|
6 51943929 629.57%
|
|
7 9400422 113.94%
|
|
8 3809909 46.18%
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
system.cpu.iq.ISSUE:rate 2.395400 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 2069722245 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 1976362680 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 42 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 325012863 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 1550012 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 175292310 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.l2cache.ReadReq_accesses 9181444 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 4578.076271 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1904.625556 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits 7012219 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency 9930877500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.236262 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 2169225 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 4131561371 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236262 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 2169225 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.Writeback_accesses 2245686 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_hits 2216531 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_miss_rate 0.012983 # miss rate for Writeback accesses
|
|
system.cpu.l2cache.Writeback_misses 29155 # number of Writeback misses
|
|
system.cpu.l2cache.Writeback_mshr_miss_rate 0.012983 # mshr miss rate for Writeback accesses
|
|
system.cpu.l2cache.Writeback_mshr_misses 29155 # number of Writeback MSHR misses
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 4.254400 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 9181444 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency 4578.076271 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 1904.625556 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 7012219 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 9930877500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 0.236262 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 2169225 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 4131561371 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.236262 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 2169225 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.overall_accesses 11427130 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency 4517.361648 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 1904.625556 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 9228750 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 9930877500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 0.192383 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 2198380 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 4131561371 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.189831 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 2169225 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu.l2cache.replacements 2136457 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 2169225 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 31578.699946 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 9228750 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 29958824000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 1039499 # number of writebacks
|
|
system.cpu.numCycles 825065699 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:BlockCycles 6100420 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IQFullEvents 4850719 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.RENAME:IdleCycles 338099779 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 9291025 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:ROBFullEvents 1319 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.RENAME:RenameLookups 2964381647 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 2307795213 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 1730632745 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 411108509 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 52978940 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 16777593 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 354429782 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 458 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 47 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 42678716 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 45 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|