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gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt

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Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
sim_seconds 2.321351 # Number of seconds simulated
sim_ticks 2321351025500 # Number of ticks simulated
final_tick 2321351025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
host_inst_rate 818788 # Simulator instruction rate (inst/s)
host_op_rate 985991 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 31464875718 # Simulator tick rate (ticks/s)
host_mem_usage 430844 # Number of bytes of host memory used
host_seconds 73.78 # Real time elapsed on the host
sim_insts 60406834 # Number of instructions simulated
sim_ops 72742429 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.bytes_read::realview.clcd 110100480 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 705416 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9071832 # Number of bytes read from this memory
system.physmem.bytes_read::total 119878240 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 705416 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 705416 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3703872 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory
system.physmem.bytes_written::total 6719688 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 13762560 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 17234 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 141773 # Number of read requests responded to by this memory
system.physmem.num_reads::total 13921575 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57873 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory
system.physmem.num_writes::total 811827 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47429483 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 138 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 83 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 303882 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3907997 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51641582 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 303882 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 303882 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1595567 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1299164 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2894732 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1595567 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47429483 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 138 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 83 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 303882 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5207161 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54536314 # Total bandwidth to/from this memory (bytes/s)
stats: updates due to branch predictor warming
2014-02-16 18:40:34 +01:00
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.membus.throughput 55568847 # Throughput (bytes/s)
system.membus.data_through_bus 128994799 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iobus.throughput 48459111 # Throughput (bytes/s)
system.iobus.data_through_bus 112490607 # Total data (bytes)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dtb.read_hits 13142244 # DTB read hits
system.cpu.dtb.read_misses 7297 # DTB read misses
system.cpu.dtb.write_hits 11216207 # DTB write hits
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu.dtb.write_misses 2181 # DTB write misses
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dtb.flush_entries 3399 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dtb.read_accesses 13149541 # DTB read accesses
system.cpu.dtb.write_accesses 11218388 # DTB write accesses
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dtb.hits 24358451 # DTB hits
system.cpu.dtb.misses 9478 # DTB misses
system.cpu.dtb.accesses 24367929 # DTB accesses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.itb.inst_hits 61430007 # ITB inst hits
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.itb.inst_misses 4471 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.itb.flush_entries 2370 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.itb.inst_accesses 61434478 # ITB inst accesses
system.cpu.itb.hits 61430007 # DTB hits
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.itb.misses 4471 # DTB misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.itb.accesses 61434478 # DTB accesses
system.cpu.numCycles 4642702052 # number of cpu cycles simulated
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.committedInsts 60406834 # Number of instructions committed
system.cpu.committedOps 72742429 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 64191430 # Number of integer alu accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.num_func_calls 2135762 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 7544984 # number of instructions that are conditional controls
system.cpu.num_int_insts 64191430 # number of integer instructions
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.num_fp_insts 10269 # number of float instructions
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.num_int_register_reads 116427347 # number of times the integer registers were read
system.cpu.num_int_register_writes 42818107 # number of times the integer registers were written
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.num_cc_register_reads 217570004 # number of times the CC registers were read
system.cpu.num_cc_register_writes 28977741 # number of times the CC registers were written
system.cpu.num_mem_refs 25221274 # number of memory refs
system.cpu.num_load_insts 13499937 # Number of load instructions
system.cpu.num_store_insts 11721337 # Number of store instructions
system.cpu.num_idle_cycles 4568843017.980124 # Number of idle cycles
system.cpu.num_busy_cycles 73859034.019877 # Number of busy cycles
system.cpu.not_idle_fraction 0.015909 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.984091 # Percentage of idle cycles
system.cpu.Branches 10298517 # Number of branches fetched
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.op_class::IntAlu 47536032 65.23% 65.27% # Class of executed instruction
system.cpu.op_class::IntMult 87771 0.12% 65.39% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 2113 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.39% # Class of executed instruction
system.cpu.op_class::MemRead 13499937 18.52% 83.92% # Class of executed instruction
system.cpu.op_class::MemWrite 11721337 16.08% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.op_class::total 72875708 # Class of executed instruction
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.kern.inst.quiesce 82781 # number of quiesce instructions executed
system.cpu.icache.tags.replacements 850515 # number of replacements
system.cpu.icache.tags.tagsinuse 511.689593 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 60581740 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 851027 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 71.186625 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 5455017500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.689593 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999394 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999394 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.tag_accesses 62283794 # Number of tag accesses
system.cpu.icache.tags.data_accesses 62283794 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 60581740 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 60581740 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 60581740 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 60581740 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 60581740 # number of overall hits
system.cpu.icache.overall_hits::total 60581740 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 851027 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 851027 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 851027 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 851027 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 851027 # number of overall misses
system.cpu.icache.overall_misses::total 851027 # number of overall misses
system.cpu.icache.ReadReq_accesses::cpu.inst 61432767 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 61432767 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 61432767 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 61432767 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 61432767 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 61432767 # number of overall (read+write) accesses
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013853 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.013853 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.013853 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.013853 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.013853 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.013853 # miss rate for overall accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.replacements 62250 # number of replacements
system.cpu.l2cache.tags.tagsinuse 50006.834636 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1669916 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 127635 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 13.083527 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 2306278064000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 36897.866975 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.959775 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993971 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.476656 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 6090.537259 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.563017 # Average percentage of cache occupancy
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107032 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.092934 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.763044 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65380 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3672 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9281 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52125 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997620 # Percentage of cache occupancy per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.tag_accesses 17035648 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 17035648 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7541 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3151 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 838793 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 366790 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1216275 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 592642 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 592642 # number of Writeback hits
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 113706 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 113706 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7541 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 3151 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 838793 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 480496 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1329981 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7541 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 3151 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 838793 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 480496 # number of overall hits
system.cpu.l2cache.overall_hits::total 1329981 # number of overall hits
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 10608 # number of ReadReq misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.data 9871 # number of ReadReq misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.ReadReq_misses::total 20487 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2917 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2917 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 133474 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 133474 # number of ReadExReq misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.demand_misses::cpu.inst 10608 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 143345 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 153961 # number of demand (read+write) misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.overall_misses::cpu.inst 10608 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 143345 # number of overall misses
system.cpu.l2cache.overall_misses::total 153961 # number of overall misses
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7546 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3154 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 849401 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 376661 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1236762 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 592642 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 592642 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2943 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2943 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247180 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 247180 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7546 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3154 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 849401 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 623841 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1483942 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7546 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 849401 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 623841 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1483942 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000663 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000951 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012489 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026207 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.016565 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991165 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991165 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539987 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.539987 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000663 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000951 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012489 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.229778 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.103751 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000663 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000951 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012489 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.229778 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.103751 # miss rate for overall accesses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.writebacks::writebacks 57873 # number of writebacks
system.cpu.l2cache.writebacks::total 57873 # number of writebacks
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.tags.replacements 623329 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.997018 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 21798545 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 623841 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 34.942469 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 21757000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997018 # Average occupied blocks per requestor
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 291 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.tags.tag_accesses 90313385 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 90313385 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 11240226 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 11240226 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 9961316 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 9961316 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 110856 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 110856 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236008 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 236008 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 247196 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 247196 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 21201542 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 21201542 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 21312398 # number of overall hits
system.cpu.dcache.overall_hits::total 21312398 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 292030 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 292030 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 250123 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 250123 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 73442 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 73442 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11189 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 11189 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 542153 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 542153 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 615595 # number of overall misses
system.cpu.dcache.overall_misses::total 615595 # number of overall misses
system.cpu.dcache.ReadReq_accesses::cpu.data 11532256 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 11532256 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 10211439 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 10211439 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 184298 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 184298 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247197 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 247197 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247196 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 247196 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21743695 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21743695 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 21927993 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21927993 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025323 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.025323 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024494 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.024494 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.398496 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.398496 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045263 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045263 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.024934 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.024934 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.028073 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.028073 # miss rate for overall accesses
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.writebacks::writebacks 592642 # number of writebacks
system.cpu.dcache.writebacks::total 592642 # number of writebacks
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.toL2Bus.throughput 59392167 # Throughput (bytes/s)
system.cpu.toL2Bus.data_through_bus 137870067 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.iocache.tags.tag_accesses 0 # Number of tag accesses
system.iocache.tags.data_accesses 0 # Number of data accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
---------- End Simulation Statistics ----------
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