2010-05-24 07:44:15 +02:00
|
|
|
// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
|
2016-02-07 02:21:20 +01:00
|
|
|
// Copyright (c) 2015 Advanced Micro Devices, Inc.
|
2010-05-24 07:44:15 +02:00
|
|
|
// All rights reserved.
|
|
|
|
//
|
|
|
|
// The license below extends only to copyright in the software and shall
|
|
|
|
// not be construed as granting a license to any other intellectual
|
|
|
|
// property including but not limited to intellectual property relating
|
|
|
|
// to a hardware implementation of the functionality of the software
|
|
|
|
// licensed hereunder. You may use the software subject to the license
|
|
|
|
// terms below provided that you ensure that this notice is replicated
|
|
|
|
// unmodified and in its entirety in all distributions of the software,
|
|
|
|
// modified or unmodified, in source code or in binary form.
|
|
|
|
//
|
2008-02-27 05:39:22 +01:00
|
|
|
// Copyright (c) 2008 The Regents of The University of Michigan
|
|
|
|
// All rights reserved.
|
|
|
|
//
|
|
|
|
// Redistribution and use in source and binary forms, with or without
|
|
|
|
// modification, are permitted provided that the following conditions are
|
|
|
|
// met: redistributions of source code must retain the above copyright
|
|
|
|
// notice, this list of conditions and the following disclaimer;
|
|
|
|
// redistributions in binary form must reproduce the above copyright
|
|
|
|
// notice, this list of conditions and the following disclaimer in the
|
|
|
|
// documentation and/or other materials provided with the distribution;
|
|
|
|
// neither the name of the copyright holders nor the names of its
|
|
|
|
// contributors may be used to endorse or promote products derived from
|
|
|
|
// this software without specific prior written permission.
|
|
|
|
//
|
|
|
|
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
2007-06-13 20:05:08 +02:00
|
|
|
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
|
|
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
|
|
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
|
|
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
|
|
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
|
|
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
|
|
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
|
|
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
|
|
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
|
|
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
//
|
|
|
|
// Authors: Gabe Black
|
|
|
|
|
|
|
|
//////////////////////////////////////////////////////////////////////////
|
|
|
|
//
|
|
|
|
// LdStOp Microop templates
|
|
|
|
//
|
|
|
|
//////////////////////////////////////////////////////////////////////////
|
|
|
|
|
2007-06-20 17:02:50 +02:00
|
|
|
// LEA template
|
|
|
|
|
|
|
|
def template MicroLeaExecute {{
|
arch: teach ISA parser how to split code across files
This patch encompasses several interrelated and interdependent changes
to the ISA generation step. The end goal is to reduce the size of the
generated compilation units for instruction execution and decoding so
that batch compilation can proceed with all CPUs active without
exhausting physical memory.
The ISA parser (src/arch/isa_parser.py) has been improved so that it can
accept 'split [output_type];' directives at the top level of the grammar
and 'split(output_type)' python calls within 'exec {{ ... }}' blocks.
This has the effect of "splitting" the files into smaller compilation
units. I use air-quotes around "splitting" because the files themselves
are not split, but preprocessing directives are inserted to have the same
effect.
Architecturally, the ISA parser has had some changes in how it works.
In general, it emits code sooner. It doesn't generate per-CPU files,
and instead defers to the C preprocessor to create the duplicate copies
for each CPU type. Likewise there are more files emitted and the C
preprocessor does more substitution that used to be done by the ISA parser.
Finally, the build system (SCons) needs to be able to cope with a
dynamic list of source files coming out of the ISA parser. The changes
to the SCons{cript,truct} files support this. In broad strokes, the
targets requested on the command line are hidden from SCons until all
the build dependencies are determined, otherwise it would try, realize
it can't reach the goal, and terminate in failure. Since build steps
(i.e. running the ISA parser) must be taken to determine the file list,
several new build stages have been inserted at the very start of the
build. First, the build dependencies from the ISA parser will be emitted
to arch/$ISA/generated/inc.d, which is then read by a new SCons builder
to finalize the dependencies. (Once inc.d exists, the ISA parser will not
need to be run to complete this step.) Once the dependencies are known,
the 'Environments' are made by the makeEnv() function. This function used
to be called before the build began but now happens during the build.
It is easy to see that this step is quite slow; this is a known issue
and it's important to realize that it was already slow, but there was
no obvious cause to attribute it to since nothing was displayed to the
terminal. Since new steps that used to be performed serially are now in a
potentially-parallel build phase, the pathname handling in the SCons scripts
has been tightened up to deal with chdir() race conditions. In general,
pathnames are computed earlier and more likely to be stored, passed around,
and processed as absolute paths rather than relative paths. In the end,
some of these issues had to be fixed by inserting serializing dependencies
in the build.
Minor note:
For the null ISA, we just provide a dummy inc.d so SCons is never
compelled to try to generate it. While it seems slightly wrong to have
anything in src/arch/*/generated (i.e. a non-generated 'generated' file),
it's by far the simplest solution.
2014-05-10 00:58:47 +02:00
|
|
|
Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
|
2007-06-20 17:02:50 +02:00
|
|
|
Trace::InstRecord *traceData) const
|
|
|
|
{
|
|
|
|
Fault fault = NoFault;
|
|
|
|
Addr EA;
|
|
|
|
|
|
|
|
%(op_decl)s;
|
|
|
|
%(op_rd)s;
|
|
|
|
%(ea_code)s;
|
|
|
|
DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
|
|
|
|
|
|
|
|
%(code)s;
|
|
|
|
if(fault == NoFault)
|
|
|
|
{
|
|
|
|
%(op_wb)s;
|
|
|
|
}
|
|
|
|
|
|
|
|
return fault;
|
|
|
|
}
|
|
|
|
}};
|
|
|
|
|
|
|
|
def template MicroLeaDeclare {{
|
|
|
|
class %(class_name)s : public %(base_class)s
|
|
|
|
{
|
|
|
|
public:
|
|
|
|
%(class_name)s(ExtMachInst _machInst,
|
2010-08-23 18:44:19 +02:00
|
|
|
const char * instMnem, uint64_t setFlags,
|
2009-07-16 18:29:29 +02:00
|
|
|
uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
|
|
|
|
uint64_t _disp, InstRegIndex _segment,
|
|
|
|
InstRegIndex _data,
|
2009-02-25 19:18:22 +01:00
|
|
|
uint8_t _dataSize, uint8_t _addressSize,
|
|
|
|
Request::FlagsType _memFlags);
|
2007-06-20 17:02:50 +02:00
|
|
|
|
|
|
|
%(BasicExecDeclare)s
|
|
|
|
};
|
|
|
|
}};
|
|
|
|
|
|
|
|
// Load templates
|
|
|
|
|
2007-06-19 16:18:25 +02:00
|
|
|
def template MicroLoadExecute {{
|
arch: teach ISA parser how to split code across files
This patch encompasses several interrelated and interdependent changes
to the ISA generation step. The end goal is to reduce the size of the
generated compilation units for instruction execution and decoding so
that batch compilation can proceed with all CPUs active without
exhausting physical memory.
The ISA parser (src/arch/isa_parser.py) has been improved so that it can
accept 'split [output_type];' directives at the top level of the grammar
and 'split(output_type)' python calls within 'exec {{ ... }}' blocks.
This has the effect of "splitting" the files into smaller compilation
units. I use air-quotes around "splitting" because the files themselves
are not split, but preprocessing directives are inserted to have the same
effect.
Architecturally, the ISA parser has had some changes in how it works.
In general, it emits code sooner. It doesn't generate per-CPU files,
and instead defers to the C preprocessor to create the duplicate copies
for each CPU type. Likewise there are more files emitted and the C
preprocessor does more substitution that used to be done by the ISA parser.
Finally, the build system (SCons) needs to be able to cope with a
dynamic list of source files coming out of the ISA parser. The changes
to the SCons{cript,truct} files support this. In broad strokes, the
targets requested on the command line are hidden from SCons until all
the build dependencies are determined, otherwise it would try, realize
it can't reach the goal, and terminate in failure. Since build steps
(i.e. running the ISA parser) must be taken to determine the file list,
several new build stages have been inserted at the very start of the
build. First, the build dependencies from the ISA parser will be emitted
to arch/$ISA/generated/inc.d, which is then read by a new SCons builder
to finalize the dependencies. (Once inc.d exists, the ISA parser will not
need to be run to complete this step.) Once the dependencies are known,
the 'Environments' are made by the makeEnv() function. This function used
to be called before the build began but now happens during the build.
It is easy to see that this step is quite slow; this is a known issue
and it's important to realize that it was already slow, but there was
no obvious cause to attribute it to since nothing was displayed to the
terminal. Since new steps that used to be performed serially are now in a
potentially-parallel build phase, the pathname handling in the SCons scripts
has been tightened up to deal with chdir() race conditions. In general,
pathnames are computed earlier and more likely to be stored, passed around,
and processed as absolute paths rather than relative paths. In the end,
some of these issues had to be fixed by inserting serializing dependencies
in the build.
Minor note:
For the null ISA, we just provide a dummy inc.d so SCons is never
compelled to try to generate it. While it seems slightly wrong to have
anything in src/arch/*/generated (i.e. a non-generated 'generated' file),
it's by far the simplest solution.
2014-05-10 00:58:47 +02:00
|
|
|
Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
|
2007-06-19 16:18:25 +02:00
|
|
|
Trace::InstRecord *traceData) const
|
|
|
|
{
|
|
|
|
Fault fault = NoFault;
|
|
|
|
Addr EA;
|
|
|
|
|
|
|
|
%(op_decl)s;
|
|
|
|
%(op_rd)s;
|
|
|
|
%(ea_code)s;
|
|
|
|
DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
|
|
|
|
|
2016-02-07 02:21:20 +01:00
|
|
|
fault = readMemAtomic(xc, traceData, EA, Mem,
|
|
|
|
%(memDataSize)s, memFlags);
|
2007-07-21 00:02:09 +02:00
|
|
|
|
2009-02-25 19:19:22 +01:00
|
|
|
if (fault == NoFault) {
|
2007-06-19 16:18:25 +02:00
|
|
|
%(code)s;
|
2009-11-09 07:49:57 +01:00
|
|
|
} else if (memFlags & Request::PREFETCH) {
|
2009-02-25 19:19:22 +01:00
|
|
|
// For prefetches, ignore any faults/exceptions.
|
|
|
|
return NoFault;
|
2007-06-19 16:18:25 +02:00
|
|
|
}
|
|
|
|
if(fault == NoFault)
|
|
|
|
{
|
|
|
|
%(op_wb)s;
|
|
|
|
}
|
|
|
|
|
|
|
|
return fault;
|
|
|
|
}
|
|
|
|
}};
|
|
|
|
|
|
|
|
def template MicroLoadInitiateAcc {{
|
arch: teach ISA parser how to split code across files
This patch encompasses several interrelated and interdependent changes
to the ISA generation step. The end goal is to reduce the size of the
generated compilation units for instruction execution and decoding so
that batch compilation can proceed with all CPUs active without
exhausting physical memory.
The ISA parser (src/arch/isa_parser.py) has been improved so that it can
accept 'split [output_type];' directives at the top level of the grammar
and 'split(output_type)' python calls within 'exec {{ ... }}' blocks.
This has the effect of "splitting" the files into smaller compilation
units. I use air-quotes around "splitting" because the files themselves
are not split, but preprocessing directives are inserted to have the same
effect.
Architecturally, the ISA parser has had some changes in how it works.
In general, it emits code sooner. It doesn't generate per-CPU files,
and instead defers to the C preprocessor to create the duplicate copies
for each CPU type. Likewise there are more files emitted and the C
preprocessor does more substitution that used to be done by the ISA parser.
Finally, the build system (SCons) needs to be able to cope with a
dynamic list of source files coming out of the ISA parser. The changes
to the SCons{cript,truct} files support this. In broad strokes, the
targets requested on the command line are hidden from SCons until all
the build dependencies are determined, otherwise it would try, realize
it can't reach the goal, and terminate in failure. Since build steps
(i.e. running the ISA parser) must be taken to determine the file list,
several new build stages have been inserted at the very start of the
build. First, the build dependencies from the ISA parser will be emitted
to arch/$ISA/generated/inc.d, which is then read by a new SCons builder
to finalize the dependencies. (Once inc.d exists, the ISA parser will not
need to be run to complete this step.) Once the dependencies are known,
the 'Environments' are made by the makeEnv() function. This function used
to be called before the build began but now happens during the build.
It is easy to see that this step is quite slow; this is a known issue
and it's important to realize that it was already slow, but there was
no obvious cause to attribute it to since nothing was displayed to the
terminal. Since new steps that used to be performed serially are now in a
potentially-parallel build phase, the pathname handling in the SCons scripts
has been tightened up to deal with chdir() race conditions. In general,
pathnames are computed earlier and more likely to be stored, passed around,
and processed as absolute paths rather than relative paths. In the end,
some of these issues had to be fixed by inserting serializing dependencies
in the build.
Minor note:
For the null ISA, we just provide a dummy inc.d so SCons is never
compelled to try to generate it. While it seems slightly wrong to have
anything in src/arch/*/generated (i.e. a non-generated 'generated' file),
it's by far the simplest solution.
2014-05-10 00:58:47 +02:00
|
|
|
Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT * xc,
|
2007-06-19 16:18:25 +02:00
|
|
|
Trace::InstRecord * traceData) const
|
|
|
|
{
|
|
|
|
Fault fault = NoFault;
|
|
|
|
Addr EA;
|
|
|
|
|
|
|
|
%(op_decl)s;
|
|
|
|
%(op_rd)s;
|
|
|
|
%(ea_code)s;
|
|
|
|
DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
|
|
|
|
|
2016-02-07 02:21:20 +01:00
|
|
|
fault = initiateMemRead(xc, traceData, EA,
|
|
|
|
%(memDataSize)s, memFlags);
|
2007-06-19 16:18:25 +02:00
|
|
|
|
|
|
|
return fault;
|
|
|
|
}
|
|
|
|
}};
|
|
|
|
|
|
|
|
def template MicroLoadCompleteAcc {{
|
|
|
|
Fault %(class_name)s::completeAcc(PacketPtr pkt,
|
arch: teach ISA parser how to split code across files
This patch encompasses several interrelated and interdependent changes
to the ISA generation step. The end goal is to reduce the size of the
generated compilation units for instruction execution and decoding so
that batch compilation can proceed with all CPUs active without
exhausting physical memory.
The ISA parser (src/arch/isa_parser.py) has been improved so that it can
accept 'split [output_type];' directives at the top level of the grammar
and 'split(output_type)' python calls within 'exec {{ ... }}' blocks.
This has the effect of "splitting" the files into smaller compilation
units. I use air-quotes around "splitting" because the files themselves
are not split, but preprocessing directives are inserted to have the same
effect.
Architecturally, the ISA parser has had some changes in how it works.
In general, it emits code sooner. It doesn't generate per-CPU files,
and instead defers to the C preprocessor to create the duplicate copies
for each CPU type. Likewise there are more files emitted and the C
preprocessor does more substitution that used to be done by the ISA parser.
Finally, the build system (SCons) needs to be able to cope with a
dynamic list of source files coming out of the ISA parser. The changes
to the SCons{cript,truct} files support this. In broad strokes, the
targets requested on the command line are hidden from SCons until all
the build dependencies are determined, otherwise it would try, realize
it can't reach the goal, and terminate in failure. Since build steps
(i.e. running the ISA parser) must be taken to determine the file list,
several new build stages have been inserted at the very start of the
build. First, the build dependencies from the ISA parser will be emitted
to arch/$ISA/generated/inc.d, which is then read by a new SCons builder
to finalize the dependencies. (Once inc.d exists, the ISA parser will not
need to be run to complete this step.) Once the dependencies are known,
the 'Environments' are made by the makeEnv() function. This function used
to be called before the build began but now happens during the build.
It is easy to see that this step is quite slow; this is a known issue
and it's important to realize that it was already slow, but there was
no obvious cause to attribute it to since nothing was displayed to the
terminal. Since new steps that used to be performed serially are now in a
potentially-parallel build phase, the pathname handling in the SCons scripts
has been tightened up to deal with chdir() race conditions. In general,
pathnames are computed earlier and more likely to be stored, passed around,
and processed as absolute paths rather than relative paths. In the end,
some of these issues had to be fixed by inserting serializing dependencies
in the build.
Minor note:
For the null ISA, we just provide a dummy inc.d so SCons is never
compelled to try to generate it. While it seems slightly wrong to have
anything in src/arch/*/generated (i.e. a non-generated 'generated' file),
it's by far the simplest solution.
2014-05-10 00:58:47 +02:00
|
|
|
CPU_EXEC_CONTEXT * xc,
|
2007-06-19 16:18:25 +02:00
|
|
|
Trace::InstRecord * traceData) const
|
|
|
|
{
|
|
|
|
Fault fault = NoFault;
|
|
|
|
|
|
|
|
%(op_decl)s;
|
|
|
|
%(op_rd)s;
|
|
|
|
|
2016-02-07 02:21:20 +01:00
|
|
|
getMem(pkt, Mem, %(memDataSize)s, traceData);
|
2007-08-27 05:30:36 +02:00
|
|
|
|
2007-06-19 16:18:25 +02:00
|
|
|
%(code)s;
|
|
|
|
|
|
|
|
if(fault == NoFault)
|
|
|
|
{
|
|
|
|
%(op_wb)s;
|
|
|
|
}
|
|
|
|
|
|
|
|
return fault;
|
|
|
|
}
|
|
|
|
}};
|
|
|
|
|
|
|
|
// Store templates
|
|
|
|
|
|
|
|
def template MicroStoreExecute {{
|
arch: teach ISA parser how to split code across files
This patch encompasses several interrelated and interdependent changes
to the ISA generation step. The end goal is to reduce the size of the
generated compilation units for instruction execution and decoding so
that batch compilation can proceed with all CPUs active without
exhausting physical memory.
The ISA parser (src/arch/isa_parser.py) has been improved so that it can
accept 'split [output_type];' directives at the top level of the grammar
and 'split(output_type)' python calls within 'exec {{ ... }}' blocks.
This has the effect of "splitting" the files into smaller compilation
units. I use air-quotes around "splitting" because the files themselves
are not split, but preprocessing directives are inserted to have the same
effect.
Architecturally, the ISA parser has had some changes in how it works.
In general, it emits code sooner. It doesn't generate per-CPU files,
and instead defers to the C preprocessor to create the duplicate copies
for each CPU type. Likewise there are more files emitted and the C
preprocessor does more substitution that used to be done by the ISA parser.
Finally, the build system (SCons) needs to be able to cope with a
dynamic list of source files coming out of the ISA parser. The changes
to the SCons{cript,truct} files support this. In broad strokes, the
targets requested on the command line are hidden from SCons until all
the build dependencies are determined, otherwise it would try, realize
it can't reach the goal, and terminate in failure. Since build steps
(i.e. running the ISA parser) must be taken to determine the file list,
several new build stages have been inserted at the very start of the
build. First, the build dependencies from the ISA parser will be emitted
to arch/$ISA/generated/inc.d, which is then read by a new SCons builder
to finalize the dependencies. (Once inc.d exists, the ISA parser will not
need to be run to complete this step.) Once the dependencies are known,
the 'Environments' are made by the makeEnv() function. This function used
to be called before the build began but now happens during the build.
It is easy to see that this step is quite slow; this is a known issue
and it's important to realize that it was already slow, but there was
no obvious cause to attribute it to since nothing was displayed to the
terminal. Since new steps that used to be performed serially are now in a
potentially-parallel build phase, the pathname handling in the SCons scripts
has been tightened up to deal with chdir() race conditions. In general,
pathnames are computed earlier and more likely to be stored, passed around,
and processed as absolute paths rather than relative paths. In the end,
some of these issues had to be fixed by inserting serializing dependencies
in the build.
Minor note:
For the null ISA, we just provide a dummy inc.d so SCons is never
compelled to try to generate it. While it seems slightly wrong to have
anything in src/arch/*/generated (i.e. a non-generated 'generated' file),
it's by far the simplest solution.
2014-05-10 00:58:47 +02:00
|
|
|
Fault %(class_name)s::execute(CPU_EXEC_CONTEXT * xc,
|
2007-06-19 16:18:25 +02:00
|
|
|
Trace::InstRecord *traceData) const
|
|
|
|
{
|
|
|
|
Fault fault = NoFault;
|
|
|
|
|
|
|
|
Addr EA;
|
|
|
|
%(op_decl)s;
|
|
|
|
%(op_rd)s;
|
|
|
|
%(ea_code)s;
|
|
|
|
DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
|
|
|
|
|
|
|
|
%(code)s;
|
|
|
|
|
|
|
|
if(fault == NoFault)
|
|
|
|
{
|
2016-02-07 02:21:20 +01:00
|
|
|
fault = writeMemAtomic(xc, traceData, Mem, %(memDataSize)s, EA,
|
2011-07-03 07:34:29 +02:00
|
|
|
memFlags, NULL);
|
2007-07-27 07:08:35 +02:00
|
|
|
if(fault == NoFault)
|
2007-07-21 00:02:09 +02:00
|
|
|
{
|
2007-07-27 07:08:35 +02:00
|
|
|
%(op_wb)s;
|
2007-07-21 00:02:09 +02:00
|
|
|
}
|
2007-06-19 16:18:25 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
return fault;
|
|
|
|
}
|
|
|
|
}};
|
|
|
|
|
|
|
|
def template MicroStoreInitiateAcc {{
|
arch: teach ISA parser how to split code across files
This patch encompasses several interrelated and interdependent changes
to the ISA generation step. The end goal is to reduce the size of the
generated compilation units for instruction execution and decoding so
that batch compilation can proceed with all CPUs active without
exhausting physical memory.
The ISA parser (src/arch/isa_parser.py) has been improved so that it can
accept 'split [output_type];' directives at the top level of the grammar
and 'split(output_type)' python calls within 'exec {{ ... }}' blocks.
This has the effect of "splitting" the files into smaller compilation
units. I use air-quotes around "splitting" because the files themselves
are not split, but preprocessing directives are inserted to have the same
effect.
Architecturally, the ISA parser has had some changes in how it works.
In general, it emits code sooner. It doesn't generate per-CPU files,
and instead defers to the C preprocessor to create the duplicate copies
for each CPU type. Likewise there are more files emitted and the C
preprocessor does more substitution that used to be done by the ISA parser.
Finally, the build system (SCons) needs to be able to cope with a
dynamic list of source files coming out of the ISA parser. The changes
to the SCons{cript,truct} files support this. In broad strokes, the
targets requested on the command line are hidden from SCons until all
the build dependencies are determined, otherwise it would try, realize
it can't reach the goal, and terminate in failure. Since build steps
(i.e. running the ISA parser) must be taken to determine the file list,
several new build stages have been inserted at the very start of the
build. First, the build dependencies from the ISA parser will be emitted
to arch/$ISA/generated/inc.d, which is then read by a new SCons builder
to finalize the dependencies. (Once inc.d exists, the ISA parser will not
need to be run to complete this step.) Once the dependencies are known,
the 'Environments' are made by the makeEnv() function. This function used
to be called before the build began but now happens during the build.
It is easy to see that this step is quite slow; this is a known issue
and it's important to realize that it was already slow, but there was
no obvious cause to attribute it to since nothing was displayed to the
terminal. Since new steps that used to be performed serially are now in a
potentially-parallel build phase, the pathname handling in the SCons scripts
has been tightened up to deal with chdir() race conditions. In general,
pathnames are computed earlier and more likely to be stored, passed around,
and processed as absolute paths rather than relative paths. In the end,
some of these issues had to be fixed by inserting serializing dependencies
in the build.
Minor note:
For the null ISA, we just provide a dummy inc.d so SCons is never
compelled to try to generate it. While it seems slightly wrong to have
anything in src/arch/*/generated (i.e. a non-generated 'generated' file),
it's by far the simplest solution.
2014-05-10 00:58:47 +02:00
|
|
|
Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT * xc,
|
2007-06-19 16:18:25 +02:00
|
|
|
Trace::InstRecord * traceData) const
|
|
|
|
{
|
|
|
|
Fault fault = NoFault;
|
|
|
|
|
|
|
|
Addr EA;
|
|
|
|
%(op_decl)s;
|
|
|
|
%(op_rd)s;
|
|
|
|
%(ea_code)s;
|
|
|
|
DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
|
|
|
|
|
|
|
|
%(code)s;
|
|
|
|
|
|
|
|
if(fault == NoFault)
|
|
|
|
{
|
2016-02-07 02:21:20 +01:00
|
|
|
fault = writeMemTiming(xc, traceData, Mem, %(memDataSize)s, EA,
|
2011-07-03 07:34:29 +02:00
|
|
|
memFlags, NULL);
|
2007-06-19 16:18:25 +02:00
|
|
|
}
|
|
|
|
return fault;
|
|
|
|
}
|
|
|
|
}};
|
|
|
|
|
|
|
|
def template MicroStoreCompleteAcc {{
|
2009-02-25 19:15:56 +01:00
|
|
|
Fault %(class_name)s::completeAcc(PacketPtr pkt,
|
arch: teach ISA parser how to split code across files
This patch encompasses several interrelated and interdependent changes
to the ISA generation step. The end goal is to reduce the size of the
generated compilation units for instruction execution and decoding so
that batch compilation can proceed with all CPUs active without
exhausting physical memory.
The ISA parser (src/arch/isa_parser.py) has been improved so that it can
accept 'split [output_type];' directives at the top level of the grammar
and 'split(output_type)' python calls within 'exec {{ ... }}' blocks.
This has the effect of "splitting" the files into smaller compilation
units. I use air-quotes around "splitting" because the files themselves
are not split, but preprocessing directives are inserted to have the same
effect.
Architecturally, the ISA parser has had some changes in how it works.
In general, it emits code sooner. It doesn't generate per-CPU files,
and instead defers to the C preprocessor to create the duplicate copies
for each CPU type. Likewise there are more files emitted and the C
preprocessor does more substitution that used to be done by the ISA parser.
Finally, the build system (SCons) needs to be able to cope with a
dynamic list of source files coming out of the ISA parser. The changes
to the SCons{cript,truct} files support this. In broad strokes, the
targets requested on the command line are hidden from SCons until all
the build dependencies are determined, otherwise it would try, realize
it can't reach the goal, and terminate in failure. Since build steps
(i.e. running the ISA parser) must be taken to determine the file list,
several new build stages have been inserted at the very start of the
build. First, the build dependencies from the ISA parser will be emitted
to arch/$ISA/generated/inc.d, which is then read by a new SCons builder
to finalize the dependencies. (Once inc.d exists, the ISA parser will not
need to be run to complete this step.) Once the dependencies are known,
the 'Environments' are made by the makeEnv() function. This function used
to be called before the build began but now happens during the build.
It is easy to see that this step is quite slow; this is a known issue
and it's important to realize that it was already slow, but there was
no obvious cause to attribute it to since nothing was displayed to the
terminal. Since new steps that used to be performed serially are now in a
potentially-parallel build phase, the pathname handling in the SCons scripts
has been tightened up to deal with chdir() race conditions. In general,
pathnames are computed earlier and more likely to be stored, passed around,
and processed as absolute paths rather than relative paths. In the end,
some of these issues had to be fixed by inserting serializing dependencies
in the build.
Minor note:
For the null ISA, we just provide a dummy inc.d so SCons is never
compelled to try to generate it. While it seems slightly wrong to have
anything in src/arch/*/generated (i.e. a non-generated 'generated' file),
it's by far the simplest solution.
2014-05-10 00:58:47 +02:00
|
|
|
CPU_EXEC_CONTEXT * xc, Trace::InstRecord * traceData) const
|
2007-06-19 16:18:25 +02:00
|
|
|
{
|
2009-02-25 19:15:56 +01:00
|
|
|
%(op_decl)s;
|
|
|
|
%(op_rd)s;
|
|
|
|
%(complete_code)s;
|
|
|
|
%(op_wb)s;
|
2007-06-19 16:18:25 +02:00
|
|
|
return NoFault;
|
|
|
|
}
|
|
|
|
}};
|
|
|
|
|
|
|
|
// Common templates
|
|
|
|
|
|
|
|
//This delcares the initiateAcc function in memory operations
|
|
|
|
def template InitiateAccDeclare {{
|
|
|
|
Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
|
|
|
|
}};
|
|
|
|
|
|
|
|
//This declares the completeAcc function in memory operations
|
|
|
|
def template CompleteAccDeclare {{
|
|
|
|
Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
|
|
|
|
}};
|
|
|
|
|
|
|
|
def template MicroLdStOpDeclare {{
|
|
|
|
class %(class_name)s : public %(base_class)s
|
|
|
|
{
|
2007-06-13 20:05:08 +02:00
|
|
|
public:
|
|
|
|
%(class_name)s(ExtMachInst _machInst,
|
2010-08-23 18:44:19 +02:00
|
|
|
const char * instMnem, uint64_t setFlags,
|
2009-07-16 18:29:29 +02:00
|
|
|
uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
|
|
|
|
uint64_t _disp, InstRegIndex _segment,
|
|
|
|
InstRegIndex _data,
|
2009-02-25 19:18:22 +01:00
|
|
|
uint8_t _dataSize, uint8_t _addressSize,
|
|
|
|
Request::FlagsType _memFlags);
|
2007-06-13 20:05:08 +02:00
|
|
|
|
|
|
|
%(BasicExecDeclare)s
|
2007-06-19 16:18:25 +02:00
|
|
|
|
|
|
|
%(InitiateAccDeclare)s
|
|
|
|
|
|
|
|
%(CompleteAccDeclare)s
|
2007-06-13 20:05:08 +02:00
|
|
|
};
|
|
|
|
}};
|
|
|
|
|
2016-02-07 02:21:20 +01:00
|
|
|
// LdStSplitOp is a load or store that uses a pair of regs as the
|
|
|
|
// source or destination. Used for cmpxchg{8,16}b.
|
|
|
|
def template MicroLdStSplitOpDeclare {{
|
|
|
|
class %(class_name)s : public %(base_class)s
|
|
|
|
{
|
|
|
|
public:
|
|
|
|
%(class_name)s(ExtMachInst _machInst,
|
|
|
|
const char * instMnem, uint64_t setFlags,
|
|
|
|
uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
|
|
|
|
uint64_t _disp, InstRegIndex _segment,
|
|
|
|
InstRegIndex _dataLow, InstRegIndex _dataHi,
|
|
|
|
uint8_t _dataSize, uint8_t _addressSize,
|
|
|
|
Request::FlagsType _memFlags);
|
|
|
|
|
|
|
|
%(BasicExecDeclare)s
|
|
|
|
|
|
|
|
%(InitiateAccDeclare)s
|
|
|
|
|
|
|
|
%(CompleteAccDeclare)s
|
|
|
|
};
|
|
|
|
}};
|
|
|
|
|
2007-06-13 20:05:08 +02:00
|
|
|
def template MicroLdStOpConstructor {{
|
2014-05-10 00:58:46 +02:00
|
|
|
%(class_name)s::%(class_name)s(
|
2010-08-23 18:44:19 +02:00
|
|
|
ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
|
2009-07-16 18:29:29 +02:00
|
|
|
uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
|
|
|
|
uint64_t _disp, InstRegIndex _segment,
|
|
|
|
InstRegIndex _data,
|
2009-02-25 19:18:22 +01:00
|
|
|
uint8_t _dataSize, uint8_t _addressSize,
|
|
|
|
Request::FlagsType _memFlags) :
|
2010-08-23 18:44:19 +02:00
|
|
|
%(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
|
2007-06-19 16:18:25 +02:00
|
|
|
_scale, _index, _base,
|
|
|
|
_disp, _segment, _data,
|
2009-02-25 19:18:22 +01:00
|
|
|
_dataSize, _addressSize, _memFlags, %(op_class)s)
|
2007-06-13 20:05:08 +02:00
|
|
|
{
|
2010-08-23 18:44:19 +02:00
|
|
|
%(constructor)s;
|
2007-06-13 20:05:08 +02:00
|
|
|
}
|
|
|
|
}};
|
|
|
|
|
2016-02-07 02:21:20 +01:00
|
|
|
def template MicroLdStSplitOpConstructor {{
|
|
|
|
%(class_name)s::%(class_name)s(
|
|
|
|
ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
|
|
|
|
uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
|
|
|
|
uint64_t _disp, InstRegIndex _segment,
|
|
|
|
InstRegIndex _dataLow, InstRegIndex _dataHi,
|
|
|
|
uint8_t _dataSize, uint8_t _addressSize,
|
|
|
|
Request::FlagsType _memFlags) :
|
|
|
|
%(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
|
|
|
|
_scale, _index, _base,
|
|
|
|
_disp, _segment, _dataLow, _dataHi,
|
|
|
|
_dataSize, _addressSize, _memFlags, %(op_class)s)
|
|
|
|
{
|
|
|
|
%(constructor)s;
|
|
|
|
}
|
|
|
|
}};
|
|
|
|
|
2007-06-19 16:18:25 +02:00
|
|
|
let {{
|
|
|
|
class LdStOp(X86Microop):
|
2009-02-25 19:18:22 +01:00
|
|
|
def __init__(self, data, segment, addr, disp,
|
2017-02-10 17:19:34 +01:00
|
|
|
dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
|
|
|
|
implicitStack):
|
2007-06-19 16:18:25 +02:00
|
|
|
self.data = data
|
|
|
|
[self.scale, self.index, self.base] = addr
|
|
|
|
self.disp = disp
|
|
|
|
self.segment = segment
|
2007-07-20 00:15:47 +02:00
|
|
|
self.dataSize = dataSize
|
2007-10-13 01:37:55 +02:00
|
|
|
self.addressSize = addressSize
|
2009-02-25 19:18:22 +01:00
|
|
|
self.memFlags = baseFlags
|
|
|
|
if atCPL0:
|
|
|
|
self.memFlags += " | (CPL0FlagBit << FlagShift)"
|
2011-03-02 07:42:18 +01:00
|
|
|
self.instFlags = ""
|
2009-02-25 19:19:22 +01:00
|
|
|
if prefetch:
|
2009-11-09 07:49:57 +01:00
|
|
|
self.memFlags += " | Request::PREFETCH"
|
2011-03-02 07:42:59 +01:00
|
|
|
self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
|
|
|
|
if nonSpec:
|
|
|
|
self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
|
2017-02-10 17:19:34 +01:00
|
|
|
# For implicit stack operations, we should use *not* use the
|
|
|
|
# alternative addressing mode for loads/stores if the prefix is set
|
|
|
|
if not implicitStack:
|
|
|
|
self.memFlags += " | (machInst.legacy.addr ? " + \
|
|
|
|
"(AddrSizeFlagBit << FlagShift) : 0)"
|
2007-06-19 16:18:25 +02:00
|
|
|
|
2010-08-23 18:44:19 +02:00
|
|
|
def getAllocator(self, microFlags):
|
|
|
|
allocator = '''new %(class_name)s(machInst, macrocodeBlock,
|
2007-06-19 16:18:25 +02:00
|
|
|
%(flags)s, %(scale)s, %(index)s, %(base)s,
|
|
|
|
%(disp)s, %(segment)s, %(data)s,
|
2009-02-25 19:18:22 +01:00
|
|
|
%(dataSize)s, %(addressSize)s, %(memFlags)s)''' % {
|
2007-06-19 16:18:25 +02:00
|
|
|
"class_name" : self.className,
|
2011-03-02 07:42:18 +01:00
|
|
|
"flags" : self.microFlagsText(microFlags) + self.instFlags,
|
2007-06-19 16:18:25 +02:00
|
|
|
"scale" : self.scale, "index" : self.index,
|
|
|
|
"base" : self.base,
|
|
|
|
"disp" : self.disp,
|
|
|
|
"segment" : self.segment, "data" : self.data,
|
2009-02-25 19:18:22 +01:00
|
|
|
"dataSize" : self.dataSize, "addressSize" : self.addressSize,
|
|
|
|
"memFlags" : self.memFlags}
|
2007-06-19 16:18:25 +02:00
|
|
|
return allocator
|
2011-02-14 02:44:24 +01:00
|
|
|
|
|
|
|
class BigLdStOp(X86Microop):
|
|
|
|
def __init__(self, data, segment, addr, disp,
|
2017-02-10 17:19:34 +01:00
|
|
|
dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
|
|
|
|
implicitStack):
|
2011-02-14 02:44:24 +01:00
|
|
|
self.data = data
|
|
|
|
[self.scale, self.index, self.base] = addr
|
|
|
|
self.disp = disp
|
|
|
|
self.segment = segment
|
|
|
|
self.dataSize = dataSize
|
|
|
|
self.addressSize = addressSize
|
|
|
|
self.memFlags = baseFlags
|
|
|
|
if atCPL0:
|
|
|
|
self.memFlags += " | (CPL0FlagBit << FlagShift)"
|
2011-03-02 07:42:59 +01:00
|
|
|
self.instFlags = ""
|
2011-02-14 02:44:24 +01:00
|
|
|
if prefetch:
|
|
|
|
self.memFlags += " | Request::PREFETCH"
|
2011-03-02 07:42:59 +01:00
|
|
|
self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
|
|
|
|
if nonSpec:
|
|
|
|
self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
|
2017-02-10 17:19:34 +01:00
|
|
|
# For implicit stack operations, we should use *not* use the
|
|
|
|
# alternative addressing mode for loads/stores if the prefix is set
|
|
|
|
if not implicitStack:
|
|
|
|
self.memFlags += " | (machInst.legacy.addr ? " + \
|
|
|
|
"(AddrSizeFlagBit << FlagShift) : 0)"
|
2011-02-14 02:44:24 +01:00
|
|
|
|
|
|
|
def getAllocator(self, microFlags):
|
|
|
|
allocString = '''
|
|
|
|
(%(dataSize)s >= 4) ?
|
|
|
|
(StaticInstPtr)(new %(class_name)sBig(machInst,
|
|
|
|
macrocodeBlock, %(flags)s, %(scale)s, %(index)s,
|
|
|
|
%(base)s, %(disp)s, %(segment)s, %(data)s,
|
|
|
|
%(dataSize)s, %(addressSize)s, %(memFlags)s)) :
|
|
|
|
(StaticInstPtr)(new %(class_name)s(machInst,
|
|
|
|
macrocodeBlock, %(flags)s, %(scale)s, %(index)s,
|
|
|
|
%(base)s, %(disp)s, %(segment)s, %(data)s,
|
|
|
|
%(dataSize)s, %(addressSize)s, %(memFlags)s))
|
|
|
|
'''
|
|
|
|
allocator = allocString % {
|
|
|
|
"class_name" : self.className,
|
2011-03-02 07:42:59 +01:00
|
|
|
"flags" : self.microFlagsText(microFlags) + self.instFlags,
|
2011-02-14 02:44:24 +01:00
|
|
|
"scale" : self.scale, "index" : self.index,
|
|
|
|
"base" : self.base,
|
|
|
|
"disp" : self.disp,
|
|
|
|
"segment" : self.segment, "data" : self.data,
|
|
|
|
"dataSize" : self.dataSize, "addressSize" : self.addressSize,
|
|
|
|
"memFlags" : self.memFlags}
|
|
|
|
return allocator
|
2016-02-07 02:21:20 +01:00
|
|
|
|
|
|
|
class LdStSplitOp(LdStOp):
|
|
|
|
def __init__(self, data, segment, addr, disp,
|
2017-02-10 17:19:34 +01:00
|
|
|
dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
|
|
|
|
implicitStack):
|
2016-02-07 02:21:20 +01:00
|
|
|
super(LdStSplitOp, self).__init__(0, segment, addr, disp,
|
2017-02-10 17:19:34 +01:00
|
|
|
dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
|
|
|
|
implicitStack)
|
2016-02-07 02:21:20 +01:00
|
|
|
(self.dataLow, self.dataHi) = data
|
|
|
|
|
|
|
|
def getAllocator(self, microFlags):
|
|
|
|
allocString = '''(StaticInstPtr)(new %(class_name)s(machInst,
|
|
|
|
macrocodeBlock, %(flags)s, %(scale)s, %(index)s,
|
|
|
|
%(base)s, %(disp)s, %(segment)s,
|
|
|
|
%(dataLow)s, %(dataHi)s,
|
|
|
|
%(dataSize)s, %(addressSize)s, %(memFlags)s))
|
|
|
|
'''
|
|
|
|
allocator = allocString % {
|
|
|
|
"class_name" : self.className,
|
|
|
|
"flags" : self.microFlagsText(microFlags) + self.instFlags,
|
|
|
|
"scale" : self.scale, "index" : self.index,
|
|
|
|
"base" : self.base,
|
|
|
|
"disp" : self.disp,
|
|
|
|
"segment" : self.segment,
|
|
|
|
"dataLow" : self.dataLow, "dataHi" : self.dataHi,
|
|
|
|
"dataSize" : self.dataSize, "addressSize" : self.addressSize,
|
|
|
|
"memFlags" : self.memFlags}
|
|
|
|
return allocator
|
|
|
|
|
2007-06-19 16:18:25 +02:00
|
|
|
}};
|
|
|
|
|
|
|
|
let {{
|
|
|
|
|
|
|
|
# Make these empty strings so that concatenating onto
|
|
|
|
# them will always work.
|
|
|
|
header_output = ""
|
|
|
|
decoder_output = ""
|
|
|
|
exec_output = ""
|
|
|
|
|
2016-02-07 02:21:20 +01:00
|
|
|
segmentEAExpr = \
|
|
|
|
'bits(scale * Index + Base + disp, addressSize * 8 - 1, 0);'
|
|
|
|
|
|
|
|
calculateEA = 'EA = SegBase + ' + segmentEAExpr
|
2007-06-19 16:18:25 +02:00
|
|
|
|
2011-02-14 02:44:24 +01:00
|
|
|
def defineMicroLoadOp(mnemonic, code, bigCode='',
|
2017-02-10 17:19:34 +01:00
|
|
|
mem_flags="0", big=True, nonSpec=False,
|
|
|
|
implicitStack=False):
|
2007-06-19 16:18:25 +02:00
|
|
|
global header_output
|
|
|
|
global decoder_output
|
|
|
|
global exec_output
|
|
|
|
global microopClasses
|
|
|
|
Name = mnemonic
|
|
|
|
name = mnemonic.lower()
|
|
|
|
|
|
|
|
# Build up the all register version of this micro op
|
2011-02-14 02:44:24 +01:00
|
|
|
iops = [InstObjParams(name, Name, 'X86ISA::LdStOp',
|
2016-02-07 02:21:20 +01:00
|
|
|
{ "code": code,
|
|
|
|
"ea_code": calculateEA,
|
|
|
|
"memDataSize": "dataSize" })]
|
2011-02-14 02:44:24 +01:00
|
|
|
if big:
|
|
|
|
iops += [InstObjParams(name, Name + "Big", 'X86ISA::LdStOp',
|
2016-02-07 02:21:20 +01:00
|
|
|
{ "code": bigCode,
|
|
|
|
"ea_code": calculateEA,
|
|
|
|
"memDataSize": "dataSize" })]
|
2011-02-14 02:44:24 +01:00
|
|
|
for iop in iops:
|
|
|
|
header_output += MicroLdStOpDeclare.subst(iop)
|
|
|
|
decoder_output += MicroLdStOpConstructor.subst(iop)
|
|
|
|
exec_output += MicroLoadExecute.subst(iop)
|
|
|
|
exec_output += MicroLoadInitiateAcc.subst(iop)
|
|
|
|
exec_output += MicroLoadCompleteAcc.subst(iop)
|
|
|
|
|
2017-02-10 17:19:34 +01:00
|
|
|
if implicitStack:
|
|
|
|
# For instructions that implicitly access the stack, the address
|
|
|
|
# size is the same as the stack segment pointer size, not the
|
|
|
|
# address size if specified by the instruction prefix
|
|
|
|
addressSize = "env.stackSize"
|
|
|
|
else:
|
|
|
|
addressSize = "env.addressSize"
|
|
|
|
|
2011-02-14 02:44:24 +01:00
|
|
|
base = LdStOp
|
|
|
|
if big:
|
|
|
|
base = BigLdStOp
|
|
|
|
class LoadOp(base):
|
2007-10-13 01:37:55 +02:00
|
|
|
def __init__(self, data, segment, addr, disp = 0,
|
2009-02-25 19:18:22 +01:00
|
|
|
dataSize="env.dataSize",
|
2017-02-10 17:19:34 +01:00
|
|
|
addressSize=addressSize,
|
|
|
|
atCPL0=False, prefetch=False, nonSpec=nonSpec,
|
|
|
|
implicitStack=implicitStack):
|
2009-02-25 19:18:22 +01:00
|
|
|
super(LoadOp, self).__init__(data, segment, addr,
|
2009-02-25 19:19:22 +01:00
|
|
|
disp, dataSize, addressSize, mem_flags,
|
2017-02-10 17:19:34 +01:00
|
|
|
atCPL0, prefetch, nonSpec, implicitStack)
|
2007-06-19 16:18:25 +02:00
|
|
|
self.className = Name
|
|
|
|
self.mnemonic = name
|
|
|
|
|
|
|
|
microopClasses[name] = LoadOp
|
|
|
|
|
2011-02-14 02:44:24 +01:00
|
|
|
defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);',
|
|
|
|
'Data = Mem & mask(dataSize * 8);')
|
2017-02-10 17:19:34 +01:00
|
|
|
defineMicroLoadOp('Ldis', 'Data = merge(Data, Mem, dataSize);',
|
|
|
|
'Data = Mem & mask(dataSize * 8);',
|
|
|
|
implicitStack=True)
|
2009-02-25 19:18:22 +01:00
|
|
|
defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);',
|
2011-02-14 02:44:24 +01:00
|
|
|
'Data = Mem & mask(dataSize * 8);',
|
|
|
|
'(StoreCheck << FlagShift)')
|
2009-04-19 13:55:43 +02:00
|
|
|
defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);',
|
2011-02-14 02:44:24 +01:00
|
|
|
'Data = Mem & mask(dataSize * 8);',
|
2016-02-07 02:21:20 +01:00
|
|
|
'(StoreCheck << FlagShift) | Request::LOCKED_RMW',
|
|
|
|
nonSpec=True)
|
2013-09-30 12:00:20 +02:00
|
|
|
|
|
|
|
defineMicroLoadOp('Ldfp', code='FpData_uqw = Mem', big = False)
|
|
|
|
|
|
|
|
defineMicroLoadOp('Ldfp87', code='''
|
|
|
|
switch (dataSize)
|
|
|
|
{
|
|
|
|
case 4:
|
|
|
|
FpData_df = *(float *)&Mem;
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
FpData_df = *(double *)&Mem;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
panic("Unhandled data size in LdFp87.\\n");
|
|
|
|
}
|
|
|
|
''', big = False)
|
2007-06-19 16:18:25 +02:00
|
|
|
|
2015-10-07 02:26:50 +02:00
|
|
|
# Load integer from memory into x87 top-of-stack register.
|
|
|
|
# Used to implement fild instruction.
|
|
|
|
defineMicroLoadOp('Ldifp87', code='''
|
|
|
|
switch (dataSize)
|
|
|
|
{
|
|
|
|
case 2:
|
|
|
|
FpData_df = (int64_t)sext<16>(Mem);
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
FpData_df = (int64_t)sext<32>(Mem);
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
FpData_df = (int64_t)Mem;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
panic("Unhandled data size in LdIFp87.\\n");
|
|
|
|
}
|
|
|
|
''', big = False)
|
|
|
|
|
2016-02-07 02:21:20 +01:00
|
|
|
def defineMicroLoadSplitOp(mnemonic, code, mem_flags="0", nonSpec=False):
|
|
|
|
global header_output
|
|
|
|
global decoder_output
|
|
|
|
global exec_output
|
|
|
|
global microopClasses
|
|
|
|
Name = mnemonic
|
|
|
|
name = mnemonic.lower()
|
|
|
|
|
|
|
|
iop = InstObjParams(name, Name, 'X86ISA::LdStSplitOp',
|
|
|
|
{ "code": code,
|
|
|
|
"ea_code": calculateEA,
|
|
|
|
"memDataSize": "2 * dataSize" })
|
|
|
|
|
|
|
|
header_output += MicroLdStSplitOpDeclare.subst(iop)
|
|
|
|
decoder_output += MicroLdStSplitOpConstructor.subst(iop)
|
|
|
|
exec_output += MicroLoadExecute.subst(iop)
|
|
|
|
exec_output += MicroLoadInitiateAcc.subst(iop)
|
|
|
|
exec_output += MicroLoadCompleteAcc.subst(iop)
|
|
|
|
|
|
|
|
class LoadOp(LdStSplitOp):
|
|
|
|
def __init__(self, data, segment, addr, disp = 0,
|
|
|
|
dataSize="env.dataSize",
|
|
|
|
addressSize="env.addressSize",
|
2017-02-10 17:19:34 +01:00
|
|
|
atCPL0=False, prefetch=False, nonSpec=nonSpec,
|
|
|
|
implicitStack=False):
|
2016-02-07 02:21:20 +01:00
|
|
|
super(LoadOp, self).__init__(data, segment, addr,
|
|
|
|
disp, dataSize, addressSize, mem_flags,
|
2017-02-10 17:19:34 +01:00
|
|
|
atCPL0, prefetch, nonSpec, implicitStack)
|
2016-02-07 02:21:20 +01:00
|
|
|
self.className = Name
|
|
|
|
self.mnemonic = name
|
|
|
|
|
|
|
|
microopClasses[name] = LoadOp
|
|
|
|
|
|
|
|
code = '''
|
|
|
|
switch (dataSize) {
|
|
|
|
case 4:
|
|
|
|
DataLow = bits(Mem_u2qw[0], 31, 0);
|
|
|
|
DataHi = bits(Mem_u2qw[0], 63, 32);
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
DataLow = Mem_u2qw[0];
|
|
|
|
DataHi = Mem_u2qw[1];
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
panic("Unhandled data size %d in LdSplit.\\n", dataSize);
|
|
|
|
}'''
|
|
|
|
|
|
|
|
defineMicroLoadSplitOp('LdSplit', code,
|
|
|
|
'(StoreCheck << FlagShift)')
|
|
|
|
|
|
|
|
defineMicroLoadSplitOp('LdSplitl', code,
|
|
|
|
'(StoreCheck << FlagShift) | Request::LOCKED_RMW',
|
|
|
|
nonSpec=True)
|
|
|
|
|
2017-02-10 17:19:34 +01:00
|
|
|
def defineMicroStoreOp(mnemonic, code, completeCode="", mem_flags="0",
|
|
|
|
implicitStack=False):
|
2007-06-19 16:18:25 +02:00
|
|
|
global header_output
|
|
|
|
global decoder_output
|
|
|
|
global exec_output
|
|
|
|
global microopClasses
|
|
|
|
Name = mnemonic
|
|
|
|
name = mnemonic.lower()
|
|
|
|
|
|
|
|
# Build up the all register version of this micro op
|
2007-07-15 02:14:19 +02:00
|
|
|
iop = InstObjParams(name, Name, 'X86ISA::LdStOp',
|
2016-02-07 02:21:20 +01:00
|
|
|
{ "code": code,
|
|
|
|
"complete_code": completeCode,
|
|
|
|
"ea_code": calculateEA,
|
|
|
|
"memDataSize": "dataSize" })
|
2007-06-19 16:18:25 +02:00
|
|
|
header_output += MicroLdStOpDeclare.subst(iop)
|
|
|
|
decoder_output += MicroLdStOpConstructor.subst(iop)
|
|
|
|
exec_output += MicroStoreExecute.subst(iop)
|
|
|
|
exec_output += MicroStoreInitiateAcc.subst(iop)
|
|
|
|
exec_output += MicroStoreCompleteAcc.subst(iop)
|
|
|
|
|
2017-02-10 17:19:34 +01:00
|
|
|
if implicitStack:
|
|
|
|
# For instructions that implicitly access the stack, the address
|
|
|
|
# size is the same as the stack segment pointer size, not the
|
|
|
|
# address size if specified by the instruction prefix
|
|
|
|
addressSize = "env.stackSize"
|
|
|
|
else:
|
|
|
|
addressSize = "env.addressSize"
|
|
|
|
|
2007-06-19 16:18:25 +02:00
|
|
|
class StoreOp(LdStOp):
|
2007-10-13 01:37:55 +02:00
|
|
|
def __init__(self, data, segment, addr, disp = 0,
|
2009-02-25 19:18:22 +01:00
|
|
|
dataSize="env.dataSize",
|
2017-02-10 17:19:34 +01:00
|
|
|
addressSize=addressSize,
|
|
|
|
atCPL0=False, nonSpec=False, implicitStack=implicitStack):
|
2011-03-02 07:42:59 +01:00
|
|
|
super(StoreOp, self).__init__(data, segment, addr, disp,
|
|
|
|
dataSize, addressSize, mem_flags, atCPL0, False,
|
2017-02-10 17:19:34 +01:00
|
|
|
nonSpec, implicitStack)
|
2007-06-19 16:18:25 +02:00
|
|
|
self.className = Name
|
|
|
|
self.mnemonic = name
|
|
|
|
|
|
|
|
microopClasses[name] = StoreOp
|
|
|
|
|
2009-02-25 19:19:14 +01:00
|
|
|
defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);')
|
2017-02-10 17:19:34 +01:00
|
|
|
defineMicroStoreOp('Stis', 'Mem = pick(Data, 2, dataSize);',
|
|
|
|
implicitStack=True)
|
2009-04-19 13:55:58 +02:00
|
|
|
defineMicroStoreOp('Stul', 'Mem = pick(Data, 2, dataSize);',
|
2015-03-24 00:14:20 +01:00
|
|
|
mem_flags="Request::LOCKED_RMW")
|
2013-09-30 12:00:20 +02:00
|
|
|
|
|
|
|
defineMicroStoreOp('Stfp', code='Mem = FpData_uqw;')
|
|
|
|
|
|
|
|
defineMicroStoreOp('Stfp87', code='''
|
|
|
|
switch (dataSize)
|
|
|
|
{
|
|
|
|
case 4: {
|
|
|
|
float single(FpData_df);
|
|
|
|
Mem = *(uint32_t *)&single;
|
|
|
|
} break;
|
|
|
|
case 8:
|
|
|
|
Mem = *(uint64_t *)&FpData_df;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
panic("Unhandled data size in StFp87.\\n");
|
|
|
|
}
|
|
|
|
''')
|
|
|
|
|
2009-02-25 19:15:56 +01:00
|
|
|
defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags="Request::NO_ACCESS")
|
2007-06-20 17:02:50 +02:00
|
|
|
|
2016-02-07 02:21:20 +01:00
|
|
|
def defineMicroStoreSplitOp(mnemonic, code,
|
|
|
|
completeCode="", mem_flags="0"):
|
|
|
|
global header_output
|
|
|
|
global decoder_output
|
|
|
|
global exec_output
|
|
|
|
global microopClasses
|
|
|
|
Name = mnemonic
|
|
|
|
name = mnemonic.lower()
|
|
|
|
|
|
|
|
iop = InstObjParams(name, Name, 'X86ISA::LdStSplitOp',
|
|
|
|
{ "code": code,
|
|
|
|
"complete_code": completeCode,
|
|
|
|
"ea_code": calculateEA,
|
|
|
|
"memDataSize": "2 * dataSize" })
|
|
|
|
|
|
|
|
header_output += MicroLdStSplitOpDeclare.subst(iop)
|
|
|
|
decoder_output += MicroLdStSplitOpConstructor.subst(iop)
|
|
|
|
exec_output += MicroStoreExecute.subst(iop)
|
|
|
|
exec_output += MicroStoreInitiateAcc.subst(iop)
|
|
|
|
exec_output += MicroStoreCompleteAcc.subst(iop)
|
|
|
|
|
|
|
|
class StoreOp(LdStSplitOp):
|
|
|
|
def __init__(self, data, segment, addr, disp = 0,
|
|
|
|
dataSize="env.dataSize",
|
|
|
|
addressSize="env.addressSize",
|
2017-02-10 17:19:34 +01:00
|
|
|
atCPL0=False, nonSpec=False, implicitStack=False):
|
2016-02-07 02:21:20 +01:00
|
|
|
super(StoreOp, self).__init__(data, segment, addr, disp,
|
|
|
|
dataSize, addressSize, mem_flags, atCPL0, False,
|
2017-02-10 17:19:34 +01:00
|
|
|
nonSpec, implicitStack)
|
2016-02-07 02:21:20 +01:00
|
|
|
self.className = Name
|
|
|
|
self.mnemonic = name
|
|
|
|
|
|
|
|
microopClasses[name] = StoreOp
|
|
|
|
|
|
|
|
code = '''
|
|
|
|
switch (dataSize) {
|
|
|
|
case 4:
|
|
|
|
Mem_u2qw[0] = (DataHi << 32) | DataLow;
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
Mem_u2qw[0] = DataLow;
|
|
|
|
Mem_u2qw[1] = DataHi;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
panic("Unhandled data size %d in StSplit.\\n", dataSize);
|
|
|
|
}'''
|
|
|
|
|
|
|
|
defineMicroStoreSplitOp('StSplit', code);
|
|
|
|
|
|
|
|
defineMicroStoreSplitOp('StSplitul', code,
|
|
|
|
mem_flags='Request::LOCKED_RMW')
|
|
|
|
|
2007-07-15 02:14:19 +02:00
|
|
|
iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp',
|
2016-02-07 02:21:20 +01:00
|
|
|
{ "code": "Data = merge(Data, EA, dataSize);",
|
|
|
|
"ea_code": "EA = " + segmentEAExpr,
|
|
|
|
"memDataSize": "dataSize" })
|
2007-06-20 17:02:50 +02:00
|
|
|
header_output += MicroLeaDeclare.subst(iop)
|
|
|
|
decoder_output += MicroLdStOpConstructor.subst(iop)
|
|
|
|
exec_output += MicroLeaExecute.subst(iop)
|
|
|
|
|
|
|
|
class LeaOp(LdStOp):
|
2007-10-13 01:37:55 +02:00
|
|
|
def __init__(self, data, segment, addr, disp = 0,
|
|
|
|
dataSize="env.dataSize", addressSize="env.addressSize"):
|
2011-03-02 07:42:59 +01:00
|
|
|
super(LeaOp, self).__init__(data, segment, addr, disp,
|
2017-02-10 17:19:34 +01:00
|
|
|
dataSize, addressSize, "0", False, False, False, False)
|
2007-06-20 17:02:50 +02:00
|
|
|
self.className = "Lea"
|
|
|
|
self.mnemonic = "lea"
|
|
|
|
|
|
|
|
microopClasses["lea"] = LeaOp
|
2007-10-22 23:30:56 +02:00
|
|
|
|
|
|
|
|
2008-02-27 05:39:22 +01:00
|
|
|
iop = InstObjParams("tia", "Tia", 'X86ISA::LdStOp',
|
2016-02-07 02:21:20 +01:00
|
|
|
{ "code": "xc->demapPage(EA, 0);",
|
|
|
|
"ea_code": calculateEA,
|
|
|
|
"memDataSize": "dataSize" })
|
2008-02-27 05:39:22 +01:00
|
|
|
header_output += MicroLeaDeclare.subst(iop)
|
|
|
|
decoder_output += MicroLdStOpConstructor.subst(iop)
|
|
|
|
exec_output += MicroLeaExecute.subst(iop)
|
|
|
|
|
|
|
|
class TiaOp(LdStOp):
|
|
|
|
def __init__(self, segment, addr, disp = 0,
|
2009-02-25 19:18:22 +01:00
|
|
|
dataSize="env.dataSize",
|
|
|
|
addressSize="env.addressSize"):
|
2009-07-16 18:29:29 +02:00
|
|
|
super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
|
2011-03-02 07:42:59 +01:00
|
|
|
addr, disp, dataSize, addressSize, "0", False, False,
|
2017-02-10 17:19:34 +01:00
|
|
|
False, False)
|
2008-02-27 05:39:22 +01:00
|
|
|
self.className = "Tia"
|
|
|
|
self.mnemonic = "tia"
|
|
|
|
|
|
|
|
microopClasses["tia"] = TiaOp
|
|
|
|
|
2007-10-22 23:30:56 +02:00
|
|
|
class CdaOp(LdStOp):
|
|
|
|
def __init__(self, segment, addr, disp = 0,
|
2009-02-25 19:18:22 +01:00
|
|
|
dataSize="env.dataSize",
|
|
|
|
addressSize="env.addressSize", atCPL0=False):
|
2009-07-16 18:29:29 +02:00
|
|
|
super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
|
2009-08-23 23:16:58 +02:00
|
|
|
addr, disp, dataSize, addressSize, "Request::NO_ACCESS",
|
2017-02-10 17:19:34 +01:00
|
|
|
atCPL0, False, False, False)
|
2007-10-22 23:30:56 +02:00
|
|
|
self.className = "Cda"
|
|
|
|
self.mnemonic = "cda"
|
|
|
|
|
|
|
|
microopClasses["cda"] = CdaOp
|
2007-06-19 16:18:25 +02:00
|
|
|
}};
|