x86: Add support for loading 32-bit and 80-bit floats in the x87
The x87 FPU supports three floating point formats: 32-bit, 64-bit, and 80-bit floats. The current gem5 implementation supports 32-bit and 64-bit floats, but only works correctly for 64-bit floats. This changeset fixes the 32-bit float handling by correctly loading and rounding (using truncation) 32-bit floats instead of simply truncating the bit pattern. 80-bit floats are loaded by first loading the 80-bits of the float to two temporary integer registers. A micro-op (cvtint_fp80) then converts the contents of the two integer registers to the internal FP representation (double). Similarly, when storing an 80-bit float, there are two conversion routines (ctvfp80h_int and cvtfp80l_int) that convert an internal FP register to 80-bit and stores the upper 64-bits or lower 32-bits to an integer register, which is the written to memory using normal integer stores.
This commit is contained in:
Andreas Sandberg
parent
c299dcedc6
commit
654d1e675a
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@ -67,11 +67,11 @@ format WarnUnimpl {
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0x0: fnop();
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default: Inst::UD2();
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}
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default: fst();
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default: Inst::FST(Ed);
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}
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0x3: decode MODRM_MOD {
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0x3: Inst::UD2();
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default: fstp();
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default: Inst::FSTP(Ed);
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}
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0x4: decode MODRM_MOD {
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0x3: decode MODRM_RM {
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@ -189,7 +189,7 @@ format WarnUnimpl {
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0x5: decode MODRM_MOD {
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0x3: fucomi();
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// 80-bit load
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default: fld();
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default: Inst::FLD80(M);
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}
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0x6: decode MODRM_MOD {
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0x3: fcomi();
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@ -197,7 +197,7 @@ format WarnUnimpl {
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}
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0x7: decode MODRM_MOD {
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0x3: Inst::UD2();
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default: fstp();
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default: Inst::FST80P(M);
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}
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}
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//0x4: esc4();
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@ -37,13 +37,13 @@
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microcode = '''
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def macroop FLD_M {
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ldfp ufp1, seg, sib, disp
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ldfp87 ufp1, seg, sib, disp
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movfp st(-1), ufp1, spm=-1
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};
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def macroop FLD_P {
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rdip t7
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ldfp ufp1, seg, riprel, disp
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ldfp87 ufp1, seg, riprel, disp
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movfp st(-1), ufp1, spm=-1
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};
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@ -51,17 +51,30 @@ def macroop FLD_R {
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movfp st(-1), sti, spm=-1
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};
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def macroop FLD80_M {
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ld t1, seg, sib, "DISPLACEMENT", dataSize=8
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ld t2, seg, sib, "DISPLACEMENT + 8", dataSize=2
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cvtint_fp80 st(-1), t1, t2, spm=-1
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};
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def macroop FLD80_P {
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rdip t7
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ld t1, seg, riprel, "DISPLACEMENT", dataSize=8
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ld t2, seg, riprel, "DISPLACEMENT + 8", dataSize=2
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cvtint_fp80 st(-1), t1, t2, spm=-1
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};
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def macroop FST_R {
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movfp sti, st(0)
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};
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def macroop FST_M {
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stfp st(0), seg, sib, disp
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stfp87 st(0), seg, sib, disp
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};
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def macroop FST_P {
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rdip t7
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stfp st(0), seg, riprel, disp
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stfp87 st(0), seg, riprel, disp
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};
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def macroop FSTP_R {
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@ -70,14 +83,32 @@ def macroop FSTP_R {
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def macroop FSTP_M {
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movfp ufp1, st(0)
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stfp ufp1, seg, sib, disp
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stfp87 ufp1, seg, sib, disp
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pop87
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};
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def macroop FSTP_P {
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movfp ufp1, st(0)
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rdip t7
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stfp ufp1, seg, riprel, disp
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stfp87 ufp1, seg, riprel, disp
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pop87
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};
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def macroop FST80P_M {
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cvtfp80h_int t1, st(0)
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cvtfp80l_int t2, st(0)
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st t1, seg, sib, "DISPLACEMENT + 0", dataSize=8
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st t2, seg, sib, "DISPLACEMENT + 8", dataSize=2
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pop87
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};
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def macroop FST80P_P {
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rdip t7
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cvtfp80h_int t1, st(0)
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cvtfp80l_int t2, st(0)
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st t1, seg, riprel, "DISPLACEMENT + 0", dataSize=8
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st t2, seg, riprel, "DISPLACEMENT + 8", dataSize=2
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pop87
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};
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'''
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@ -295,9 +295,10 @@ let {{
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class ConvOp(FpBinaryOp):
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abstract = True
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op_class = 'FloatCvtOp'
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def __init__(self, dest, src1):
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def __init__(self, dest, src1, **kwargs):
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super(ConvOp, self).__init__(dest, src1, \
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"InstRegIndex(FLOATREG_MICROFP0)")
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"InstRegIndex(FLOATREG_MICROFP0)", \
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**kwargs)
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# These probably shouldn't look at the ExtMachInst directly to figure
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# out what size to use and should instead delegate that to the macroop's
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@ -324,6 +325,34 @@ let {{
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SDestReg = merge(SDestReg, intSrcReg1, 4);
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'''
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# Convert two integers registers representing an 80-bit floating
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# point number to an x87 register.
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class cvtint_fp80(FpBinaryOp):
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code = '''
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uint8_t bits[10];
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*(uint64_t *)(bits + 0) = SSrcReg1;
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*(uint16_t *)(bits + 8) = (uint16_t)SSrcReg2;
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FpDestReg = loadFloat80(bits);
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'''
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# Convert an x87 register (double) into extended precision and
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# extract the highest 64 bits.
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class cvtfp80h_int(ConvOp):
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code = '''
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char bits[10];
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storeFloat80(bits, FpSrcReg1);
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SDestReg = *(uint64_t *)(bits + 0);
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'''
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# Convert an x87 register (double) into extended precision and
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# extract the lowest 16 bits.
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class cvtfp80l_int(ConvOp):
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code = '''
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char bits[10];
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storeFloat80(bits, FpSrcReg1);
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SDestReg = *(uint16_t *)(bits + 8);
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'''
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# These need to consider size at some point. They'll always use doubles
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# for the moment.
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class addfp(FpBinaryOp):
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@ -410,7 +410,22 @@ let {{
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defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);',
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'Data = Mem & mask(dataSize * 8);',
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'(StoreCheck << FlagShift) | Request::LOCKED')
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defineMicroLoadOp('Ldfp', 'FpData_uqw = Mem;', big = False)
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defineMicroLoadOp('Ldfp', code='FpData_uqw = Mem', big = False)
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defineMicroLoadOp('Ldfp87', code='''
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switch (dataSize)
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{
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case 4:
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FpData_df = *(float *)&Mem;
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break;
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case 8:
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FpData_df = *(double *)&Mem;
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break;
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default:
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panic("Unhandled data size in LdFp87.\\n");
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}
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''', big = False)
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def defineMicroStoreOp(mnemonic, code, completeCode="", mem_flags="0"):
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global header_output
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@ -447,7 +462,24 @@ let {{
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defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);')
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defineMicroStoreOp('Stul', 'Mem = pick(Data, 2, dataSize);',
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mem_flags="Request::LOCKED")
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defineMicroStoreOp('Stfp', 'Mem = FpData_uqw;')
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defineMicroStoreOp('Stfp', code='Mem = FpData_uqw;')
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defineMicroStoreOp('Stfp87', code='''
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switch (dataSize)
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{
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case 4: {
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float single(FpData_df);
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Mem = *(uint32_t *)&single;
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} break;
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case 8:
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Mem = *(uint64_t *)&FpData_df;
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break;
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default:
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panic("Unhandled data size in StFp87.\\n");
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}
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''')
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defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags="Request::NO_ACCESS")
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iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp',
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