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Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
# -*- mode:python -*-
Many files: Update copyright dates and author list SConscript: arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_linux_process.hh: arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: arch/alpha/alpha_tru64_process.cc: arch/alpha/alpha_tru64_process.hh: arch/alpha/aout_machdep.h: arch/alpha/arguments.cc: arch/alpha/arguments.hh: arch/alpha/ev5.cc: arch/alpha/ev5.hh: arch/alpha/faults.cc: arch/alpha/faults.hh: arch/alpha/isa_desc: arch/alpha/isa_traits.hh: arch/alpha/osfpal.cc: arch/alpha/osfpal.hh: arch/alpha/pseudo_inst.cc: arch/alpha/pseudo_inst.hh: arch/alpha/vptr.hh: arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: base/bitfield.hh: base/callback.hh: base/circlebuf.cc: base/circlebuf.hh: base/cprintf.cc: base/cprintf.hh: base/cprintf_formats.hh: base/crc.hh: base/date.cc: base/dbl_list.hh: base/endian.hh: base/fast_alloc.cc: base/fast_alloc.hh: base/fifo_buffer.cc: base/fifo_buffer.hh: base/hashmap.hh: base/hostinfo.cc: base/hostinfo.hh: base/hybrid_pred.cc: base/hybrid_pred.hh: base/inet.cc: base/inet.hh: base/inifile.cc: base/inifile.hh: base/intmath.cc: base/intmath.hh: base/match.cc: base/match.hh: base/misc.cc: base/misc.hh: base/mod_num.hh: base/mysql.cc: base/mysql.hh: base/output.cc: base/output.hh: base/pollevent.cc: base/pollevent.hh: base/predictor.hh: base/random.cc: base/random.hh: base/range.cc: base/range.hh: base/refcnt.hh: base/remote_gdb.cc: base/remote_gdb.hh: base/res_list.hh: base/sat_counter.cc: base/sat_counter.hh: base/sched_list.hh: base/socket.cc: base/socket.hh: base/statistics.cc: base/statistics.hh: base/compression/lzss_compression.cc: base/compression/lzss_compression.hh: base/compression/null_compression.hh: base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/object_file.cc: base/loader/object_file.hh: base/loader/symtab.cc: base/loader/symtab.hh: base/stats/events.cc: base/stats/events.hh: base/stats/flags.hh: base/stats/mysql.cc: base/stats/mysql.hh: base/stats/mysql_run.hh: base/stats/output.hh: base/stats/statdb.cc: base/stats/statdb.hh: base/stats/text.cc: base/stats/text.hh: base/stats/types.hh: base/stats/visit.cc: base/stats/visit.hh: base/str.cc: base/str.hh: base/time.cc: base/time.hh: base/timebuf.hh: base/trace.cc: base/trace.hh: base/userinfo.cc: base/userinfo.hh: build/SConstruct: cpu/base.cc: cpu/base.hh: cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/exetrace.cc: cpu/exetrace.hh: cpu/inst_seq.hh: cpu/intr_control.cc: cpu/intr_control.hh: cpu/memtest/memtest.cc: cpu/pc_event.cc: cpu/pc_event.hh: cpu/smt.hh: cpu/static_inst.cc: cpu/static_inst.hh: cpu/memtest/memtest.hh: cpu/o3/sat_counter.cc: cpu/o3/sat_counter.hh: cpu/ozone/cpu.hh: cpu/simple/cpu.cc: cpu/simple/cpu.hh: cpu/trace/opt_cpu.cc: cpu/trace/opt_cpu.hh: cpu/trace/reader/ibm_reader.cc: cpu/trace/reader/ibm_reader.hh: cpu/trace/reader/itx_reader.cc: cpu/trace/reader/itx_reader.hh: cpu/trace/reader/m5_reader.cc: cpu/trace/reader/m5_reader.hh: cpu/trace/reader/mem_trace_reader.cc: cpu/trace/reader/mem_trace_reader.hh: cpu/trace/trace_cpu.cc: cpu/trace/trace_cpu.hh: dev/alpha_access.h: dev/alpha_console.cc: dev/alpha_console.hh: dev/baddev.cc: dev/baddev.hh: dev/disk_image.cc: dev/disk_image.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.cc: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/ns_gige.cc: dev/ns_gige.hh: dev/ns_gige_reg.h: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: dev/pcireg.h: dev/pktfifo.cc: dev/pktfifo.hh: dev/platform.cc: dev/platform.hh: dev/simconsole.cc: dev/simconsole.hh: dev/simple_disk.cc: dev/simple_disk.hh: dev/sinic.cc: dev/sinic.hh: dev/sinicreg.hh: dev/tsunami.cc: dev/tsunami.hh: dev/tsunami_cchip.cc: dev/tsunami_cchip.hh: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/tsunamireg.h: dev/uart.cc: dev/uart.hh: dev/uart8250.cc: dev/uart8250.hh: docs/stl.hh: encumbered/cpu/full/op_class.hh: kern/kernel_stats.cc: kern/kernel_stats.hh: kern/linux/linux.hh: kern/linux/linux_syscalls.cc: kern/linux/linux_syscalls.hh: kern/linux/linux_system.cc: kern/linux/linux_system.hh: kern/linux/linux_threadinfo.hh: kern/linux/printk.cc: kern/linux/printk.hh: kern/system_events.cc: kern/system_events.hh: kern/tru64/dump_mbuf.cc: kern/tru64/dump_mbuf.hh: kern/tru64/mbuf.hh: kern/tru64/printf.cc: kern/tru64/printf.hh: kern/tru64/tru64.hh: kern/tru64/tru64_events.cc: kern/tru64/tru64_events.hh: kern/tru64/tru64_syscalls.cc: kern/tru64/tru64_syscalls.hh: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: python/SConscript: python/m5/__init__.py: python/m5/config.py: python/m5/convert.py: python/m5/multidict.py: python/m5/smartdict.py: sim/async.hh: sim/builder.cc: sim/builder.hh: sim/debug.cc: sim/debug.hh: sim/eventq.cc: sim/eventq.hh: sim/host.hh: sim/main.cc: sim/param.cc: sim/param.hh: sim/process.cc: sim/process.hh: sim/root.cc: sim/serialize.cc: sim/serialize.hh: sim/sim_events.cc: sim/sim_events.hh: sim/sim_exit.hh: sim/sim_object.cc: sim/sim_object.hh: sim/startup.cc: sim/startup.hh: sim/stat_control.cc: sim/stat_control.hh: sim/stats.hh: sim/syscall_emul.cc: sim/syscall_emul.hh: sim/system.cc: sim/system.hh: test/bitvectest.cc: test/circletest.cc: test/cprintftest.cc: test/genini.py: test/initest.cc: test/lru_test.cc: test/nmtest.cc: test/offtest.cc: test/paramtest.cc: test/rangetest.cc: test/sized_test.cc: test/stattest.cc: test/strnumtest.cc: test/symtest.cc: test/tokentest.cc: test/tracetest.cc: util/ccdrv/devtime.c: util/m5/m5.c: util/oprofile-top.py: util/rundiff: util/m5/m5op.h: util/m5/m5op.s: util/stats/db.py: util/stats/dbinit.py: util/stats/display.py: util/stats/info.py: util/stats/print.py: util/stats/stats.py: util/tap/tap.cc: Update copyright dates and author list --HG-- extra : convert_revision : 0faba08fc0fc0146f1efb7f61e4b043c020ff9e4
2005-06-05 11:16:00 +02:00
# Copyright (c) 2004-2005 The Regents of The University of Michigan
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Updated Authors from bk prs info --HG-- extra : convert_revision : 77f475b156d81c03a2811818fa23593d5615c685
2006-06-01 01:26:56 +02:00
#
# Authors: Steve Reinhardt
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
import os
import sys
If we find the mysql libraries on the machine, just compile with mysql and remove the special compile type. SConscript: If we find the mysql libraries on the machine, just compile with mysql. build/SConstruct: we always use mysql, and we got rid of the FS_MEASURE --HG-- extra : convert_revision : a7c4277c890e1b6390ef06288114c9bdde11b178
2005-03-28 07:41:28 +02:00
from os.path import isdir
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
# This file defines how to build a particular configuration of M5
# based on variable settings in the 'env' build environment.
# Import build environment variable from SConstruct.
Import('env')
###################################################
#
# Define needed sources.
#
###################################################
# Base sources used by all configurations.
Some stuff aparently didn't get committed which was from before the new repository was created. SConscript: There is a new SConscript in the arch/alpha directory which has the alpha specific files. To add files for an arch, a similar file should be created. arch/isa_parser.py: The isa parser now supports include directives. These are done with ##include build/SConstruct: The target directory is passed on so that the architecture specific SConscript can have it. Also, sparc was added as a valid architecture type. arch/alpha/SConscript: This SConscript adds the alpha specific source arch/sparc/isa_desc/operands.h: This sets up the operand types that the sparc isa uses arch/sparc/isa_traits.cc: Implementation of sparc specific things, like a register file with windows build/build_options/default/SPARC_SE: The default options for a sparc syscall emulation build. --HG-- extra : convert_revision : 1afedae61dc8cae0d59d3bf1d41420d929be2efd
2006-01-25 01:57:17 +01:00
base_sources = Split('''
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
base/circlebuf.cc
base/cprintf.cc
base/fast_alloc.cc
base/fifo_buffer.cc
base/hostinfo.cc
base/hybrid_pred.cc
base/inifile.cc
base/intmath.cc
Move all of the object matching code to a shared file so it can be more easily re-used. This currently uses some cooked up matching function that I wrote a while ago, but should probably be changed to use regular expressions in the future. add doDebugBreak to control breakpoints on a per SimObject basis SConscript: add match base/stats/events.cc: base/trace.cc: Move the object matching code into a separate file so it can be more easily shared base/trace.hh: the object matching code was wrapped up and moved. adapt. sim/sim_object.cc: add the doDebugBreak flag that can be set on a per-SimObject basis. This will be used in the future to control whether or not debug_break() will actually break for a given object. provide a function interface that can be called from the debugger. sim/sim_object.hh: add the doDebugBreak flag that can be set on a per-SimObject basis. This will be used in the future to control whether or not debug_break() will actually break for a given object. --HG-- extra : convert_revision : 6bf7924de63d41f5ba6b80d579efdf26ba265a8f
2004-07-30 16:47:53 +02:00
base/match.cc
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
base/misc.cc
Rework the command line paramters for python output and how output files and the output directory are are handled. Make the output directory configuration via a command line parameter, or an environment variable. SConscript: Add new output file stuff base/misc.cc: dev/simconsole.cc: use new output file code cpu/base_cpu.cc: use new output file code to generate output streams dev/etherdump.cc: use the output file code to find the output directory use a real stream instead of a pointer dev/etherdump.hh: use a real stream instead of a pointer objects/Root.mpy: output_dir and config_output_file are not longer configured here. sim/main.cc: - Completely rework the command line argument passing to deal with changes in python and output files. - Update help output to reflect changes. - Remove all direct support for .ini files. They are strictly for intermediate representation. - Remove the --foo:bar=blah syntax for .ini files and add --foo.bar=blah syntax for python. This will generate: foo.bar = 'blah' in the python script. - Add '-d' to set the output directory. - Use new output file code to access the output stream. sim/serialize.cc: use the new code to find the output directory sim/universe.cc: Get rid of makeOutputStream. Use the new output file code. Remove output_dir and config_output_file as parameters. --HG-- extra : convert_revision : df2f0e13d401c3a60cae1239aa1ec3511721544d
2005-02-11 15:47:41 +01:00
base/output.cc
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
base/pollevent.cc
base/range.cc
Fix up the random number stuff. SConscript: compile the random number generator stuff into m5 base/random.cc: we need to define our destructor base/random.hh: Since there's no state, just makes all of these get functions static --HG-- extra : convert_revision : 9d4b8abd57367391a8ecda3914b1d912d9c64185
2004-12-13 18:55:13 +01:00
base/random.cc
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
base/sat_counter.cc
base/socket.cc
base/statistics.cc
base/str.cc
base/time.cc
base/trace.cc
base/traceflags.cc
base/userinfo.cc
base/compression/lzss_compression.cc
base/loader/aout_object.cc
base/loader/ecoff_object.cc
base/loader/elf_object.cc
base/loader/object_file.cc
base/loader/symtab.cc
base/stats/events.cc
base/stats/statdb.cc
base/stats/visit.cc
base/stats/text.cc
Move activity tracking code into its own class. Now the CPU no longer has to keep track of the activity tracking internals; it just calls advance() on the class and uses it to tell if it should deschedule itself. SConscript: Split off activity/idling code into its own class to do the processing separately. cpu/o3/alpha_cpu_builder.cc: cpu/o3/alpha_params.hh: Activity stuff. This is mostly for debugging and may be removed later on (or changed to enable/disable activity idling). cpu/o3/cpu.cc: Move activity idling stuff mostly into its own class, so it no longer clutters this file. cpu/o3/cpu.hh: Move activity idling stuff into its own class. python/m5/objects/AlphaFullCPU.py: Add parameter for initial activity value. --HG-- extra : convert_revision : f32f7cc03895dc07ab57ddba78c5402a1a8b0f1a
2006-05-19 21:37:52 +02:00
cpu/activity.cc
shuffle files around for new directory structure --HG-- rename : cpu/base_cpu.cc => cpu/base.cc rename : cpu/base_cpu.hh => cpu/base.hh rename : cpu/beta_cpu/2bit_local_pred.cc => cpu/o3/2bit_local_pred.cc rename : cpu/beta_cpu/2bit_local_pred.hh => cpu/o3/2bit_local_pred.hh rename : cpu/beta_cpu/alpha_full_cpu.cc => cpu/o3/alpha_cpu.cc rename : cpu/beta_cpu/alpha_full_cpu.hh => cpu/o3/alpha_cpu.hh rename : cpu/beta_cpu/alpha_full_cpu_builder.cc => cpu/o3/alpha_cpu_builder.cc rename : cpu/beta_cpu/alpha_full_cpu_impl.hh => cpu/o3/alpha_cpu_impl.hh rename : cpu/beta_cpu/alpha_dyn_inst.cc => cpu/o3/alpha_dyn_inst.cc rename : cpu/beta_cpu/alpha_dyn_inst.hh => cpu/o3/alpha_dyn_inst.hh rename : cpu/beta_cpu/alpha_dyn_inst_impl.hh => cpu/o3/alpha_dyn_inst_impl.hh rename : cpu/beta_cpu/alpha_impl.hh => cpu/o3/alpha_impl.hh rename : cpu/beta_cpu/alpha_params.hh => cpu/o3/alpha_params.hh rename : cpu/beta_cpu/bpred_unit.cc => cpu/o3/bpred_unit.cc rename : cpu/beta_cpu/bpred_unit.hh => cpu/o3/bpred_unit.hh rename : cpu/beta_cpu/bpred_unit_impl.hh => cpu/o3/bpred_unit_impl.hh rename : cpu/beta_cpu/btb.cc => cpu/o3/btb.cc rename : cpu/beta_cpu/btb.hh => cpu/o3/btb.hh rename : cpu/beta_cpu/comm.hh => cpu/o3/comm.hh rename : cpu/beta_cpu/commit.cc => cpu/o3/commit.cc rename : cpu/beta_cpu/commit.hh => cpu/o3/commit.hh rename : cpu/beta_cpu/commit_impl.hh => cpu/o3/commit_impl.hh rename : cpu/beta_cpu/full_cpu.cc => cpu/o3/cpu.cc rename : cpu/beta_cpu/full_cpu.hh => cpu/o3/cpu.hh rename : cpu/beta_cpu/cpu_policy.hh => cpu/o3/cpu_policy.hh rename : cpu/beta_cpu/decode.cc => cpu/o3/decode.cc rename : cpu/beta_cpu/decode.hh => cpu/o3/decode.hh rename : cpu/beta_cpu/decode_impl.hh => cpu/o3/decode_impl.hh rename : cpu/beta_cpu/fetch.cc => cpu/o3/fetch.cc rename : cpu/beta_cpu/fetch.hh => cpu/o3/fetch.hh rename : cpu/beta_cpu/fetch_impl.hh => cpu/o3/fetch_impl.hh rename : cpu/beta_cpu/free_list.cc => cpu/o3/free_list.cc rename : cpu/beta_cpu/free_list.hh => cpu/o3/free_list.hh rename : cpu/beta_cpu/iew.cc => cpu/o3/iew.cc rename : cpu/beta_cpu/iew.hh => cpu/o3/iew.hh rename : cpu/beta_cpu/iew_impl.hh => cpu/o3/iew_impl.hh rename : cpu/beta_cpu/inst_queue.cc => cpu/o3/inst_queue.cc rename : cpu/beta_cpu/inst_queue.hh => cpu/o3/inst_queue.hh rename : cpu/beta_cpu/inst_queue_impl.hh => cpu/o3/inst_queue_impl.hh rename : cpu/beta_cpu/mem_dep_unit.cc => cpu/o3/mem_dep_unit.cc rename : cpu/beta_cpu/mem_dep_unit.hh => cpu/o3/mem_dep_unit.hh rename : cpu/beta_cpu/mem_dep_unit_impl.hh => cpu/o3/mem_dep_unit_impl.hh rename : cpu/beta_cpu/ras.cc => cpu/o3/ras.cc rename : cpu/beta_cpu/ras.hh => cpu/o3/ras.hh rename : cpu/beta_cpu/regfile.hh => cpu/o3/regfile.hh rename : cpu/beta_cpu/rename.cc => cpu/o3/rename.cc rename : cpu/beta_cpu/rename.hh => cpu/o3/rename.hh rename : cpu/beta_cpu/rename_impl.hh => cpu/o3/rename_impl.hh rename : cpu/beta_cpu/rename_map.cc => cpu/o3/rename_map.cc rename : cpu/beta_cpu/rename_map.hh => cpu/o3/rename_map.hh rename : cpu/beta_cpu/rob.cc => cpu/o3/rob.cc rename : cpu/beta_cpu/rob.hh => cpu/o3/rob.hh rename : cpu/beta_cpu/rob_impl.hh => cpu/o3/rob_impl.hh rename : cpu/beta_cpu/sat_counter.cc => cpu/o3/sat_counter.cc rename : cpu/beta_cpu/sat_counter.hh => cpu/o3/sat_counter.hh rename : cpu/beta_cpu/store_set.cc => cpu/o3/store_set.cc rename : cpu/beta_cpu/store_set.hh => cpu/o3/store_set.hh rename : cpu/beta_cpu/tournament_pred.cc => cpu/o3/tournament_pred.cc rename : cpu/beta_cpu/tournament_pred.hh => cpu/o3/tournament_pred.hh rename : cpu/ooo_cpu/ooo_cpu.cc => cpu/ozone/cpu.cc rename : cpu/ooo_cpu/ooo_cpu.hh => cpu/ozone/cpu.hh rename : cpu/ooo_cpu/ooo_impl.hh => cpu/ozone/cpu_impl.hh rename : cpu/ooo_cpu/ea_list.cc => cpu/ozone/ea_list.cc rename : cpu/ooo_cpu/ea_list.hh => cpu/ozone/ea_list.hh rename : cpu/simple_cpu/simple_cpu.cc => cpu/simple/cpu.cc rename : cpu/simple_cpu/simple_cpu.hh => cpu/simple/cpu.hh rename : cpu/full_cpu/smt.hh => cpu/smt.hh rename : cpu/full_cpu/op_class.hh => encumbered/cpu/full/op_class.hh extra : convert_revision : c4a891d8d6d3e0e9e5ea56be47d851da44d8c032
2005-06-05 02:50:10 +02:00
cpu/base.cc
commit a couple of minor things that I forgot to last time. src/SConscript: src/arch/sparc/SConscript: commit a couple of things that I forgot to last time. --HG-- extra : convert_revision : f140912905b9d36eccc27e35ebcaf2c15611b56b
2006-05-30 00:25:02 +02:00
cpu/cpuevent.cc
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
cpu/exetrace.cc
Reorganization to move FuncUnit, FUDesc, and OpDesc out of the encumbered directory and into the normal cpu directory. src/SConscript: Split off FuncUnits from old FUPool so I'm not including encumbered code. This was all written by Steve Raasch so it's safe to include in the main tree. src/cpu/o3/fu_pool.cc: Include the func unit file that's not in the encumbered directory. --HG-- extra : convert_revision : 9801c606961dd2d62dba190d13a76069992bf241
2006-06-16 23:52:15 +02:00
cpu/func_unit.cc
Move op_class.hh out of encumbered/cpu/full and into cpu. Pull opClassStrings array out of encumbered/cpu/full/fu_pool.cc and move to new cpu/op_class.cc file. SConscript: Add new cpu-model-independent file to define OpClass enum strings. cpu/op_class.hh: Fix comments etc. cpu/static_inst.hh: op_class.hh moved to cpu directory --HG-- rename : encumbered/cpu/full/op_class.hh => cpu/op_class.hh extra : convert_revision : 314ac5ab7cc5c6a34b43dc1c2f2adc3e02f6d07f
2006-02-22 04:12:27 +01:00
cpu/op_class.cc
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
cpu/pc_event.cc
Move quiesce event to its own class. SConscript: Move quiesce event to its own file/class. --HG-- extra : convert_revision : 6aa7863adb529fc03142666213c3ec348825bd3b
2006-04-23 00:11:54 +02:00
cpu/quiesce_event.cc
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
cpu/static_inst.cc
Reorganization/renaming of CPUExecContext. Now it is called SimpleThread in order to clear up the confusion due to the many ExecContexts. It also derives from a common ThreadState object, which holds various state common to threads across CPU models. Following with the previous check-in, ExecContext now refers only to the interface provided to the ISA in order to access CPU state. ThreadContext refers to the interface provided to all objects outside the CPU in order to access thread state. SimpleThread provides all thread state and the interface to access it, and is suitable for simple execution models such as the SimpleCPU. src/SConscript: Include thread state file. src/arch/alpha/ev5.cc: src/cpu/checker/cpu.cc: src/cpu/checker/cpu.hh: src/cpu/checker/thread_context.hh: src/cpu/memtest/memtest.cc: src/cpu/memtest/memtest.hh: src/cpu/o3/cpu.cc: src/cpu/ozone/cpu_impl.hh: src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: Rename CPUExecContext to SimpleThread. src/cpu/base_dyn_inst.hh: Make thread member variables protected.. src/cpu/o3/alpha_cpu.hh: src/cpu/o3/cpu.hh: Make various members of ThreadState protected. src/cpu/o3/alpha_cpu_impl.hh: Push generation of TranslatingPort into the CPU itself. Make various members of ThreadState protected. src/cpu/o3/thread_state.hh: Pull a lot of common code into the base ThreadState class. src/cpu/ozone/thread_state.hh: Rename CPUExecContext to SimpleThread, move a lot of common code into base ThreadState class. src/cpu/thread_state.hh: Push a lot of common code into base ThreadState class. This goes along with renaming CPUExecContext to SimpleThread, and making it derive from ThreadState. src/cpu/simple_thread.cc: Rename CPUExecContext to SimpleThread, make it derive from ThreadState. This helps push a lot of common code/state into a single class that can be used by all CPUs. src/cpu/simple_thread.hh: Rename CPUExecContext to SimpleThread, make it derive from ThreadState. src/kern/system_events.cc: Rename cpu_exec_context to thread_context. src/sim/process.hh: Remove unused forward declaration. --HG-- rename : src/cpu/cpu_exec_context.cc => src/cpu/simple_thread.cc rename : src/cpu/cpu_exec_context.hh => src/cpu/simple_thread.hh extra : convert_revision : 2ed617aa80b64016cb9270f75352607cca032733
2006-06-07 21:29:53 +02:00
cpu/simple_thread.cc
cpu/thread_state.cc
Fixes to get compiling to work. This is mainly fixing up some includes; changing functions within the XCs; changing MemReqPtrs to Requests or Packets where appropriate. Currently the O3 and Ozone CPUs do not work in the new memory system; I still need to fix up the ports to work and handle responses properly. This check-in is so that the merge between m5 and newmem is no longer outstanding. src/SConscript: Need to include FU Pool for new CPU model. I'll try to figure out a cleaner way to handle this in the future. src/base/traceflags.py: Include new traces flags, fix up merge mess up. src/cpu/SConscript: Include the base_dyn_inst.cc as one of othe sources. Don't compile the Ozone CPU for now. src/cpu/base.cc: Remove an extra } from the merge. src/cpu/base_dyn_inst.cc: Fixes to make compiling work. Don't instantiate the OzoneCPU for now. src/cpu/base_dyn_inst.hh: src/cpu/o3/2bit_local_pred.cc: src/cpu/o3/alpha_cpu_builder.cc: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/o3/alpha_dyn_inst.hh: src/cpu/o3/alpha_params.hh: src/cpu/o3/bpred_unit.cc: src/cpu/o3/btb.hh: src/cpu/o3/commit.hh: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/free_list.hh: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue.hh: src/cpu/o3/inst_queue_impl.hh: src/cpu/o3/regfile.hh: src/cpu/o3/sat_counter.hh: src/cpu/op_class.hh: src/cpu/ozone/cpu.hh: src/cpu/checker/cpu.cc: src/cpu/checker/cpu.hh: src/cpu/checker/exec_context.hh: src/cpu/checker/o3_cpu_builder.cc: src/cpu/ozone/cpu_impl.hh: src/mem/request.hh: src/cpu/o3/fu_pool.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_unit.hh: src/cpu/o3/lsq_unit_impl.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/back_end.hh: src/cpu/ozone/dyn_inst.cc: src/cpu/ozone/dyn_inst.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/inorder_back_end.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/ozone_impl.hh: src/cpu/ozone/thread_state.hh: Fixes to get compiling to work. src/cpu/o3/alpha_cpu.hh: Fixes to get compiling to work. Float reg accessors have changed, as well as MemReqPtrs to RequestPtrs. src/cpu/o3/alpha_dyn_inst_impl.hh: Fixes to get compiling to work. Pass in the packet to the completeAcc function. Fix up syscall function. --HG-- rename : cpu/activity.cc => src/cpu/activity.cc rename : cpu/activity.hh => src/cpu/activity.hh rename : cpu/checker/cpu.cc => src/cpu/checker/cpu.cc rename : cpu/checker/cpu.hh => src/cpu/checker/cpu.hh rename : cpu/checker/cpu_builder.cc => src/cpu/checker/cpu_builder.cc rename : cpu/checker/exec_context.hh => src/cpu/checker/exec_context.hh rename : cpu/checker/o3_cpu_builder.cc => src/cpu/checker/o3_cpu_builder.cc rename : cpu/o3/dep_graph.hh => src/cpu/o3/dep_graph.hh rename : cpu/o3/fu_pool.cc => src/cpu/o3/fu_pool.cc rename : cpu/o3/fu_pool.hh => src/cpu/o3/fu_pool.hh rename : cpu/o3/lsq.cc => src/cpu/o3/lsq.cc rename : cpu/o3/lsq.hh => src/cpu/o3/lsq.hh rename : cpu/o3/lsq_impl.hh => src/cpu/o3/lsq_impl.hh rename : cpu/o3/lsq_unit.cc => src/cpu/o3/lsq_unit.cc rename : cpu/o3/lsq_unit.hh => src/cpu/o3/lsq_unit.hh rename : cpu/o3/lsq_unit_impl.hh => src/cpu/o3/lsq_unit_impl.hh rename : cpu/o3/scoreboard.cc => src/cpu/o3/scoreboard.cc rename : cpu/o3/scoreboard.hh => src/cpu/o3/scoreboard.hh rename : cpu/o3/thread_state.hh => src/cpu/o3/thread_state.hh rename : cpu/ozone/back_end.cc => src/cpu/ozone/back_end.cc rename : cpu/ozone/back_end.hh => src/cpu/ozone/back_end.hh rename : cpu/ozone/back_end_impl.hh => src/cpu/ozone/back_end_impl.hh rename : cpu/ozone/cpu_builder.cc => src/cpu/ozone/cpu_builder.cc rename : cpu/ozone/dyn_inst.cc => src/cpu/ozone/dyn_inst.cc rename : cpu/ozone/dyn_inst.hh => src/cpu/ozone/dyn_inst.hh rename : cpu/ozone/dyn_inst_impl.hh => src/cpu/ozone/dyn_inst_impl.hh rename : cpu/ozone/front_end.cc => src/cpu/ozone/front_end.cc rename : cpu/ozone/front_end.hh => src/cpu/ozone/front_end.hh rename : cpu/ozone/front_end_impl.hh => src/cpu/ozone/front_end_impl.hh rename : cpu/ozone/inorder_back_end.cc => src/cpu/ozone/inorder_back_end.cc rename : cpu/ozone/inorder_back_end.hh => src/cpu/ozone/inorder_back_end.hh rename : cpu/ozone/inorder_back_end_impl.hh => src/cpu/ozone/inorder_back_end_impl.hh rename : cpu/ozone/inst_queue.cc => src/cpu/ozone/inst_queue.cc rename : cpu/ozone/inst_queue.hh => src/cpu/ozone/inst_queue.hh rename : cpu/ozone/inst_queue_impl.hh => src/cpu/ozone/inst_queue_impl.hh rename : cpu/ozone/lsq_unit.cc => src/cpu/ozone/lsq_unit.cc rename : cpu/ozone/lsq_unit.hh => src/cpu/ozone/lsq_unit.hh rename : cpu/ozone/lsq_unit_impl.hh => src/cpu/ozone/lsq_unit_impl.hh rename : cpu/ozone/lw_back_end.cc => src/cpu/ozone/lw_back_end.cc rename : cpu/ozone/lw_back_end.hh => src/cpu/ozone/lw_back_end.hh rename : cpu/ozone/lw_back_end_impl.hh => src/cpu/ozone/lw_back_end_impl.hh rename : cpu/ozone/lw_lsq.cc => src/cpu/ozone/lw_lsq.cc rename : cpu/ozone/lw_lsq.hh => src/cpu/ozone/lw_lsq.hh rename : cpu/ozone/lw_lsq_impl.hh => src/cpu/ozone/lw_lsq_impl.hh rename : cpu/ozone/null_predictor.hh => src/cpu/ozone/null_predictor.hh rename : cpu/ozone/ozone_impl.hh => src/cpu/ozone/ozone_impl.hh rename : cpu/ozone/rename_table.cc => src/cpu/ozone/rename_table.cc rename : cpu/ozone/rename_table.hh => src/cpu/ozone/rename_table.hh rename : cpu/ozone/rename_table_impl.hh => src/cpu/ozone/rename_table_impl.hh rename : cpu/ozone/simple_impl.hh => src/cpu/ozone/simple_impl.hh rename : cpu/ozone/simple_params.hh => src/cpu/ozone/simple_params.hh rename : cpu/ozone/thread_state.hh => src/cpu/ozone/thread_state.hh rename : cpu/quiesce_event.cc => src/cpu/quiesce_event.cc rename : cpu/quiesce_event.hh => src/cpu/quiesce_event.hh rename : cpu/thread_state.hh => src/cpu/thread_state.hh rename : python/m5/objects/FUPool.py => src/python/m5/objects/FUPool.py rename : python/m5/objects/OzoneCPU.py => src/python/m5/objects/OzoneCPU.py rename : python/m5/objects/SimpleOzoneCPU.py => src/python/m5/objects/SimpleOzoneCPU.py extra : convert_revision : ca7f0fbf65ee1a70d482fb4eda9a1840c7f9b8f8
2006-06-03 00:15:20 +02:00
add a bridge object, modify bus object to be able to connect to other buses or bridges without panicing SConscript: add new cc files to scons mem/bus.cc: mem/bus.hh: implement addressRanges() on the bus. propigate address ranges to anyone who is interested stripping out ranges of who your propigating to (to avoid livelock) mem/packet.hh: add intersect function that returns true if two packets touch at least one byte of the same data (for functional access) add fixPacket() that will eventually take the correct action giving a timing and functional packet, right now it panics mem/physical.cc: Don't panic if the physical memory recieves a status change, just ignore. --HG-- extra : convert_revision : d470d51f2fb1db2700ad271e09792315ef33ba01
2006-04-28 21:37:48 +02:00
mem/bridge.cc
mem/bus.cc
Replace Memory with MemObject; no need for two different levels of hierarchy there. Get rid of addPort(). Change getPort() behavior on PhysicalMemory. SConscript: cpu/simple/cpu.hh: sim/system.cc: sim/system.hh: Replace Memory with MemObject. cpu/base.hh: No need to declare Port here anymore. cpu/cpu_exec_context.hh: Need PageTable definition. cpu/simple/cpu.cc: mem/physical.cc: mem/physical.hh: Replace Memory with MemObject. Get rid of addPort(); allow getting anonymous ports with getPort(). mem/translating_port.hh: Remove unneeded header. sim/process.cc: Replace Memory with MemObject. Change how initialization port gets set up to deal with change in addPort()/getPort(). Current solution is not ideal but it works. sim/process.hh: Remove unneeded headers and declarations. Make LiveProcess::getDesc() abstract instead of panicing if called. sim/syscall_emul.hh: Fix includes. --HG-- extra : convert_revision : 11d4ffb54230038afcf7219cc46e51f809329a2f
2006-03-12 23:21:59 +01:00
mem/mem_object.cc
add a bridge object, modify bus object to be able to connect to other buses or bridges without panicing SConscript: add new cc files to scons mem/bus.cc: mem/bus.hh: implement addressRanges() on the bus. propigate address ranges to anyone who is interested stripping out ranges of who your propigating to (to avoid livelock) mem/packet.hh: add intersect function that returns true if two packets touch at least one byte of the same data (for functional access) add fixPacket() that will eventually take the correct action giving a timing and functional packet, right now it panics mem/physical.cc: Don't panic if the physical memory recieves a status change, just ignore. --HG-- extra : convert_revision : d470d51f2fb1db2700ad271e09792315ef33ba01
2006-04-28 21:37:48 +02:00
mem/packet.cc
Changes to start making the tree use the new memory system. Trying to compile decoder.cc but fails still. SConscript: Place the memory objects back in the right place arch/alpha/isa_desc: Fix includes to point to the new memory requests cpu/exec_context.hh: Exec context now points to memory object, fix the include paths. Convert to prot_read/prot_write functions instead of read and write. Convert to new CpuRequestPtr instead of MemReqPtr. mem/request.hh: Add back in support for Request Flags (needed by decoder to tag request) Removed the flags that were associated with packets/coherence. sim/process.hh: Converted to point to new memory objects --HG-- extra : convert_revision : a0b95380915d63b53194e2a26336d6adb1a0086b
2006-02-15 20:53:02 +01:00
mem/physical.cc
Move read/writeBlob functions to Port class; clean up implementation a little. SConscript: Add mem/port.cc cpu/simple/cpu.cc: cpu/simple/cpu.hh: Move read/writeBlob functions to base Port class. mem/port.hh: Implement read/writeBlob functions. No need for them to be virtual since the proxy object (now called TranslatingPort) is not a subclass of Port. mem/port.cc: Implement read/writeBlob functions. --HG-- extra : convert_revision : a3660eaa43a7c286aca962f17fa32fbd42bf1fa6
2006-02-21 17:27:53 +01:00
mem/port.cc
Move PioPort timing code into Simple Timing Port object Make PioPort use it Make Physical memory use it as well src/SConscript: Add timing port to sconscript src/dev/io_device.cc: src/dev/io_device.hh: Move simple timing pio port stuff into a simple timing port class so it can be used by the physical memory src/mem/physical.cc: src/mem/physical.hh: use a simple timing port stuff instead of rolling our own here --HG-- extra : convert_revision : e5befbd295a572568cfdca533efb5ed1984c59d1
2006-07-21 01:03:47 +02:00
mem/tport.cc
Changes to start making the tree use the new memory system. Trying to compile decoder.cc but fails still. SConscript: Place the memory objects back in the right place arch/alpha/isa_desc: Fix includes to point to the new memory requests cpu/exec_context.hh: Exec context now points to memory object, fix the include paths. Convert to prot_read/prot_write functions instead of read and write. Convert to new CpuRequestPtr instead of MemReqPtr. mem/request.hh: Add back in support for Request Flags (needed by decoder to tag request) Removed the flags that were associated with packets/coherence. sim/process.hh: Converted to point to new memory objects --HG-- extra : convert_revision : a0b95380915d63b53194e2a26336d6adb1a0086b
2006-02-15 20:53:02 +01:00
Backing in more changsets, getting closer to compile base_cache.cc compiles, continuing on src/SConscript: Add in compilation flags for cache files src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: Back in more fixes, now base_cache compiles src/mem/cache/cache.hh: src/mem/cache/cache_blk.hh: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/coherence_protocol.cc: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/blocking_buffer.hh: src/mem/cache/miss/miss_queue.cc: src/mem/cache/miss/miss_queue.hh: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr.hh: src/mem/cache/miss/mshr_queue.cc: src/mem/cache/miss/mshr_queue.hh: src/mem/cache/prefetch/base_prefetcher.cc: src/mem/cache/tags/fa_lru.cc: src/mem/cache/tags/iic.cc: src/mem/cache/tags/lru.cc: src/mem/cache/tags/split_lifo.cc: src/mem/cache/tags/split_lru.cc: src/mem/packet.cc: src/mem/packet.hh: src/mem/request.hh: Backing in more changsets, getting closer to compile --HG-- extra : convert_revision : ac2dcda39f8d27baffc4db1df17b9a1fcce5b6ed
2006-06-28 20:35:00 +02:00
mem/cache/base_cache.cc
mem/cache/cache.cc
mem/cache/coherence/coherence_protocol.cc
mem/cache/coherence/uni_coherence.cc
mem/cache/miss/blocking_buffer.cc
mem/cache/miss/miss_queue.cc
mem/cache/miss/mshr.cc
mem/cache/miss/mshr_queue.cc
mem/cache/prefetch/base_prefetcher.cc
mem/cache/prefetch/ghb_prefetcher.cc
mem/cache/prefetch/prefetcher.cc
mem/cache/prefetch/stride_prefetcher.cc
mem/cache/prefetch/tagged_prefetcher.cc
mem/cache/tags/base_tags.cc
mem/cache/tags/cache_tags.cc
mem/cache/tags/fa_lru.cc
All files compile in the mem directory except cache_builder Missing some functionality (like split caches and copy support) src/SConscript: Typo src/mem/cache/prefetch/base_prefetcher.cc: src/mem/cache/prefetch/ghb_prefetcher.hh: src/mem/cache/prefetch/stride_prefetcher.hh: src/mem/cache/prefetch/tagged_prefetcher_impl.hh: src/mem/cache/tags/fa_lru.cc: src/mem/cache/tags/fa_lru.hh: src/mem/cache/tags/iic.cc: src/mem/cache/tags/iic.hh: src/mem/cache/tags/lru.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.cc: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.cc: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.cc: src/mem/cache/tags/split_lru.hh: src/mem/packet.hh: src/mem/request.hh: Fix so it compiles --HG-- extra : convert_revision : 0d87d84f6e9445bab655c0cb0f8541bbf6eab904
2006-06-30 16:25:25 +02:00
mem/cache/tags/iic.cc
Backing in more changsets, getting closer to compile base_cache.cc compiles, continuing on src/SConscript: Add in compilation flags for cache files src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: Back in more fixes, now base_cache compiles src/mem/cache/cache.hh: src/mem/cache/cache_blk.hh: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/coherence_protocol.cc: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/blocking_buffer.hh: src/mem/cache/miss/miss_queue.cc: src/mem/cache/miss/miss_queue.hh: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr.hh: src/mem/cache/miss/mshr_queue.cc: src/mem/cache/miss/mshr_queue.hh: src/mem/cache/prefetch/base_prefetcher.cc: src/mem/cache/tags/fa_lru.cc: src/mem/cache/tags/iic.cc: src/mem/cache/tags/lru.cc: src/mem/cache/tags/split_lifo.cc: src/mem/cache/tags/split_lru.cc: src/mem/packet.cc: src/mem/packet.hh: src/mem/request.hh: Backing in more changsets, getting closer to compile --HG-- extra : convert_revision : ac2dcda39f8d27baffc4db1df17b9a1fcce5b6ed
2006-06-28 20:35:00 +02:00
mem/cache/tags/lru.cc
mem/cache/tags/repl/gen.cc
mem/cache/tags/repl/repl.cc
mem/cache/tags/split.cc
mem/cache/tags/split_lifo.cc
mem/cache/tags/split_lru.cc
Still missing prefetch and tags directories as well as cache builder. Some implementation details were left blank still, need to fill them in. src/SConscript: Reorder build to compile all files first src/mem/cache/cache.hh: src/mem/cache/cache_builder.cc: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/coherence_protocol.cc: src/mem/cache/coherence/uni_coherence.cc: src/mem/cache/coherence/uni_coherence.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/miss_queue.cc: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr.hh: src/mem/cache/miss/mshr_queue.cc: More changesets pulled, now compiles everything in /miss directory and in the root directory src/mem/packet.hh: Add some more support, need to clean some of it out once everything is working --HG-- extra : convert_revision : ba73676165810edf2c2effaf5fbad8397d6bd800
2006-06-29 22:07:19 +02:00
mem/cache/cache_builder.cc
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
sim/builder.cc
sim/debug.cc
sim/eventq.cc
Changed the fault enum into a class, and fixed everything up to work with it. Next, the faults need to be pulled out of all the other code so that they are only used to communicate between the CPU and the ISA. SConscript: The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away. arch/alpha/alpha_memory.cc: Changed Fault to Fault * and took the underscores out of fault names. arch/alpha/alpha_memory.hh: Changed Fault to Fault *. Also, added an include for the alpha faults. arch/alpha/ev5.cc: Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names. arch/alpha/isa/decoder.isa: Changed Fault to Fault * and took the underscores out fault names. arch/alpha/isa/fp.isa: Changed Fault to Fault *, and took the underscores out of fault names. arch/alpha/isa/main.isa: Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files. arch/alpha/isa/mem.isa: Changed Fault to Fault * and removed underscores from fault names. arch/alpha/isa/unimp.isa: arch/alpha/isa/unknown.isa: cpu/exec_context.hh: cpu/ozone/cpu.hh: cpu/simple/cpu.cc: dev/alpha_console.cc: dev/ide_ctrl.cc: dev/isa_fake.cc: dev/pciconfigall.cc: dev/pcidev.cc: dev/pcidev.hh: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: Changed Fault to Fault *, and removed underscores from fault names. arch/alpha/isa_traits.hh: Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed. cpu/base_dyn_inst.cc: Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault. cpu/base_dyn_inst.hh: Changed Fault to Fault * and took the underscores out of the fault names. cpu/exec_context.cc: cpu/o3/alpha_dyn_inst.hh: cpu/o3/alpha_dyn_inst_impl.hh: cpu/o3/fetch.hh: dev/alpha_console.hh: dev/baddev.hh: dev/ide_ctrl.hh: dev/isa_fake.hh: dev/ns_gige.hh: dev/pciconfigall.hh: dev/sinic.hh: dev/tsunami_cchip.hh: dev/tsunami_io.hh: dev/tsunami_pchip.hh: dev/uart.hh: dev/uart8250.hh: Changed Fault to Fault *. cpu/o3/alpha_cpu.hh: Changed Fault to Fault *, removed underscores from fault names. cpu/o3/alpha_cpu_impl.hh: Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away. cpu/o3/commit_impl.hh: cpu/o3/fetch_impl.hh: dev/baddev.cc: Changed Fault to Fault *, and removed underscores from the fault names. cpu/o3/regfile.hh: Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names. cpu/simple/cpu.hh: Changed Fault to Fault * dev/ns_gige.cc: Changed Fault to Fault *, and removdd underscores from fault names. dev/sinic.cc: Changed Fault to Fault *, and removed the underscores from fault names. dev/uart8250.cc: Chanted Fault to Fault *, and removed underscores from fault names. kern/kernel_stats.cc: Removed underscores from fault names, and from NumFaults. kern/kernel_stats.hh: Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally. sim/faults.cc: This allocates the system wide faults. sim/faults.hh: This declares the system wide faults. sim/syscall_emul.cc: sim/syscall_emul.hh: Removed the underscores from fault names. --HG-- rename : arch/alpha/faults.cc => sim/faults.cc rename : arch/alpha/faults.hh => sim/faults.hh extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d
2006-02-16 07:22:51 +01:00
sim/faults.cc
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
sim/main.cc
Rename SWIG "main" module to "cc_main" so it's clear from the Python side that this is the interface to C++. src/SConscript: main_wrap.cc -> cc_main_wrap.cc src/python/SConscript: src/python/m5/__init__.py: src/sim/main.cc: s/main/cc_main/ src/python/m5/config.py: s/main/cc_main/ Also directly import cc_main so we don't need to put the "m5." in front all the time. --HG-- extra : convert_revision : 755552f70cf671881ff31e476c677b95ef12950d
2006-06-17 18:08:19 +02:00
python/swig/cc_main_wrap.cc
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
sim/param.cc
Rename sim/universe.{cc,hh} to root.{cc,hh} (since the object defined there was renamed Root long ago). SConscript: arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_tru64_process.cc: base/misc.cc: base/pollevent.cc: base/pollevent.hh: base/stats/events.cc: base/trace.hh: cpu/beta_cpu/fetch_impl.hh: cpu/beta_cpu/full_cpu.cc: cpu/beta_cpu/inst_queue_impl.hh: cpu/pc_event.cc: cpu/static_inst.cc: dev/etherbus.cc: dev/etherdump.cc: dev/etherlink.cc: dev/ide_disk.cc: dev/pcidev.cc: sim/builder.cc: sim/eventq.cc: sim/main.cc: sim/root.cc: sim/stat_control.cc: Rename sim/universe.{cc,hh} to root.{cc,hh}. --HG-- rename : sim/universe.cc => sim/root.cc extra : convert_revision : b8699e81e285253d66da75412e7bb2c251c0389a
2005-06-02 03:59:27 +02:00
sim/root.cc
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
sim/serialize.cc
sim/sim_events.cc
sim/sim_object.cc
add a new phase to the simulator. Basically the simulator now goes through the following phases. 1) Construct all param contexts 2) Call the checkParams() on each context 3) Build the configuration hierarchy 4) Construct all SimObjects 5) Initialize all SimObjects by calling init() on each one 6) Unserialize the checkpoint 7) Register all statisitcs 8) Check validity of all statistics (after that, no new stats) 9) Reset all stats. 10) Call SimStartup() which calls startup() on all SimObjects, ParamContexts, and any other object deriving from StartupCallback SConscript: no more SimInit() we have SimStartup() now sim/param.hh: Make all params have a startup callback. sim/sim_events.cc: the init callbacks no longer exist. We can simplify code by using startup(). sim/sim_object.hh: Make all SimObjects derive from StartupCallback --HG-- extra : convert_revision : ab81e259eb5510cc597f7bacb2bfb619fb4cc15f
2004-11-03 17:47:55 +01:00
sim/startup.cc
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
sim/stat_context.cc
sim/stat_control.cc
Add PageTable code and SConscript fixes for new syscall emulation memory model. These changes really should have been part of the previous changeset. SConscript: Move System and PhysicalMemory sources from being full_system_sources to base_sources, since they are now used in syscall emulation also. Also add source files for PageTable and ProxyMemory objects. Actual source files for PhysicalMemory and ProxyMemory are not committed yet since they still need to be ported from old interface. --HG-- extra : convert_revision : cb39e3b13d71429b7ee6082794dc09428cde989f
2006-01-29 23:28:04 +01:00
sim/system.cc
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
sim/trace_context.cc
''')
Enable building only selected CPU models via new scons CPU_MODELS parameter. For example: scons CPU_MODELS="SimpleCPU,FullCPU" ALPHA_SE/m5.debug Unfortunately the option is not sticky due to a scons bug with saving & restoring ListOption parameters. SConscript: Separate out cpu-model-specific files so they can be conditionally included based on value of new CPU_MODELS parameter. Most of these are now handled in cpu/SConscript, except for FullCPU which is still in this file. arch/SConscript: The set of CPU-model-specific execute files must now be determined from the CPU_MODELS parameter, via the new cpu_models.py file. Also pass the list of configured CPU models to isa_parser.py. arch/isa_parser.py: Move CpuModel definition and objects out to a separate file so they can be shared with scons. Global list of CPU models to generate code for is now controlled by command-line parameters (so we can do only a subset of the available ones). build/SConstruct: Define new CPU_MODELS ListOption. cpu/static_inst.hh: Rename static_inst_impl.hh to static_inst_exec_sigs.hh. --HG-- extra : convert_revision : 163df32a76d4c05900490b2bce4c7962a5e3f614
2006-02-23 23:00:29 +01:00
# Old FullCPU sources
Hacks to avoid compiling in old FullCPU model. Needed in the interim until we port the old model over to the new interface. Long term we should have a cleaner solution for controlling which models get compiled in. SConscript: Move old FullCPU source file list to separate full_cpu_sources list so we can choose to not include it in compile. arch/isa_parser.py: Hack to avoid generating FullCPU execute files. Need a better way to control this. cpu/exetrace.cc: Don't include old FullCPU-specific headers (apparently unnecessary anyway--or if not they should be). --HG-- extra : convert_revision : 00d5a91a9e4d71507404b8c7f4c6e7c7b7ba3853
2006-01-29 23:35:53 +01:00
full_cpu_sources = Split('''
encumbered/cpu/full/bpred.cc
encumbered/cpu/full/commit.cc
encumbered/cpu/full/cpu.cc
encumbered/cpu/full/create_vector.cc
encumbered/cpu/full/cv_spec_state.cc
encumbered/cpu/full/dd_queue.cc
encumbered/cpu/full/dep_link.cc
encumbered/cpu/full/dispatch.cc
encumbered/cpu/full/dyn_inst.cc
encumbered/cpu/full/execute.cc
encumbered/cpu/full/fetch.cc
encumbered/cpu/full/floss_reasons.cc
Enable building only selected CPU models via new scons CPU_MODELS parameter. For example: scons CPU_MODELS="SimpleCPU,FullCPU" ALPHA_SE/m5.debug Unfortunately the option is not sticky due to a scons bug with saving & restoring ListOption parameters. SConscript: Separate out cpu-model-specific files so they can be conditionally included based on value of new CPU_MODELS parameter. Most of these are now handled in cpu/SConscript, except for FullCPU which is still in this file. arch/SConscript: The set of CPU-model-specific execute files must now be determined from the CPU_MODELS parameter, via the new cpu_models.py file. Also pass the list of configured CPU models to isa_parser.py. arch/isa_parser.py: Move CpuModel definition and objects out to a separate file so they can be shared with scons. Global list of CPU models to generate code for is now controlled by command-line parameters (so we can do only a subset of the available ones). build/SConstruct: Define new CPU_MODELS ListOption. cpu/static_inst.hh: Rename static_inst_impl.hh to static_inst_exec_sigs.hh. --HG-- extra : convert_revision : 163df32a76d4c05900490b2bce4c7962a5e3f614
2006-02-23 23:00:29 +01:00
encumbered/cpu/full/fu_pool.cc
Hacks to avoid compiling in old FullCPU model. Needed in the interim until we port the old model over to the new interface. Long term we should have a cleaner solution for controlling which models get compiled in. SConscript: Move old FullCPU source file list to separate full_cpu_sources list so we can choose to not include it in compile. arch/isa_parser.py: Hack to avoid generating FullCPU execute files. Need a better way to control this. cpu/exetrace.cc: Don't include old FullCPU-specific headers (apparently unnecessary anyway--or if not they should be). --HG-- extra : convert_revision : 00d5a91a9e4d71507404b8c7f4c6e7c7b7ba3853
2006-01-29 23:35:53 +01:00
encumbered/cpu/full/inst_fifo.cc
encumbered/cpu/full/instpipe.cc
encumbered/cpu/full/issue.cc
encumbered/cpu/full/ls_queue.cc
encumbered/cpu/full/machine_queue.cc
encumbered/cpu/full/pipetrace.cc
encumbered/cpu/full/readyq.cc
encumbered/cpu/full/reg_info.cc
encumbered/cpu/full/rob_station.cc
encumbered/cpu/full/spec_memory.cc
encumbered/cpu/full/spec_state.cc
encumbered/cpu/full/storebuffer.cc
encumbered/cpu/full/writeback.cc
encumbered/cpu/full/iq/iq_station.cc
encumbered/cpu/full/iq/iqueue.cc
encumbered/cpu/full/iq/segmented/chain_info.cc
encumbered/cpu/full/iq/segmented/chain_wire.cc
encumbered/cpu/full/iq/segmented/iq_seg.cc
encumbered/cpu/full/iq/segmented/iq_segmented.cc
encumbered/cpu/full/iq/segmented/seg_chain.cc
encumbered/cpu/full/iq/seznec/iq_seznec.cc
encumbered/cpu/full/iq/standard/iq_standard.cc
''')
Hand merge. Stuff probably doesn't compile. --HG-- rename : arch/alpha/isa_desc => arch/alpha/isa/main.isa rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux/process.cc rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux/process.hh rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64/process.cc rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64/process.hh rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh extra : convert_revision : 7d1efcedd708815d985a951f6f010fbd83dc27e8
2006-03-10 00:35:28 +01:00
trace_reader_sources = Split('''
cpu/trace/reader/mem_trace_reader.cc
cpu/trace/reader/ibm_reader.cc
cpu/trace/reader/itx_reader.cc
cpu/trace/reader/m5_reader.cc
cpu/trace/opt_cpu.cc
cpu/trace/trace_cpu.cc
More progress toward compiling... partly by fixing things, partly by ignoring CPU models that don't currently compile. SConscript: Split sources for fast, simple, and o3 CPU models into separate source lists. For now none of these are included in the base source list, so you won't get any CPU models at all... but we still can't compile the other stuff so it's not an issue. Also get rid of obsolete encumbered/mem file. base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/object_file.hh: cpu/exec_context.cc: sim/process.cc: sim/system.cc: sim/system.hh: FunctionalMemory -> Memory cpu/pc_event.hh: Get rid of unused badpc. cpu/simple/cpu.cc: cpu/simple/cpu.hh: Move Port functions into .cc file. mem/port.hh: Make recvAddressRangesQuery panic by default instead of being abstract... do CPUs need to implement this? mem/request.hh: Add prefetch flags. sim/syscall_emul.hh: Start to fix... --HG-- extra : convert_revision : ece53b3855f20916caaa381598ac37e8c7adfba7
2006-02-15 23:52:49 +01:00
''')
Hand merge. Stuff probably doesn't compile. --HG-- rename : arch/alpha/isa_desc => arch/alpha/isa/main.isa rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux/process.cc rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux/process.hh rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64/process.cc rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64/process.hh rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh extra : convert_revision : 7d1efcedd708815d985a951f6f010fbd83dc27e8
2006-03-10 00:35:28 +01:00
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
# MySql sources
mysql_sources = Split('''
base/mysql.cc
base/stats/mysql.cc
''')
# Full-system sources
full_system_sources = Split('''
Clean up network header stuff and make it more generic. Use libdnet when we can instead of our own home grown stuff. SConscript: separate the crc code into its own file base/inet.cc: move the crc stuff to crc.cc add generic code for calculating ip/tcp/udp checksums base/inet.hh: - move crc stuff to crc.hh - #include all of the libdnet stuff. (this makes base/inet.hh the only file you need to include if you want to use this kind of stuff.) - Wrap some of the libdnet structs to get easier access to structure members. These wrappers will automatically deal with masking/shifting/ byte-swapping. base/refcnt.hh: If one derives from RefCountingPtr, they should have access to the internal data pointer. build/SConstruct: make #include of dnet stuff work dev/etherlink.cc: dev/ethertap.cc: dev/ethertap.hh: EtherPacket -> PacketData dev/etherpkt.cc: EtherPacket -> PacketData add a function for populating extra info about a packet. Basically just gives pointers to ethernet/ip/tcp/udp headers if they exist. dev/etherpkt.hh: EtherPacket -> PacketData remove most of the packet header stuff from teh PacketData class and just add a few generic functions for grabbing various headers that may exist in the packet. The old functionality is contained in the headers. dev/ns_gige.cc: - IP -> Ip, UDP -> Udp, TCP ->Tcp when used in variable names - get rid of our own byte swapping functions. - whack checksum code and use libdnet version. - Get pointers to the various packet headers and grab info from those headers. (The byte swapping in the headers now.) - Add stats for Udp Checksums dev/ns_gige.hh: use libdnet for checksum code. IP -> Ip, TCP -> Tcp in variable names add stats for UDP checksums --HG-- extra : convert_revision : 96c4160e1967b7c0090acd456df4a76e1f3aab53
2004-09-20 16:43:53 +02:00
base/crc.cc
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
base/inet.cc
base/remote_gdb.cc
cpu/intr_control.cc
Add new function profiling stuff, wrap the pc_sample stuff into it. SConscript: Get rid of the pc_sample stuff and move to the new profiling stuff base/traceflags.py: DPRINTF Stack stuff cpu/base.cc: cpu/base.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/simple/cpu.cc: Add profiling stuff kern/kernel_stats.hh: Use a smart pointer sim/system.cc: sim/system.hh: Create a new symbol table that has all of the symbols for a particular system util/stats/categories.py: change around the categories, add categories for function profiling stuff util/stats/profile.py: No profile parsing and display code to deal with function profiling stuff, graph, dot, and text outputs. --HG-- extra : convert_revision : b3de0cdc8bd468e42647966e2640ae009bda9eb8
2005-10-19 01:07:42 +02:00
cpu/profile.cc
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
dev/alpha_console.cc
updates for newmem SConscript: compile some more devices --HG-- extra : convert_revision : 82a8164ab38814a56a0c143658bc06338cf6b8f5
2006-04-10 20:14:06 +02:00
dev/baddev.cc
fixes for newmem ALPHA_FS finally compiles again SConscript: Use a couple more FS sources, still don't compile that much arch/alpha/faults.hh: the unimp fault should probably exist in nonfs too. dev/alpha_console.cc: dev/alpha_console.hh: dev/simconsole.cc: dev/simple_disk.cc: dev/simple_disk.hh: dev/uart.cc: dev/uart.hh: dev/uart8250.cc: dev/uart8250.hh: sim/process.cc: sim/system.cc: fixes for newmem dev/io_device.hh: a system pointer is probably useful for every device to have mem/bus.hh: mem/physical.cc: new address ranges function python/m5/objects/SimpleDisk.py: simple disk now has a system pointer rather than physmem directly --HG-- extra : convert_revision : d8c0a5c6510a6210aec5e8adfb0a4a06ec0dcebf
2006-04-06 20:57:51 +02:00
dev/disk_image.cc
Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working after merge from head. Checkpointing may need some work now. Endian-happiness still not complete. SConscript: add all devices back into make file base/inet.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/pktfifo.cc: dev/pktfifo.hh: rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system configs/test/fs.py: add nics to fs.py cpu/cpu_exec_context.cc: remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the static virtual ports in the exec context cpu/simple/cpu.cc: cpu/simple/cpu.hh: dev/alpha_console.cc: dev/ide_ctrl.cc: use new methods for accessing packet data dev/ide_disk.cc: add some more dprintfs dev/io_device.cc: delete packets when we are done with them. Update for new packet methods to access data dev/isa_fake.cc: dev/pciconfigall.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: dev/uart8250.hh: mem/physical.cc: mem/port.cc: dUpdate for new packet methods to access data dev/ns_gige.cc: Update for new memory system dev/ns_gige.hh: python/m5/objects/Ethernet.py: update for new memory system dev/sinic.cc: dev/sinic.hh: Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions mem/packet.hh: Add methods to access data instead of accessing it directly. --HG-- extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e
2006-04-25 01:31:50 +02:00
dev/etherbus.cc
dev/etherdump.cc
dev/etherint.cc
dev/etherlink.cc
dev/etherpkt.cc
dev/ethertap.cc
dev/ide_ctrl.cc
make ide disk work for newmem SConscript: compile ide devices base/chunk_generator.hh: add another parameter to the chuck generator called complete() which returns the number of bytes transfered so far. Very useful for adding to a pointer. configs/test/fs.py: Add ide disk to fs test configuration dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: update for new memory system mem/bus.cc: support devices that return multiple ranges remove old ranges before using new info mem/packet.hh: make senderstate void* per steve's request that we use every construct possible in C++ mem/physical.cc: have memory stamp the packet with the time. mem/physical.hh: actually set the memory latency variable python/m5/objects/Device.py: Add DmaDevice python/m5/objects/Ide.py: Ide disk no longer has a physmem pointer python/m5/objects/Pci.py: update pci device for newmem python/m5/objects/PhysicalMemory.py: add latency parameter for physical memory sim/byteswap.hh: use fast architecture dependent byteswap calls if they exist --HG-- extra : convert_revision : e3cf2e8f61064ad302d94bc22010a00c59f3f793
2006-04-20 23:14:30 +02:00
dev/ide_disk.cc
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
dev/io_device.cc
updates for newmem SConscript: compile some more devices --HG-- extra : convert_revision : 82a8164ab38814a56a0c143658bc06338cf6b8f5
2006-04-10 20:14:06 +02:00
dev/isa_fake.cc
Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working after merge from head. Checkpointing may need some work now. Endian-happiness still not complete. SConscript: add all devices back into make file base/inet.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/pktfifo.cc: dev/pktfifo.hh: rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system configs/test/fs.py: add nics to fs.py cpu/cpu_exec_context.cc: remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the static virtual ports in the exec context cpu/simple/cpu.cc: cpu/simple/cpu.hh: dev/alpha_console.cc: dev/ide_ctrl.cc: use new methods for accessing packet data dev/ide_disk.cc: add some more dprintfs dev/io_device.cc: delete packets when we are done with them. Update for new packet methods to access data dev/isa_fake.cc: dev/pciconfigall.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: dev/uart8250.hh: mem/physical.cc: mem/port.cc: dUpdate for new packet methods to access data dev/ns_gige.cc: Update for new memory system dev/ns_gige.hh: python/m5/objects/Ethernet.py: update for new memory system dev/sinic.cc: dev/sinic.hh: Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions mem/packet.hh: Add methods to access data instead of accessing it directly. --HG-- extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e
2006-04-25 01:31:50 +02:00
dev/ns_gige.cc
fullsys now builds and runs for about one cycle SConscript: easier to fix than temporarily remove cpu/simple/cpu.cc: cpu/simple/cpu.hh: mem needed for both fullsys and syscall dev/baddev.cc: fix for new mem system dev/io_device.cc: fix typo dev/io_device.hh: PioDevice needs to be a memobject dev/isa_fake.cc: dev/pciconfigall.cc: dev/pciconfigall.hh: fix for new mem systems dev/platform.cc: dev/platform.hh: dev/tsunami.cc: dev/tsunami.hh: rather than the platform have a pointer to pciconfig, go the other way so all devices are the same and can have a platform pointer dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/uart8250.cc: python/m5/objects/AlphaConsole.py: python/m5/objects/BadDevice.py: python/m5/objects/BaseCPU.py: python/m5/objects/Device.py: python/m5/objects/Pci.py: python/m5/objects/PhysicalMemory.py: python/m5/objects/System.py: python/m5/objects/Tsunami.py: python/m5/objects/Uart.py: fixes for newmem --HG-- extra : convert_revision : b7b67e19095cca64889f6307725aa2f3d84c7105
2006-04-11 19:42:47 +02:00
dev/pciconfigall.cc
make ide disk work for newmem SConscript: compile ide devices base/chunk_generator.hh: add another parameter to the chuck generator called complete() which returns the number of bytes transfered so far. Very useful for adding to a pointer. configs/test/fs.py: Add ide disk to fs test configuration dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: update for new memory system mem/bus.cc: support devices that return multiple ranges remove old ranges before using new info mem/packet.hh: make senderstate void* per steve's request that we use every construct possible in C++ mem/physical.cc: have memory stamp the packet with the time. mem/physical.hh: actually set the memory latency variable python/m5/objects/Device.py: Add DmaDevice python/m5/objects/Ide.py: Ide disk no longer has a physmem pointer python/m5/objects/Pci.py: update pci device for newmem python/m5/objects/PhysicalMemory.py: add latency parameter for physical memory sim/byteswap.hh: use fast architecture dependent byteswap calls if they exist --HG-- extra : convert_revision : e3cf2e8f61064ad302d94bc22010a00c59f3f793
2006-04-20 23:14:30 +02:00
dev/pcidev.cc
Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working after merge from head. Checkpointing may need some work now. Endian-happiness still not complete. SConscript: add all devices back into make file base/inet.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/pktfifo.cc: dev/pktfifo.hh: rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system configs/test/fs.py: add nics to fs.py cpu/cpu_exec_context.cc: remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the static virtual ports in the exec context cpu/simple/cpu.cc: cpu/simple/cpu.hh: dev/alpha_console.cc: dev/ide_ctrl.cc: use new methods for accessing packet data dev/ide_disk.cc: add some more dprintfs dev/io_device.cc: delete packets when we are done with them. Update for new packet methods to access data dev/isa_fake.cc: dev/pciconfigall.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: dev/uart8250.hh: mem/physical.cc: mem/port.cc: dUpdate for new packet methods to access data dev/ns_gige.cc: Update for new memory system dev/ns_gige.hh: python/m5/objects/Ethernet.py: update for new memory system dev/sinic.cc: dev/sinic.hh: Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions mem/packet.hh: Add methods to access data instead of accessing it directly. --HG-- extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e
2006-04-25 01:31:50 +02:00
dev/pcifake.cc
dev/pktfifo.cc
fixes for newmem ALPHA_FS finally compiles again SConscript: Use a couple more FS sources, still don't compile that much arch/alpha/faults.hh: the unimp fault should probably exist in nonfs too. dev/alpha_console.cc: dev/alpha_console.hh: dev/simconsole.cc: dev/simple_disk.cc: dev/simple_disk.hh: dev/uart.cc: dev/uart.hh: dev/uart8250.cc: dev/uart8250.hh: sim/process.cc: sim/system.cc: fixes for newmem dev/io_device.hh: a system pointer is probably useful for every device to have mem/bus.hh: mem/physical.cc: new address ranges function python/m5/objects/SimpleDisk.py: simple disk now has a system pointer rather than physmem directly --HG-- extra : convert_revision : d8c0a5c6510a6210aec5e8adfb0a4a06ec0dcebf
2006-04-06 20:57:51 +02:00
dev/platform.cc
dev/simconsole.cc
dev/simple_disk.cc
updates for newmem SConscript: compile some more devices --HG-- extra : convert_revision : 82a8164ab38814a56a0c143658bc06338cf6b8f5
2006-04-10 20:14:06 +02:00
dev/tsunami.cc
dev/tsunami_cchip.cc
dev/tsunami_io.cc
dev/tsunami_fake.cc
dev/tsunami_pchip.cc
fixes for newmem ALPHA_FS finally compiles again SConscript: Use a couple more FS sources, still don't compile that much arch/alpha/faults.hh: the unimp fault should probably exist in nonfs too. dev/alpha_console.cc: dev/alpha_console.hh: dev/simconsole.cc: dev/simple_disk.cc: dev/simple_disk.hh: dev/uart.cc: dev/uart.hh: dev/uart8250.cc: dev/uart8250.hh: sim/process.cc: sim/system.cc: fixes for newmem dev/io_device.hh: a system pointer is probably useful for every device to have mem/bus.hh: mem/physical.cc: new address ranges function python/m5/objects/SimpleDisk.py: simple disk now has a system pointer rather than physmem directly --HG-- extra : convert_revision : d8c0a5c6510a6210aec5e8adfb0a4a06ec0dcebf
2006-04-06 20:57:51 +02:00
dev/uart.cc
dev/uart8250.cc
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
kern/kernel_stats.cc
kern/system_events.cc
move alpha specific code into arch/alpha System -> AlphaSystem SConscript: Move some more files around arch/alpha/freebsd/system.cc: arch/alpha/freebsd/system.hh: System -> AlphaSystem arch/alpha/linux/aligned.hh: arch/alpha/linux/hwrpb.hh: arch/alpha/linux/system.cc: arch/alpha/linux/thread_info.hh: arch/alpha/linux/threadinfo.hh: move alpha specific code into arch/alpha python/m5/objects/System.py: Split off arch specific parts of system into AlphaSystem --HG-- rename : kern/freebsd/freebsd_system.cc => arch/alpha/freebsd/system.cc rename : kern/freebsd/freebsd_system.hh => arch/alpha/freebsd/system.hh rename : kern/linux/aligned.hh => arch/alpha/linux/aligned.hh rename : kern/linux/hwrpb.hh => arch/alpha/linux/hwrpb.hh rename : kern/linux/linux_system.cc => arch/alpha/linux/system.cc rename : kern/linux/linux_system.hh => arch/alpha/linux/system.hh rename : kern/linux/thread_info.hh => arch/alpha/linux/thread_info.hh rename : kern/linux/linux_threadinfo.hh => arch/alpha/linux/threadinfo.hh rename : kern/tru64/tru64_system.cc => arch/alpha/tru64/system.cc rename : kern/tru64/tru64_system.hh => arch/alpha/tru64/system.hh extra : convert_revision : 1c496efb823326a4b629574bd9b5f30e99a0aa40
2006-03-05 02:45:01 +01:00
kern/linux/events.cc
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
kern/linux/linux_syscalls.cc
added printk.cc to the sconsscript so it will actually build. SConscript: grrr, spent half an hour looking for why the linker was dying. needed to include the new file printk.cc --HG-- extra : convert_revision : 4c461d9dbe96e94d7c312bf71ee8ad4c87a3b1a1
2004-07-31 03:14:05 +02:00
kern/linux/printk.cc
Only compile in Tru64 objects if we're doing Alpha. --HG-- extra : convert_revision : 15bcdb3a6552ad8ee070677c9464ae1302768068
2006-03-29 05:44:24 +02:00
fixes for new memory system SConscript: comment out most devices add vport.cc arch/alpha/arguments.cc: arch/alpha/arguments.hh: push in alpha name space fix for new memory system arch/alpha/faults.cc: arch/alpha/faults.hh: Added an unimplemented fault that can be returned if a certain function isn't implemented arch/alpha/freebsd/system.cc: arch/alpha/linux/system.cc: arch/alpha/stacktrace.cc: arch/alpha/system.cc: arch/alpha/tlb.hh: arch/alpha/tru64/system.cc: fixed for new memory system arch/alpha/tlb.cc: fixed for new memory system removed code that seems to have no purpose arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: fixed for new memory system put in namespace AlphaISA base/remote_gdb.cc: fix for new memory system cpu/cpu_exec_context.cc: cpu/cpu_exec_context.hh: cpu/exec_context.hh: create two ports one of physical accesses and one for superpage accesses Add functions getVirtPort() getPhysPort() delVirtPort(). To get statically allocated physical or virtual ports or if an execcontext is passed in get a dynamically allocated virtual port dev/alpha_console.cc: dev/alpha_console.hh: Redo for new memory system dev/io_device.cc: dev/io_device.hh: new I/O devices for new memory system kern/linux/events.cc: kern/linux/printk.cc: kern/linux/printk.hh: kern/tru64/dump_mbuf.hh: kern/tru64/printf.cc: kern/tru64/printf.hh: Arguments now in namespaces kern/tru64/tru64_events.cc: mem/bus.cc: fix for new memory syste mem/physical.hh: new addressranges function getPort should be public mem/port.hh: Add write/read methods to functional port update getDeviceAddrRanges to have a list of both snoops and response lists sim/pseudo_inst.cc: sim/system.cc: sim/system.hh: Update for new mem system sim/vptr.hh: comment out code and replace with panics This will need to be fixed at some point, but it's not easy. --HG-- extra : convert_revision : 41f41f422cfbab3751284d55cccb6ea64a7956e2
2006-04-06 06:51:46 +02:00
mem/vport.cc
Only compile in Tru64 objects if we're doing Alpha. --HG-- extra : convert_revision : 15bcdb3a6552ad8ee070677c9464ae1302768068
2006-03-29 05:44:24 +02:00
sim/pseudo_inst.cc
''')
fixes for gcc 4.1 Nate needs to fix sinic builder stuff Gabe needs to verify my fixes to decoder.isa OPT/DEBUG compiles for ALPHA_FS, ALPHA_SE, MIPS_SE, SPARC_SE with this changeset README: Fix the swig version in the readme src/SConscript: remove sinic until nate fixes the builder crap for it src/arch/alpha/system.hh: src/arch/mips/isa/includes.isa: src/arch/sparc/isa/decoder.isa: src/base/stats/visit.cc: src/base/timebuf.hh: src/dev/ide_disk.cc: src/dev/sinic.cc: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr_queue.cc: src/mem/packet.hh: src/mem/request.hh: src/sim/builder.hh: src/sim/system.hh: fixes for gcc 4.1 --HG-- extra : convert_revision : 3775427c0047b282574d4831dd602c96cac3ba17
2006-08-15 23:41:22 +02:00
#dev/sinic.cc
Only compile in Tru64 objects if we're doing Alpha. --HG-- extra : convert_revision : 15bcdb3a6552ad8ee070677c9464ae1302768068
2006-03-29 05:44:24 +02:00
fixes for new memory system SConscript: comment out most devices add vport.cc arch/alpha/arguments.cc: arch/alpha/arguments.hh: push in alpha name space fix for new memory system arch/alpha/faults.cc: arch/alpha/faults.hh: Added an unimplemented fault that can be returned if a certain function isn't implemented arch/alpha/freebsd/system.cc: arch/alpha/linux/system.cc: arch/alpha/stacktrace.cc: arch/alpha/system.cc: arch/alpha/tlb.hh: arch/alpha/tru64/system.cc: fixed for new memory system arch/alpha/tlb.cc: fixed for new memory system removed code that seems to have no purpose arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: fixed for new memory system put in namespace AlphaISA base/remote_gdb.cc: fix for new memory system cpu/cpu_exec_context.cc: cpu/cpu_exec_context.hh: cpu/exec_context.hh: create two ports one of physical accesses and one for superpage accesses Add functions getVirtPort() getPhysPort() delVirtPort(). To get statically allocated physical or virtual ports or if an execcontext is passed in get a dynamically allocated virtual port dev/alpha_console.cc: dev/alpha_console.hh: Redo for new memory system dev/io_device.cc: dev/io_device.hh: new I/O devices for new memory system kern/linux/events.cc: kern/linux/printk.cc: kern/linux/printk.hh: kern/tru64/dump_mbuf.hh: kern/tru64/printf.cc: kern/tru64/printf.hh: Arguments now in namespaces kern/tru64/tru64_events.cc: mem/bus.cc: fix for new memory syste mem/physical.hh: new addressranges function getPort should be public mem/port.hh: Add write/read methods to functional port update getDeviceAddrRanges to have a list of both snoops and response lists sim/pseudo_inst.cc: sim/system.cc: sim/system.hh: Update for new mem system sim/vptr.hh: comment out code and replace with panics This will need to be fixed at some point, but it's not easy. --HG-- extra : convert_revision : 41f41f422cfbab3751284d55cccb6ea64a7956e2
2006-04-06 06:51:46 +02:00
Only compile in Tru64 objects if we're doing Alpha. --HG-- extra : convert_revision : 15bcdb3a6552ad8ee070677c9464ae1302768068
2006-03-29 05:44:24 +02:00
if env['TARGET_ISA'] == 'alpha':
full_system_sources += Split('''
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
kern/tru64/dump_mbuf.cc
kern/tru64/printf.cc
kern/tru64/tru64_events.cc
kern/tru64/tru64_syscalls.cc
''')
make all of the turbolaser stuff only compile if ALPHA_TLASER is defined. build/SConstruct: Default ALPHA_TLASER to false dev/uart8250.cc: fix paths --HG-- extra : convert_revision : 3616b5b4b9060860a73568a4ed4f1e8eb991938f
2005-06-05 07:24:17 +02:00
# turbolaser encumbered sources
turbolaser_sources = Split('''
encumbered/dev/dma.cc
encumbered/dev/etherdev.cc
encumbered/dev/scsi.cc
encumbered/dev/scsi_ctrl.cc
encumbered/dev/scsi_disk.cc
encumbered/dev/scsi_none.cc
encumbered/dev/tlaser_clock.cc
encumbered/dev/tlaser_ipi.cc
encumbered/dev/tlaser_mbox.cc
encumbered/dev/tlaser_mc146818.cc
encumbered/dev/tlaser_node.cc
encumbered/dev/tlaser_pcia.cc
encumbered/dev/tlaser_pcidev.cc
encumbered/dev/tlaser_serial.cc
encumbered/dev/turbolaser.cc
encumbered/dev/uart8530.cc
''')
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
# Syscall emulation (non-full-system) sources
syscall_emulation_sources = Split('''
Add a functional port that is used to load the original binaries in FS SE mode now has a port that goes to whatever toplevel mem object the CPU sees that does the appropriate translation for syscall emulation SConscript: translating port is a syscall emu only source arch/alpha/system.cc: base/loader/object_file.cc: base/loader/object_file.hh: Use the new functional port to write the binaries into memory cpu/cpu_exec_context.cc: cpu/cpu_exec_context.hh: cpu/simple/cpu.cc: We aren't always going to be writing straight to memory with syscalls support writing to a cache mem/port.hh: Add a simple unidirectional functional port that panics on any incoming requests mem/translating_port.hh: make translating port inherit from the simple port sim/system.cc: sim/system.hh: Add a functional port that is used to load the original binaries --HG-- extra : convert_revision : 9096866d0b23e3aceea68394abb76e63c0f8fd8d
2006-03-31 01:06:00 +02:00
mem/translating_port.cc
page_table.cc is a syscall only kinda thing fix tlbs for newmem SConscript: page_table.cc is a syscall only kinda thing arch/alpha/tlb.cc: arch/alpha/tlb.hh: fix tlbs for newmem --HG-- extra : convert_revision : 0aafcb9698b993a807be883bde1696ee4d33b408
2006-03-30 01:42:53 +02:00
mem/page_table.cc
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
sim/process.cc
sim/syscall_emul.cc
''')
Changes that get rid of the OSFlags and derive a new class of this format <architecture>-<OS>. This class is derived from the original <OS> class and is used to define information that is both architecure and OS specific (for example, the AlphaLinux class is derived from the Linux class and defined in arch/alpha/linux/linux.hh). SConscript: no need to compile linux.cc and tru64.cc now, since openFlagsTable has been moved arch/alpha/SConscript: compile linux.cc and tru64.cc within alpha arch. arch/alpha/linux/process.cc: template syscall functions on AlphaLinux instead of Linux ... AlphaLinux is derived off of Linux arch/alpha/tru64/process.cc: template syscall functions on AlphaTru64 instead of Linux ... AlphaTru64 is derived off of Linux moved tableFunc syscall function into this file arch/mips/SConscript: compile mips_linux.cc for openFlags table arch/mips/isa_traits.hh: remove constants from here arch/mips/linux_process.cc: template syscall functions on MipsLinux instead of Linux ... MipsLinux is derived off of Linux kern/linux/linux.hh: remove OSFlags kern/tru64/tru64.hh: remove OSFlags def., openFlagTable, and tableFunc ... sim/syscall_emul.hh: go back to using "OS" instead of "OSFlags" arch/alpha/linux/linux.cc: defines openFlagTable arch/alpha/linux/linux.hh: arch/alpha/tru64/tru64.hh: Alpha Linux constants placed here in class derived from Linux class arch/alpha/tru64/tru64.cc: defines openFlagTable for AlphaTru64 arch/mips/mips_linux.cc: MIPS Linux open flag table arch/mips/mips_linux.hh: Mips Linux constants placed here in class derived from Linux class --HG-- extra : convert_revision : e6c1c2c895429c28fd141732e223e897ab19315e
2006-04-13 11:42:18 +02:00
#if env['TARGET_ISA'] == 'alpha':
# syscall_emulation_sources += Split('''
# kern/tru64/tru64.cc
# ''')
Only compile in Tru64 objects if we're doing Alpha. --HG-- extra : convert_revision : 15bcdb3a6552ad8ee070677c9464ae1302768068
2006-03-29 05:44:24 +02:00
Minor Sconscript edit ... mips decoder changes ... initialize NNPC and output fault name in simple cpu SConscript: Separate Alpha EIO from syscall building for other architectures arch/isa_specific.hh: change MIPS constant to 34k arch/mips/isa/decoder.isa: Allow sll,ssnop,nop, and ehb to be determined through decoder using the different types of default cases arch/mips/isa/formats/branch.isa: Delete debug code arch/mips/isa/formats/noop.isa: add a Nop format arch/mips/isa_traits.hh: use constants instead of enums arch/mips/process.cc: point to the correct header file cpu/simple/cpu.cc: Output the actual fault name sim/process.cc: Inititalize NNPC --HG-- extra : convert_revision : adb0026dfad25b14c98fb03c98bfe9c681bba6f8
2006-03-15 00:28:51 +01:00
alpha_eio_sources = Split('''
encumbered/eio/exolex.cc
encumbered/eio/libexo.cc
encumbered/eio/eio.cc
''')
Be sure to include the EIO sources as well so we can run regression tests. src/SConscript: It's no longer "ALPHA_ISA". I don't think we meant to leave out the EIO sources. --HG-- extra : convert_revision : 1ca63ffb571d9021f1ced0bf0df1816b0b798edc
2006-07-12 23:20:01 +02:00
if env['TARGET_ISA'] == 'alpha':
Minor Sconscript edit ... mips decoder changes ... initialize NNPC and output fault name in simple cpu SConscript: Separate Alpha EIO from syscall building for other architectures arch/isa_specific.hh: change MIPS constant to 34k arch/mips/isa/decoder.isa: Allow sll,ssnop,nop, and ehb to be determined through decoder using the different types of default cases arch/mips/isa/formats/branch.isa: Delete debug code arch/mips/isa/formats/noop.isa: add a Nop format arch/mips/isa_traits.hh: use constants instead of enums arch/mips/process.cc: point to the correct header file cpu/simple/cpu.cc: Output the actual fault name sim/process.cc: Inititalize NNPC --HG-- extra : convert_revision : adb0026dfad25b14c98fb03c98bfe9c681bba6f8
2006-03-15 00:28:51 +01:00
syscall_emulation_sources += alpha_eio_sources
Add in a new translating port that allows syscalls to translate addresses via the page table before accessing the memory port. Other compile issues cleaned up. SConscript: Changes to compile the new Translating Port. Split out memtester and eio support, will rework them back in after first getting a simpleCPU to work arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_tru64_process.cc: sim/syscall_emul.cc: sim/syscall_emul.hh: Changes to use the new translating Port. cpu/exec_context.cc: cpu/exec_context.hh: Create a translating port in each execution context. sim/process.cc: Fix the way we do proxy memory --HG-- extra : convert_revision : 3d33218fe8b425a5d9ce24757f1112b4aa6001fd
2006-02-21 05:26:39 +01:00
memtest_sources = Split('''
cpu/memtest/memtest.cc
''')
Move main control from C++ into Python. User script now invokes initialization and simulation loop after building configuration. These functions are exported from C++ to Python using SWIG. SConstruct: Set up SWIG builder & scanner. Set up symlinking of source files into build directory (by not disabling the default behavior). configs/test/test.py: Rewrite to use new script-driven interface. Include a sample option. src/SConscript: Set up symlinking of source files into build directory (by not disabling the default behavior). Add SWIG-generated main_wrap.cc to source list. src/arch/SConscript: Set up symlinking of source files into build directory (by not disabling the default behavior). src/arch/alpha/ev5.cc: src/arch/alpha/isa/decoder.isa: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/trace/opt_cpu.cc: src/cpu/trace/trace_cpu.cc: src/sim/pseudo_inst.cc: src/sim/root.cc: src/sim/serialize.cc: src/sim/syscall_emul.cc: SimExit() is now exitSimLoop(). src/cpu/base.cc: SimExitEvent is now SimLoopExitEvent src/python/SConscript: Add SWIG build command for main.i. Use python/m5 in build dir as source for zip archive... easy now with file duplication enabled. src/python/m5/__init__.py: - Move copyright notice back to C++ so we can print it right away, even for interactive sessions. - Get rid of argument parsing code; just provide default option descriptors for user script to call optparse with. - Don't clutter m5 namespace by sucking in all of m5.config and m5.objects. - Move instantiate() function here from config.py. src/python/m5/config.py: - Move instantiate() function to __init__.py. - Param.Foo deferred type lookups must use m5.objects namespace now (not m5). src/python/m5/objects/AlphaConsole.py: src/python/m5/objects/AlphaFullCPU.py: src/python/m5/objects/AlphaTLB.py: src/python/m5/objects/BadDevice.py: src/python/m5/objects/BaseCPU.py: src/python/m5/objects/BaseCache.py: src/python/m5/objects/Bridge.py: src/python/m5/objects/Bus.py: src/python/m5/objects/CoherenceProtocol.py: src/python/m5/objects/Device.py: src/python/m5/objects/DiskImage.py: src/python/m5/objects/Ethernet.py: src/python/m5/objects/Ide.py: src/python/m5/objects/IntrControl.py: src/python/m5/objects/MemObject.py: src/python/m5/objects/MemTest.py: src/python/m5/objects/Pci.py: src/python/m5/objects/PhysicalMemory.py: src/python/m5/objects/Platform.py: src/python/m5/objects/Process.py: src/python/m5/objects/Repl.py: src/python/m5/objects/Root.py: src/python/m5/objects/SimConsole.py: src/python/m5/objects/SimpleDisk.py: src/python/m5/objects/System.py: src/python/m5/objects/Tsunami.py: src/python/m5/objects/Uart.py: Fix up imports (m5 namespace no longer includes m5.config). src/sim/eventq.cc: src/sim/eventq.hh: Support for Python-called simulate() function: - Use IsExitEvent flag to signal events that want to exit the simulation loop gracefully (instead of calling exit() to terminate the process). - Modify interface to hand exit event object back to caller so it can be inspected for cause. src/sim/host.hh: Add MaxTick constant. src/sim/main.cc: Move copyright notice back to C++ so we can print it right away, even for interactive sessions. Use PYTHONPATH environment var to set module path (instead of clunky code injection method). Move main control from here into Python: - Separate initialization code and simulation loop into separate functions callable from Python. - Make Python interpreter invocation more pure (more like directly invoking interpreter). Add -i and -p flags (only options on binary itself; other options processed by Python). Import readline package when using interactive mode. src/sim/sim_events.cc: SimExitEvent is now SimLoopExitEvent, and uses IsSimExit flag to terminate loop (instead of exiting simulator process). src/sim/sim_events.hh: SimExitEvent is now SimLoopExitEvent, and uses IsSimExit flag to terminate loop (instead of exiting simulator process). Get rid of a few unused constructors. src/sim/sim_exit.hh: SimExit() is now exitSimLoop(). Get rid of unused functions. Add comments. --HG-- extra : convert_revision : 280b0d671516b25545a6f24cefa64a68319ff3d4
2006-06-10 05:01:31 +02:00
# Include file paths are rooted in this directory. SCons will
# automatically expand '.' to refer to both the source directory and
# the corresponding build directory to pick up generated include
# files.
env.Append(CPPPATH=Dir('.'))
Alot of changes to push towards ISA independence. Highlights are renaming of the isa_desc files, movement of byte_swap.hh into sim, and the creation of arch/isa_traits.hh SConscript: Moved some files out of targetarch. The either no longer need to be there, never needed to be there, or should be referred to directly in arch/alpha due to there strictly alpha content. arch/alpha/isa_traits.hh: Added alpha's endianness to it's isa_traits.hh arch/mips/isa_traits.hh: Added MIPS endianness to it's isa_traits.hh arch/sparc/isa_traits.hh: Added SPARCs endianess to it's isa_traits.hh build/SConstruct: Added MIPS as a valid architecture cpu/exec_context.hh: Included arch/isa_traits.hh to bring in the endianness of the system. cpu/o3/alpha_cpu.hh: Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding of little endianness cpu/o3/fetch_impl.hh: kern/freebsd/freebsd_system.cc: Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endianness. sim/system.cc: Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endian. --HG-- extra : convert_revision : b1ab34b7569db531cd1c74f273b24222e63f9007
2006-02-08 07:03:55 +01:00
# Add a flag defining what THE_ISA should be for all compilation
env.Append(CPPDEFINES=[('THE_ISA','%s_ISA' % env['TARGET_ISA'].upper())])
Make targetarch directory in build tree and copy arch/alpha files to it instead of using symlink. The symlink broke scons's built-in include dependency tacking. Interestingly once it was fixed scons discovered two circular dependency problems which are also fixed now. SConscript: Make targetarch directory in build tree and copy arch/alpha files to it instead of using symlink. The symlink broke scons's built-in include dependency tacking. arch/alpha/ev5.hh: Get rid of circular #include dependence. kern/kernel_stats.cc: Add needed header file. kern/linux/linux_syscalls.hh: kern/tru64/tru64_syscalls.hh: Replace targetarch/syscalls.hh with single template class declaration. --HG-- extra : convert_revision : b8551623c1d441c6eb8d0651387e97e373128814
2004-10-23 04:49:12 +02:00
Move main control from C++ into Python. User script now invokes initialization and simulation loop after building configuration. These functions are exported from C++ to Python using SWIG. SConstruct: Set up SWIG builder & scanner. Set up symlinking of source files into build directory (by not disabling the default behavior). configs/test/test.py: Rewrite to use new script-driven interface. Include a sample option. src/SConscript: Set up symlinking of source files into build directory (by not disabling the default behavior). Add SWIG-generated main_wrap.cc to source list. src/arch/SConscript: Set up symlinking of source files into build directory (by not disabling the default behavior). src/arch/alpha/ev5.cc: src/arch/alpha/isa/decoder.isa: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/trace/opt_cpu.cc: src/cpu/trace/trace_cpu.cc: src/sim/pseudo_inst.cc: src/sim/root.cc: src/sim/serialize.cc: src/sim/syscall_emul.cc: SimExit() is now exitSimLoop(). src/cpu/base.cc: SimExitEvent is now SimLoopExitEvent src/python/SConscript: Add SWIG build command for main.i. Use python/m5 in build dir as source for zip archive... easy now with file duplication enabled. src/python/m5/__init__.py: - Move copyright notice back to C++ so we can print it right away, even for interactive sessions. - Get rid of argument parsing code; just provide default option descriptors for user script to call optparse with. - Don't clutter m5 namespace by sucking in all of m5.config and m5.objects. - Move instantiate() function here from config.py. src/python/m5/config.py: - Move instantiate() function to __init__.py. - Param.Foo deferred type lookups must use m5.objects namespace now (not m5). src/python/m5/objects/AlphaConsole.py: src/python/m5/objects/AlphaFullCPU.py: src/python/m5/objects/AlphaTLB.py: src/python/m5/objects/BadDevice.py: src/python/m5/objects/BaseCPU.py: src/python/m5/objects/BaseCache.py: src/python/m5/objects/Bridge.py: src/python/m5/objects/Bus.py: src/python/m5/objects/CoherenceProtocol.py: src/python/m5/objects/Device.py: src/python/m5/objects/DiskImage.py: src/python/m5/objects/Ethernet.py: src/python/m5/objects/Ide.py: src/python/m5/objects/IntrControl.py: src/python/m5/objects/MemObject.py: src/python/m5/objects/MemTest.py: src/python/m5/objects/Pci.py: src/python/m5/objects/PhysicalMemory.py: src/python/m5/objects/Platform.py: src/python/m5/objects/Process.py: src/python/m5/objects/Repl.py: src/python/m5/objects/Root.py: src/python/m5/objects/SimConsole.py: src/python/m5/objects/SimpleDisk.py: src/python/m5/objects/System.py: src/python/m5/objects/Tsunami.py: src/python/m5/objects/Uart.py: Fix up imports (m5 namespace no longer includes m5.config). src/sim/eventq.cc: src/sim/eventq.hh: Support for Python-called simulate() function: - Use IsExitEvent flag to signal events that want to exit the simulation loop gracefully (instead of calling exit() to terminate the process). - Modify interface to hand exit event object back to caller so it can be inspected for cause. src/sim/host.hh: Add MaxTick constant. src/sim/main.cc: Move copyright notice back to C++ so we can print it right away, even for interactive sessions. Use PYTHONPATH environment var to set module path (instead of clunky code injection method). Move main control from here into Python: - Separate initialization code and simulation loop into separate functions callable from Python. - Make Python interpreter invocation more pure (more like directly invoking interpreter). Add -i and -p flags (only options on binary itself; other options processed by Python). Import readline package when using interactive mode. src/sim/sim_events.cc: SimExitEvent is now SimLoopExitEvent, and uses IsSimExit flag to terminate loop (instead of exiting simulator process). src/sim/sim_events.hh: SimExitEvent is now SimLoopExitEvent, and uses IsSimExit flag to terminate loop (instead of exiting simulator process). Get rid of a few unused constructors. src/sim/sim_exit.hh: SimExit() is now exitSimLoop(). Get rid of unused functions. Add comments. --HG-- extra : convert_revision : 280b0d671516b25545a6f24cefa64a68319ff3d4
2006-06-10 05:01:31 +02:00
arch_sources = SConscript('arch/SConscript', exports = 'env')
Make targetarch directory in build tree and copy arch/alpha files to it instead of using symlink. The symlink broke scons's built-in include dependency tacking. Interestingly once it was fixed scons discovered two circular dependency problems which are also fixed now. SConscript: Make targetarch directory in build tree and copy arch/alpha files to it instead of using symlink. The symlink broke scons's built-in include dependency tacking. arch/alpha/ev5.hh: Get rid of circular #include dependence. kern/kernel_stats.cc: Add needed header file. kern/linux/linux_syscalls.hh: kern/tru64/tru64_syscalls.hh: Replace targetarch/syscalls.hh with single template class declaration. --HG-- extra : convert_revision : b8551623c1d441c6eb8d0651387e97e373128814
2004-10-23 04:49:12 +02:00
Move main control from C++ into Python. User script now invokes initialization and simulation loop after building configuration. These functions are exported from C++ to Python using SWIG. SConstruct: Set up SWIG builder & scanner. Set up symlinking of source files into build directory (by not disabling the default behavior). configs/test/test.py: Rewrite to use new script-driven interface. Include a sample option. src/SConscript: Set up symlinking of source files into build directory (by not disabling the default behavior). Add SWIG-generated main_wrap.cc to source list. src/arch/SConscript: Set up symlinking of source files into build directory (by not disabling the default behavior). src/arch/alpha/ev5.cc: src/arch/alpha/isa/decoder.isa: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/trace/opt_cpu.cc: src/cpu/trace/trace_cpu.cc: src/sim/pseudo_inst.cc: src/sim/root.cc: src/sim/serialize.cc: src/sim/syscall_emul.cc: SimExit() is now exitSimLoop(). src/cpu/base.cc: SimExitEvent is now SimLoopExitEvent src/python/SConscript: Add SWIG build command for main.i. Use python/m5 in build dir as source for zip archive... easy now with file duplication enabled. src/python/m5/__init__.py: - Move copyright notice back to C++ so we can print it right away, even for interactive sessions. - Get rid of argument parsing code; just provide default option descriptors for user script to call optparse with. - Don't clutter m5 namespace by sucking in all of m5.config and m5.objects. - Move instantiate() function here from config.py. src/python/m5/config.py: - Move instantiate() function to __init__.py. - Param.Foo deferred type lookups must use m5.objects namespace now (not m5). src/python/m5/objects/AlphaConsole.py: src/python/m5/objects/AlphaFullCPU.py: src/python/m5/objects/AlphaTLB.py: src/python/m5/objects/BadDevice.py: src/python/m5/objects/BaseCPU.py: src/python/m5/objects/BaseCache.py: src/python/m5/objects/Bridge.py: src/python/m5/objects/Bus.py: src/python/m5/objects/CoherenceProtocol.py: src/python/m5/objects/Device.py: src/python/m5/objects/DiskImage.py: src/python/m5/objects/Ethernet.py: src/python/m5/objects/Ide.py: src/python/m5/objects/IntrControl.py: src/python/m5/objects/MemObject.py: src/python/m5/objects/MemTest.py: src/python/m5/objects/Pci.py: src/python/m5/objects/PhysicalMemory.py: src/python/m5/objects/Platform.py: src/python/m5/objects/Process.py: src/python/m5/objects/Repl.py: src/python/m5/objects/Root.py: src/python/m5/objects/SimConsole.py: src/python/m5/objects/SimpleDisk.py: src/python/m5/objects/System.py: src/python/m5/objects/Tsunami.py: src/python/m5/objects/Uart.py: Fix up imports (m5 namespace no longer includes m5.config). src/sim/eventq.cc: src/sim/eventq.hh: Support for Python-called simulate() function: - Use IsExitEvent flag to signal events that want to exit the simulation loop gracefully (instead of calling exit() to terminate the process). - Modify interface to hand exit event object back to caller so it can be inspected for cause. src/sim/host.hh: Add MaxTick constant. src/sim/main.cc: Move copyright notice back to C++ so we can print it right away, even for interactive sessions. Use PYTHONPATH environment var to set module path (instead of clunky code injection method). Move main control from here into Python: - Separate initialization code and simulation loop into separate functions callable from Python. - Make Python interpreter invocation more pure (more like directly invoking interpreter). Add -i and -p flags (only options on binary itself; other options processed by Python). Import readline package when using interactive mode. src/sim/sim_events.cc: SimExitEvent is now SimLoopExitEvent, and uses IsSimExit flag to terminate loop (instead of exiting simulator process). src/sim/sim_events.hh: SimExitEvent is now SimLoopExitEvent, and uses IsSimExit flag to terminate loop (instead of exiting simulator process). Get rid of a few unused constructors. src/sim/sim_exit.hh: SimExit() is now exitSimLoop(). Get rid of unused functions. Add comments. --HG-- extra : convert_revision : 280b0d671516b25545a6f24cefa64a68319ff3d4
2006-06-10 05:01:31 +02:00
cpu_sources = SConscript('cpu/SConscript', exports = 'env')
Enable building only selected CPU models via new scons CPU_MODELS parameter. For example: scons CPU_MODELS="SimpleCPU,FullCPU" ALPHA_SE/m5.debug Unfortunately the option is not sticky due to a scons bug with saving & restoring ListOption parameters. SConscript: Separate out cpu-model-specific files so they can be conditionally included based on value of new CPU_MODELS parameter. Most of these are now handled in cpu/SConscript, except for FullCPU which is still in this file. arch/SConscript: The set of CPU-model-specific execute files must now be determined from the CPU_MODELS parameter, via the new cpu_models.py file. Also pass the list of configured CPU models to isa_parser.py. arch/isa_parser.py: Move CpuModel definition and objects out to a separate file so they can be shared with scons. Global list of CPU models to generate code for is now controlled by command-line parameters (so we can do only a subset of the available ones). build/SConstruct: Define new CPU_MODELS ListOption. cpu/static_inst.hh: Rename static_inst_impl.hh to static_inst_exec_sigs.hh. --HG-- extra : convert_revision : 163df32a76d4c05900490b2bce4c7962a5e3f614
2006-02-23 23:00:29 +01:00
# This is outside of cpu/SConscript since the source directory isn't
# underneath 'cpu'.
if 'FullCPU' in env['CPU_MODELS']:
cpu_sources += full_cpu_sources
Make targetarch directory in build tree and copy arch/alpha files to it instead of using symlink. The symlink broke scons's built-in include dependency tacking. Interestingly once it was fixed scons discovered two circular dependency problems which are also fixed now. SConscript: Make targetarch directory in build tree and copy arch/alpha files to it instead of using symlink. The symlink broke scons's built-in include dependency tacking. arch/alpha/ev5.hh: Get rid of circular #include dependence. kern/kernel_stats.cc: Add needed header file. kern/linux/linux_syscalls.hh: kern/tru64/tru64_syscalls.hh: Replace targetarch/syscalls.hh with single template class declaration. --HG-- extra : convert_revision : b8551623c1d441c6eb8d0651387e97e373128814
2004-10-23 04:49:12 +02:00
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
# Set up complete list of sources based on configuration.
Enable building only selected CPU models via new scons CPU_MODELS parameter. For example: scons CPU_MODELS="SimpleCPU,FullCPU" ALPHA_SE/m5.debug Unfortunately the option is not sticky due to a scons bug with saving & restoring ListOption parameters. SConscript: Separate out cpu-model-specific files so they can be conditionally included based on value of new CPU_MODELS parameter. Most of these are now handled in cpu/SConscript, except for FullCPU which is still in this file. arch/SConscript: The set of CPU-model-specific execute files must now be determined from the CPU_MODELS parameter, via the new cpu_models.py file. Also pass the list of configured CPU models to isa_parser.py. arch/isa_parser.py: Move CpuModel definition and objects out to a separate file so they can be shared with scons. Global list of CPU models to generate code for is now controlled by command-line parameters (so we can do only a subset of the available ones). build/SConstruct: Define new CPU_MODELS ListOption. cpu/static_inst.hh: Rename static_inst_impl.hh to static_inst_exec_sigs.hh. --HG-- extra : convert_revision : 163df32a76d4c05900490b2bce4c7962a5e3f614
2006-02-23 23:00:29 +01:00
sources = base_sources + arch_sources + cpu_sources
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
if env['FULL_SYSTEM']:
sources += full_system_sources
make all of the turbolaser stuff only compile if ALPHA_TLASER is defined. build/SConstruct: Default ALPHA_TLASER to false dev/uart8250.cc: fix paths --HG-- extra : convert_revision : 3616b5b4b9060860a73568a4ed4f1e8eb991938f
2005-06-05 07:24:17 +02:00
if env['ALPHA_TLASER']:
sources += turbolaser_sources
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
else:
sources += syscall_emulation_sources
Build options are set via a build_options file in the build directory instead of being inferred from the name of the build directory. Options are passed to C++ via config/*.hh files instead of via the command line. Build option flags are now always defined to 0 or 1, so checks must use '#if' rather than '#ifdef'. SConscript: MySQL detection moved to SConstruct. Add config/*.hh files (via ConfigFile builder). arch/alpha/alpha_memory.cc: arch/alpha/ev5.cc: arch/alpha/ev5.hh: arch/alpha/isa_traits.hh: base/fast_alloc.hh: base/statistics.cc: base/statistics.hh: base/stats/events.cc: base/stats/events.hh: cpu/base.cc: cpu/base.hh: cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/o3/alpha_cpu.hh: cpu/o3/alpha_cpu_builder.cc: cpu/o3/alpha_cpu_impl.hh: cpu/o3/alpha_dyn_inst.hh: cpu/o3/alpha_dyn_inst_impl.hh: cpu/o3/alpha_params.hh: cpu/o3/commit_impl.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: cpu/o3/fetch_impl.hh: cpu/o3/iew.hh: cpu/o3/iew_impl.hh: cpu/o3/regfile.hh: cpu/o3/rename_impl.hh: cpu/o3/rob_impl.hh: cpu/ozone/cpu.hh: cpu/pc_event.cc: cpu/simple/cpu.cc: cpu/simple/cpu.hh: sim/process.cc: sim/process.hh: Convert compile flags from def/undef to 0/1. Set via #include config/*.hh instead of command line. arch/alpha/isa_desc: Convert compile flags from def/undef to 0/1. Set via #include config/*.hh instead of command line. Revamp fenv.h support... most of the ugliness is hidden in base/fenv.hh now. base/mysql.hh: Fix typo in #ifndef guard. build/SConstruct: Build options are set via a build_options file in the build directory instead of being inferred from the name of the build directory. Options are passed to C++ via config/*.hh files instead of via the command line. python/SConscript: Generate m5_build_env directly from scons options instead of indirectly via CPPDEFINES. python/m5/convert.py: Allow '0' and '1' for booleans. Rewrite toBool to use dict. base/fenv.hh: Revamp <fenv.h> support to make it a compile option (so we can test w/o it even if it's present) and to make isa_desc cleaner. --HG-- extra : convert_revision : 8f97dc11185bef5e1865b3269c7341df8525c9ad
2005-08-30 19:18:54 +02:00
if env['USE_MYSQL']:
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
sources += mysql_sources
Build options are set via a build_options file in the build directory instead of being inferred from the name of the build directory. Options are passed to C++ via config/*.hh files instead of via the command line. Build option flags are now always defined to 0 or 1, so checks must use '#if' rather than '#ifdef'. SConscript: MySQL detection moved to SConstruct. Add config/*.hh files (via ConfigFile builder). arch/alpha/alpha_memory.cc: arch/alpha/ev5.cc: arch/alpha/ev5.hh: arch/alpha/isa_traits.hh: base/fast_alloc.hh: base/statistics.cc: base/statistics.hh: base/stats/events.cc: base/stats/events.hh: cpu/base.cc: cpu/base.hh: cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/o3/alpha_cpu.hh: cpu/o3/alpha_cpu_builder.cc: cpu/o3/alpha_cpu_impl.hh: cpu/o3/alpha_dyn_inst.hh: cpu/o3/alpha_dyn_inst_impl.hh: cpu/o3/alpha_params.hh: cpu/o3/commit_impl.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: cpu/o3/fetch_impl.hh: cpu/o3/iew.hh: cpu/o3/iew_impl.hh: cpu/o3/regfile.hh: cpu/o3/rename_impl.hh: cpu/o3/rob_impl.hh: cpu/ozone/cpu.hh: cpu/pc_event.cc: cpu/simple/cpu.cc: cpu/simple/cpu.hh: sim/process.cc: sim/process.hh: Convert compile flags from def/undef to 0/1. Set via #include config/*.hh instead of command line. arch/alpha/isa_desc: Convert compile flags from def/undef to 0/1. Set via #include config/*.hh instead of command line. Revamp fenv.h support... most of the ugliness is hidden in base/fenv.hh now. base/mysql.hh: Fix typo in #ifndef guard. build/SConstruct: Build options are set via a build_options file in the build directory instead of being inferred from the name of the build directory. Options are passed to C++ via config/*.hh files instead of via the command line. python/SConscript: Generate m5_build_env directly from scons options instead of indirectly via CPPDEFINES. python/m5/convert.py: Allow '0' and '1' for booleans. Rewrite toBool to use dict. base/fenv.hh: Revamp <fenv.h> support to make it a compile option (so we can test w/o it even if it's present) and to make isa_desc cleaner. --HG-- extra : convert_revision : 8f97dc11185bef5e1865b3269c7341df8525c9ad
2005-08-30 19:18:54 +02:00
for opt in env.ExportOptions:
env.ConfigFile(opt)
pc event now clears lower 2 bits always build with dynamic libraries for mysqlclient SConscript: always use dynamic library now cpu/pc_event.hh: cleared lower 2 bits, since everything must be 4byte aligned --HG-- extra : convert_revision : 332ecd25a598e6a46a79bd653449aa7eb22a580a
2004-09-16 21:11:38 +02:00
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
###################################################
#
# Special build rules.
#
###################################################
# base/traceflags.{cc,hh} are generated from base/traceflags.py.
# $TARGET.base will expand to "<build-dir>/base/traceflags".
env.Command(Split('base/traceflags.hh base/traceflags.cc'),
'base/traceflags.py',
'python $SOURCE $TARGET.base')
Move main control from C++ into Python. User script now invokes initialization and simulation loop after building configuration. These functions are exported from C++ to Python using SWIG. SConstruct: Set up SWIG builder & scanner. Set up symlinking of source files into build directory (by not disabling the default behavior). configs/test/test.py: Rewrite to use new script-driven interface. Include a sample option. src/SConscript: Set up symlinking of source files into build directory (by not disabling the default behavior). Add SWIG-generated main_wrap.cc to source list. src/arch/SConscript: Set up symlinking of source files into build directory (by not disabling the default behavior). src/arch/alpha/ev5.cc: src/arch/alpha/isa/decoder.isa: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/trace/opt_cpu.cc: src/cpu/trace/trace_cpu.cc: src/sim/pseudo_inst.cc: src/sim/root.cc: src/sim/serialize.cc: src/sim/syscall_emul.cc: SimExit() is now exitSimLoop(). src/cpu/base.cc: SimExitEvent is now SimLoopExitEvent src/python/SConscript: Add SWIG build command for main.i. Use python/m5 in build dir as source for zip archive... easy now with file duplication enabled. src/python/m5/__init__.py: - Move copyright notice back to C++ so we can print it right away, even for interactive sessions. - Get rid of argument parsing code; just provide default option descriptors for user script to call optparse with. - Don't clutter m5 namespace by sucking in all of m5.config and m5.objects. - Move instantiate() function here from config.py. src/python/m5/config.py: - Move instantiate() function to __init__.py. - Param.Foo deferred type lookups must use m5.objects namespace now (not m5). src/python/m5/objects/AlphaConsole.py: src/python/m5/objects/AlphaFullCPU.py: src/python/m5/objects/AlphaTLB.py: src/python/m5/objects/BadDevice.py: src/python/m5/objects/BaseCPU.py: src/python/m5/objects/BaseCache.py: src/python/m5/objects/Bridge.py: src/python/m5/objects/Bus.py: src/python/m5/objects/CoherenceProtocol.py: src/python/m5/objects/Device.py: src/python/m5/objects/DiskImage.py: src/python/m5/objects/Ethernet.py: src/python/m5/objects/Ide.py: src/python/m5/objects/IntrControl.py: src/python/m5/objects/MemObject.py: src/python/m5/objects/MemTest.py: src/python/m5/objects/Pci.py: src/python/m5/objects/PhysicalMemory.py: src/python/m5/objects/Platform.py: src/python/m5/objects/Process.py: src/python/m5/objects/Repl.py: src/python/m5/objects/Root.py: src/python/m5/objects/SimConsole.py: src/python/m5/objects/SimpleDisk.py: src/python/m5/objects/System.py: src/python/m5/objects/Tsunami.py: src/python/m5/objects/Uart.py: Fix up imports (m5 namespace no longer includes m5.config). src/sim/eventq.cc: src/sim/eventq.hh: Support for Python-called simulate() function: - Use IsExitEvent flag to signal events that want to exit the simulation loop gracefully (instead of calling exit() to terminate the process). - Modify interface to hand exit event object back to caller so it can be inspected for cause. src/sim/host.hh: Add MaxTick constant. src/sim/main.cc: Move copyright notice back to C++ so we can print it right away, even for interactive sessions. Use PYTHONPATH environment var to set module path (instead of clunky code injection method). Move main control from here into Python: - Separate initialization code and simulation loop into separate functions callable from Python. - Make Python interpreter invocation more pure (more like directly invoking interpreter). Add -i and -p flags (only options on binary itself; other options processed by Python). Import readline package when using interactive mode. src/sim/sim_events.cc: SimExitEvent is now SimLoopExitEvent, and uses IsSimExit flag to terminate loop (instead of exiting simulator process). src/sim/sim_events.hh: SimExitEvent is now SimLoopExitEvent, and uses IsSimExit flag to terminate loop (instead of exiting simulator process). Get rid of a few unused constructors. src/sim/sim_exit.hh: SimExit() is now exitSimLoop(). Get rid of unused functions. Add comments. --HG-- extra : convert_revision : 280b0d671516b25545a6f24cefa64a68319ff3d4
2006-06-10 05:01:31 +02:00
SConscript('python/SConscript', exports = ['env'])
Move libelf/SConscript include to m5/SConscript, so elf headers get created in build tree (under build/FOO/libelf) instead of source tree (m5/libelf). SConscript: Move libelf/SConscript include here. build/SConstruct: Get rid of libelf/SConscript include (moved to m5/SConscript). --HG-- extra : convert_revision : c0acb3bab2afa5079748b907c5917f548582099e
2004-08-04 07:46:03 +02:00
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
# This function adds the specified sources to the given build
# environment, and returns a list of all the corresponding SCons
# Object nodes (including an extra one for date.cc). We explicitly
# add the Object nodes so we can set up special dependencies for
Make targetarch directory in build tree and copy arch/alpha files to it instead of using symlink. The symlink broke scons's built-in include dependency tacking. Interestingly once it was fixed scons discovered two circular dependency problems which are also fixed now. SConscript: Make targetarch directory in build tree and copy arch/alpha files to it instead of using symlink. The symlink broke scons's built-in include dependency tacking. arch/alpha/ev5.hh: Get rid of circular #include dependence. kern/kernel_stats.cc: Add needed header file. kern/linux/linux_syscalls.hh: kern/tru64/tru64_syscalls.hh: Replace targetarch/syscalls.hh with single template class declaration. --HG-- extra : convert_revision : b8551623c1d441c6eb8d0651387e97e373128814
2004-10-23 04:49:12 +02:00
# date.cc.
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
def make_objs(sources, env):
objs = [env.Object(s) for s in sources]
# make date.cc depend on all other objects so it always gets
# recompiled whenever anything else does
date_obj = env.Object('base/date.cc')
env.Depends(date_obj, objs)
objs.append(date_obj)
return objs
###################################################
#
# Define binaries. Each different build type (debug, opt, etc.) gets
# a slightly different build environment.
#
###################################################
Link in Python interpreter. Use embedded zip archive to carry Python code instead of homegrown embedded string/file mechanism. Do argument parsing in Python instead of C++. SConstruct: Add Python interpreter include path & library. Define two new simple builders which copy & concatenate files, respectively, for use by the Python embedded zipfile code. src/SConscript: Encapsulate environment creation in a function. Add code to append Python zip archive to final executable. Eliminate references to obsolete files. src/python/SConscript: Rewrite to generate embedded zip archive of Python code (replacing old "embedded string" mechanism). src/python/m5/__init__.py: Move main arg-parsing loop here (out of C++ main()). src/python/m5/config.py: Minor fix (version incompatibility?). src/sim/main.cc: Invoke embedded Python interpreter to parse args and generate config.ini, replacing C++ arg parsing code. --HG-- extra : convert_revision : 72d21236b2bee139ff39ba4cf031a4a1f8560029
2006-05-30 19:11:34 +02:00
# List of constructed environments to pass back to SConstruct
envList = []
# Function to create a new build environment as clone of current
# environment 'env' with modified object suffix and optional stripped
# binary. Additional keyword arguments are appended to corresponding
# build environment vars.
def makeEnv(label, objsfx, strip = False, **kwargs):
newEnv = env.Copy(OBJSUFFIX=objsfx)
newEnv.Label = label
newEnv.Append(**kwargs)
exe = 'm5.' + label # final executable
bin = exe + '.bin' # executable w/o appended Python zip archive
newEnv.Program(bin, make_objs(sources, newEnv))
if strip:
stripped_bin = bin + '.stripped'
newEnv.Command(stripped_bin, bin, 'strip $SOURCE -o $TARGET')
bin = stripped_bin
targets = newEnv.Concat(exe, [bin, 'python/m5py.zip'])
newEnv.M5Binary = targets[0]
envList.append(newEnv)
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
# Debug binary
Link in Python interpreter. Use embedded zip archive to carry Python code instead of homegrown embedded string/file mechanism. Do argument parsing in Python instead of C++. SConstruct: Add Python interpreter include path & library. Define two new simple builders which copy & concatenate files, respectively, for use by the Python embedded zipfile code. src/SConscript: Encapsulate environment creation in a function. Add code to append Python zip archive to final executable. Eliminate references to obsolete files. src/python/SConscript: Rewrite to generate embedded zip archive of Python code (replacing old "embedded string" mechanism). src/python/m5/__init__.py: Move main arg-parsing loop here (out of C++ main()). src/python/m5/config.py: Minor fix (version incompatibility?). src/sim/main.cc: Invoke embedded Python interpreter to parse args and generate config.ini, replacing C++ arg parsing code. --HG-- extra : convert_revision : 72d21236b2bee139ff39ba4cf031a4a1f8560029
2006-05-30 19:11:34 +02:00
makeEnv('debug', '.do',
CCFLAGS = Split('-g3 -gdwarf-2 -O0'),
CPPDEFINES = 'DEBUG')
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
# Optimized binary
Link in Python interpreter. Use embedded zip archive to carry Python code instead of homegrown embedded string/file mechanism. Do argument parsing in Python instead of C++. SConstruct: Add Python interpreter include path & library. Define two new simple builders which copy & concatenate files, respectively, for use by the Python embedded zipfile code. src/SConscript: Encapsulate environment creation in a function. Add code to append Python zip archive to final executable. Eliminate references to obsolete files. src/python/SConscript: Rewrite to generate embedded zip archive of Python code (replacing old "embedded string" mechanism). src/python/m5/__init__.py: Move main arg-parsing loop here (out of C++ main()). src/python/m5/config.py: Minor fix (version incompatibility?). src/sim/main.cc: Invoke embedded Python interpreter to parse args and generate config.ini, replacing C++ arg parsing code. --HG-- extra : convert_revision : 72d21236b2bee139ff39ba4cf031a4a1f8560029
2006-05-30 19:11:34 +02:00
makeEnv('opt', '.o',
CCFLAGS = Split('-g -O3'))
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
# "Fast" binary
Link in Python interpreter. Use embedded zip archive to carry Python code instead of homegrown embedded string/file mechanism. Do argument parsing in Python instead of C++. SConstruct: Add Python interpreter include path & library. Define two new simple builders which copy & concatenate files, respectively, for use by the Python embedded zipfile code. src/SConscript: Encapsulate environment creation in a function. Add code to append Python zip archive to final executable. Eliminate references to obsolete files. src/python/SConscript: Rewrite to generate embedded zip archive of Python code (replacing old "embedded string" mechanism). src/python/m5/__init__.py: Move main arg-parsing loop here (out of C++ main()). src/python/m5/config.py: Minor fix (version incompatibility?). src/sim/main.cc: Invoke embedded Python interpreter to parse args and generate config.ini, replacing C++ arg parsing code. --HG-- extra : convert_revision : 72d21236b2bee139ff39ba4cf031a4a1f8560029
2006-05-30 19:11:34 +02:00
makeEnv('fast', '.fo', strip = True,
CCFLAGS = Split('-O3'),
CPPDEFINES = 'NDEBUG')
Initial SCons-based build system. See www.scons.org. 'cd build; scons' will build ALPHA/m5.debug. Use e.g. 'scons KERNEL/m5.opt' to build other binaries. Read the comments in build/SConstruct for more details. base/traceflags.py: Take basename of generated cc/hh files from command line instead of hardwiring them. Lets us call the script from a different directory and still have the files end up in the right place (e.g. "base/traceflags.py base/traceflags"). --HG-- extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-03 06:16:38 +02:00
# Profiled binary
Link in Python interpreter. Use embedded zip archive to carry Python code instead of homegrown embedded string/file mechanism. Do argument parsing in Python instead of C++. SConstruct: Add Python interpreter include path & library. Define two new simple builders which copy & concatenate files, respectively, for use by the Python embedded zipfile code. src/SConscript: Encapsulate environment creation in a function. Add code to append Python zip archive to final executable. Eliminate references to obsolete files. src/python/SConscript: Rewrite to generate embedded zip archive of Python code (replacing old "embedded string" mechanism). src/python/m5/__init__.py: Move main arg-parsing loop here (out of C++ main()). src/python/m5/config.py: Minor fix (version incompatibility?). src/sim/main.cc: Invoke embedded Python interpreter to parse args and generate config.ini, replacing C++ arg parsing code. --HG-- extra : convert_revision : 72d21236b2bee139ff39ba4cf031a4a1f8560029
2006-05-30 19:11:34 +02:00
makeEnv('prof', '.po',
CCFLAGS = Split('-O3 -g -pg'),
LINKFLAGS = '-pg')
Regression tests now run under scons! For example, 'scons ALPHA_SE/test/opt/quick' will build ALPHA_SE/m5.opt if necessary and run all the self-identified "quick" tests on it. Other possibilities: - Run just test1: scons ALPHA_SE/test/opt/test1 - Run all tests: scons ALPHA_SE/test/opt - Run all tests on debug build: scons ALPHA_SE/test/debug - Update test1 reference outputs in m5-test: scons update_ref=y ALPHA_SE/test/opt/test1 The proper tests will be selected based on the setting of FULL_SYSTEM, ALPHA_TLASER, etc. README: Update directions to use scons-based test invocation. SConscript: Return list of generated build environments to SConstruct so it can associate tests with each of them. Set 'M5Binary' attribute on each env to record name of generated binary to be tested. build/SConstruct: - Support invoking m5-test tests via scons. - Add new non-sticky option category, for 'update_ref'. - Move existing "sticky" option definitions out of build_dir loop. Someday we can generate help text from these. - Make 'CC' and 'CXX' sticky options; use environment vars as defaults if available. - Make config builder more scons-y. python/m5/__init__.py: Make AddToPath() correctly handle relative path arguments. Assumes that sys.path[0] has the directory where the current Python file lives; new m5execfile() function sets this up properly for exec'd files. --HG-- extra : convert_revision : 48896688592e210d8e63f96c34e57474853d0e66
2005-09-05 22:31:27 +02:00
Return('envList')
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