2015-07-16 02:53:50 +02:00
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# Copyright (c) 2015 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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2007-05-28 04:21:17 +02:00
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# Copyright (c) 2005-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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2006-09-05 02:14:07 +02:00
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from m5.SimObject import SimObject
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from m5.params import *
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from m5.proxy import *
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2015-12-10 11:35:15 +01:00
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from PciDevice import PciDevice
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2005-01-15 10:12:25 +01:00
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2007-08-16 22:49:02 +02:00
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class EtherObject(SimObject):
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type = 'EtherObject'
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2005-01-15 10:12:25 +01:00
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abstract = True
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2015-12-10 11:35:18 +01:00
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cxx_header = "dev/net/etherobject.hh"
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2005-01-15 10:12:25 +01:00
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2007-08-16 22:49:02 +02:00
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class EtherLink(EtherObject):
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2005-02-03 03:13:01 +01:00
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type = 'EtherLink'
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2015-12-10 11:35:18 +01:00
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cxx_header = "dev/net/etherlink.hh"
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2012-02-13 12:43:09 +01:00
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int0 = SlavePort("interface 0")
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int1 = SlavePort("interface 1")
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Make the notion of a global event tick independent of the actual
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 21:32:06 +02:00
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delay = Param.Latency('0us', "packet transmit delay")
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2005-11-02 20:44:42 +01:00
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delay_var = Param.Latency('0ns', "packet transmit delay variability")
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2005-06-02 17:19:01 +02:00
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speed = Param.NetworkBandwidth('1Gbps', "link speed")
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2005-01-15 10:12:25 +01:00
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dump = Param.EtherDump(NULL, "dump object")
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2016-01-07 23:33:47 +01:00
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class DistEtherLink(EtherObject):
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type = 'DistEtherLink'
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cxx_header = "dev/net/dist_etherlink.hh"
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2015-07-16 02:53:50 +02:00
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int0 = SlavePort("interface 0")
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delay = Param.Latency('0us', "packet transmit delay")
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delay_var = Param.Latency('0ns', "packet transmit delay variability")
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speed = Param.NetworkBandwidth('1Gbps', "link speed")
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dump = Param.EtherDump(NULL, "dump object")
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2016-01-07 23:33:47 +01:00
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dist_rank = Param.UInt32('0', "Rank of this gem5 process (dist run)")
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dist_size = Param.UInt32('1', "Number of gem5 processes (dist run)")
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sync_start = Param.Latency('5200000000000t', "first dist sync barrier")
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sync_repeat = Param.Latency('10us', "dist sync barrier repeat")
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2015-07-16 02:53:50 +02:00
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server_name = Param.String('localhost', "Message server name")
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server_port = Param.UInt32('2200', "Message server port")
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2016-01-07 23:33:47 +01:00
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is_switch = Param.Bool(False, "true if this a link in etherswitch")
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2016-10-27 04:48:40 +02:00
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dist_sync_on_pseudo_op = Param.Bool(False, "Start sync with pseudo_op")
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2016-01-07 23:33:47 +01:00
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num_nodes = Param.UInt32('2', "Number of simulate nodes")
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2015-07-16 02:53:50 +02:00
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2007-08-16 22:49:02 +02:00
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class EtherBus(EtherObject):
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2005-02-03 03:13:01 +01:00
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type = 'EtherBus'
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2015-12-10 11:35:18 +01:00
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cxx_header = "dev/net/etherbus.hh"
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Make the notion of a global event tick independent of the actual
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 21:32:06 +02:00
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loopback = Param.Bool(True, "send packet back to the sending interface")
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2005-01-15 10:12:25 +01:00
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dump = Param.EtherDump(NULL, "dump object")
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Make the notion of a global event tick independent of the actual
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 21:32:06 +02:00
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speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
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2005-01-15 10:12:25 +01:00
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2016-02-06 19:33:34 +01:00
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class EtherSwitch(EtherObject):
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type = 'EtherSwitch'
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cxx_header = "dev/net/etherswitch.hh"
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dump = Param.EtherDump(NULL, "dump object")
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fabric_speed = Param.NetworkBandwidth('10Gbps', "switch fabric speed in bits "
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"per second")
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interface = VectorMasterPort("Ethernet Interface")
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output_buffer_size = Param.MemorySize('1MB', "size of output port buffers")
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delay = Param.Latency('0us', "packet transmit delay")
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delay_var = Param.Latency('0ns', "packet transmit delay variability")
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time_to_live = Param.Latency('10ms', "time to live of MAC address maping")
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2007-08-16 22:49:02 +02:00
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class EtherTap(EtherObject):
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2005-02-03 03:13:01 +01:00
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type = 'EtherTap'
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2015-12-10 11:35:18 +01:00
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cxx_header = "dev/net/ethertap.hh"
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2005-01-15 10:12:25 +01:00
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bufsz = Param.Int(10000, "tap buffer size")
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dump = Param.EtherDump(NULL, "dump object")
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port = Param.UInt16(3500, "tap port")
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2005-05-29 07:14:50 +02:00
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class EtherDump(SimObject):
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2005-02-03 03:13:01 +01:00
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type = 'EtherDump'
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2015-12-10 11:35:18 +01:00
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cxx_header = "dev/net/etherdump.hh"
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2005-01-15 10:12:25 +01:00
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file = Param.String("dump file")
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2005-09-17 16:47:16 +02:00
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maxlen = Param.Int(96, "max portion of packet data to dump")
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2005-01-15 10:12:25 +01:00
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2007-08-16 22:49:02 +02:00
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class EtherDevice(PciDevice):
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type = 'EtherDevice'
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abstract = True
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2015-12-10 11:35:18 +01:00
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cxx_header = "dev/net/etherdevice.hh"
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2012-02-13 12:43:09 +01:00
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interface = MasterPort("Ethernet Interface")
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2007-08-16 22:49:02 +02:00
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class IGbE(EtherDevice):
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2008-12-05 19:58:22 +01:00
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# Base class for two IGbE adapters listed above
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2006-09-19 02:12:45 +02:00
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type = 'IGbE'
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2015-12-10 11:35:18 +01:00
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cxx_header = "dev/net/i8254xGBe.hh"
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2007-06-20 17:14:11 +02:00
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hardware_address = Param.EthernetAddr(NextEthernetAddr,
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"Ethernet Hardware Address")
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2007-03-27 00:40:18 +02:00
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rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO")
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tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO")
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2007-05-28 04:21:17 +02:00
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rx_desc_cache_size = Param.Int(64,
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"Number of enteries in the rx descriptor cache")
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tx_desc_cache_size = Param.Int(64,
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"Number of enteries in the rx descriptor cache")
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2006-09-19 02:12:45 +02:00
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VendorID = 0x8086
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SubsystemID = 0x1008
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SubsystemVendorID = 0x8086
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Status = 0x0000
|
|
|
|
|
SubClassCode = 0x00
|
|
|
|
|
ClassCode = 0x02
|
|
|
|
|
ProgIF = 0x00
|
|
|
|
|
BAR0 = 0x00000000
|
|
|
|
|
BAR1 = 0x00000000
|
|
|
|
|
BAR2 = 0x00000000
|
|
|
|
|
BAR3 = 0x00000000
|
|
|
|
|
BAR4 = 0x00000000
|
|
|
|
|
BAR5 = 0x00000000
|
|
|
|
|
MaximumLatency = 0x00
|
|
|
|
|
MinimumGrant = 0xff
|
|
|
|
|
InterruptLine = 0x1e
|
|
|
|
|
InterruptPin = 0x01
|
|
|
|
|
BAR0Size = '128kB'
|
2008-08-13 23:41:58 +02:00
|
|
|
wb_delay = Param.Latency('10ns', "delay before desc writeback occurs")
|
|
|
|
|
fetch_delay = Param.Latency('10ns', "delay before desc fetch occurs")
|
|
|
|
|
fetch_comp_delay = Param.Latency('10ns', "delay after desc fetch occurs")
|
|
|
|
|
wb_comp_delay = Param.Latency('10ns', "delay after desc wb occurs")
|
|
|
|
|
tx_read_delay = Param.Latency('0ns', "delay after tx dma read")
|
|
|
|
|
rx_write_delay = Param.Latency('0ns', "delay after rx dma read")
|
2009-01-06 16:36:55 +01:00
|
|
|
phy_pid = Param.UInt16("Phy PID that corresponds to device ID")
|
|
|
|
|
phy_epid = Param.UInt16("Phy EPID that corresponds to device ID")
|
2008-12-05 19:58:22 +01:00
|
|
|
|
|
|
|
|
class IGbE_e1000(IGbE):
|
|
|
|
|
# Older Intel 8254x based gigabit ethernet adapter
|
|
|
|
|
# Uses Intel e1000 driver
|
|
|
|
|
DeviceID = 0x1075
|
2009-01-06 16:36:55 +01:00
|
|
|
phy_pid = 0x02A8
|
|
|
|
|
phy_epid = 0x0380
|
2008-08-13 23:41:58 +02:00
|
|
|
|
2008-12-05 19:58:22 +01:00
|
|
|
class IGbE_igb(IGbE):
|
|
|
|
|
# Newer Intel 8257x based gigabit ethernet adapter
|
|
|
|
|
# Uses Intel igb driver and in theory supports packet splitting and LRO
|
|
|
|
|
DeviceID = 0x10C9
|
2009-01-06 16:36:55 +01:00
|
|
|
phy_pid = 0x0141
|
|
|
|
|
phy_epid = 0x0CC0
|
2006-09-19 02:12:45 +02:00
|
|
|
|
2007-08-16 22:49:02 +02:00
|
|
|
class EtherDevBase(EtherDevice):
|
2007-06-20 17:14:11 +02:00
|
|
|
type = 'EtherDevBase'
|
|
|
|
|
abstract = True
|
2015-12-10 11:35:18 +01:00
|
|
|
cxx_header = "dev/net/etherdevice.hh"
|
2012-11-02 17:32:01 +01:00
|
|
|
|
2005-01-15 10:12:25 +01:00
|
|
|
hardware_address = Param.EthernetAddr(NextEthernetAddr,
|
|
|
|
|
"Ethernet Hardware Address")
|
|
|
|
|
|
Make the notion of a global event tick independent of the actual
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 21:32:06 +02:00
|
|
|
dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
|
|
|
|
|
dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
|
|
|
|
|
dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
|
|
|
|
|
dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
|
2005-04-30 03:01:43 +02:00
|
|
|
|
Make the notion of a global event tick independent of the actual
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 21:32:06 +02:00
|
|
|
rx_delay = Param.Latency('1us', "Receive Delay")
|
|
|
|
|
tx_delay = Param.Latency('1us', "Transmit Delay")
|
2005-10-19 04:05:05 +02:00
|
|
|
rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo")
|
|
|
|
|
tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo")
|
2005-01-15 10:12:25 +01:00
|
|
|
|
2005-10-19 04:05:05 +02:00
|
|
|
rx_filter = Param.Bool(True, "Enable Receive Filter")
|
2005-11-25 19:33:36 +01:00
|
|
|
intr_delay = Param.Latency('10us', "Interrupt propagation delay")
|
|
|
|
|
rx_thread = Param.Bool(False, "dedicated kernel thread for transmit")
|
|
|
|
|
tx_thread = Param.Bool(False, "dedicated kernel threads for receive")
|
2006-03-03 20:17:48 +01:00
|
|
|
rss = Param.Bool(False, "Receive Side Scaling")
|
2005-01-15 10:12:25 +01:00
|
|
|
|
2007-08-16 22:49:05 +02:00
|
|
|
class NSGigE(EtherDevBase):
|
|
|
|
|
type = 'NSGigE'
|
2015-12-10 11:35:18 +01:00
|
|
|
cxx_header = "dev/net/ns_gige.hh"
|
2007-08-16 22:49:05 +02:00
|
|
|
|
|
|
|
|
dma_data_free = Param.Bool(False, "DMA of Data is free")
|
|
|
|
|
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
|
|
|
|
|
dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
|
|
|
|
|
|
2006-07-12 23:16:00 +02:00
|
|
|
VendorID = 0x100B
|
|
|
|
|
DeviceID = 0x0022
|
|
|
|
|
Status = 0x0290
|
|
|
|
|
SubClassCode = 0x00
|
|
|
|
|
ClassCode = 0x02
|
|
|
|
|
ProgIF = 0x00
|
|
|
|
|
BAR0 = 0x00000001
|
|
|
|
|
BAR1 = 0x00000000
|
|
|
|
|
BAR2 = 0x00000000
|
|
|
|
|
BAR3 = 0x00000000
|
|
|
|
|
BAR4 = 0x00000000
|
|
|
|
|
BAR5 = 0x00000000
|
|
|
|
|
MaximumLatency = 0x34
|
|
|
|
|
MinimumGrant = 0xb0
|
|
|
|
|
InterruptLine = 0x1e
|
|
|
|
|
InterruptPin = 0x01
|
|
|
|
|
BAR0Size = '256B'
|
|
|
|
|
BAR1Size = '4kB'
|
|
|
|
|
|
2005-04-25 03:32:32 +02:00
|
|
|
|
2005-10-19 04:05:05 +02:00
|
|
|
|
2007-08-16 22:49:05 +02:00
|
|
|
class Sinic(EtherDevBase):
|
|
|
|
|
type = 'Sinic'
|
2008-10-10 07:19:39 +02:00
|
|
|
cxx_class = 'Sinic::Device'
|
2015-12-10 11:35:18 +01:00
|
|
|
cxx_header = "dev/net/sinic.hh"
|
2006-07-12 23:16:00 +02:00
|
|
|
|
2007-08-16 22:49:05 +02:00
|
|
|
rx_max_copy = Param.MemorySize('1514B', "rx max copy")
|
|
|
|
|
tx_max_copy = Param.MemorySize('16kB', "tx max copy")
|
|
|
|
|
rx_max_intr = Param.UInt32(10, "max rx packets per interrupt")
|
|
|
|
|
rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold")
|
|
|
|
|
rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold")
|
|
|
|
|
tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold")
|
|
|
|
|
tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold")
|
|
|
|
|
virtual_count = Param.UInt32(1, "Virtualized SINIC")
|
2008-10-09 13:58:23 +02:00
|
|
|
zero_copy_size = Param.UInt32(64, "Bytes to copy if below threshold")
|
|
|
|
|
zero_copy_threshold = Param.UInt32(256,
|
|
|
|
|
"Only zero copy above this threshold")
|
2007-08-16 22:49:05 +02:00
|
|
|
zero_copy = Param.Bool(False, "Zero copy receive")
|
|
|
|
|
delay_copy = Param.Bool(False, "Delayed copy transmit")
|
|
|
|
|
virtual_addr = Param.Bool(False, "Virtual addressing")
|
2005-01-15 10:12:25 +01:00
|
|
|
|
2006-07-12 23:16:00 +02:00
|
|
|
VendorID = 0x1291
|
|
|
|
|
DeviceID = 0x1293
|
|
|
|
|
Status = 0x0290
|
|
|
|
|
SubClassCode = 0x00
|
|
|
|
|
ClassCode = 0x02
|
|
|
|
|
ProgIF = 0x00
|
|
|
|
|
BAR0 = 0x00000000
|
|
|
|
|
BAR1 = 0x00000000
|
|
|
|
|
BAR2 = 0x00000000
|
|
|
|
|
BAR3 = 0x00000000
|
|
|
|
|
BAR4 = 0x00000000
|
|
|
|
|
BAR5 = 0x00000000
|
|
|
|
|
MaximumLatency = 0x34
|
|
|
|
|
MinimumGrant = 0xb0
|
|
|
|
|
InterruptLine = 0x1e
|
|
|
|
|
InterruptPin = 0x01
|
|
|
|
|
BAR0Size = '64kB'
|
|
|
|
|
|
|
|
|
|
|
