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Ethernet devices have an RSS option to tell the driver to

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use Receive side scaling

dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
dev/sinic.cc:
dev/sinic.hh:
dev/sinicreg.hh:
    add support for setting the RSS flag to notify the driver
    to use RSS

--HG--
extra : convert_revision : 5f0c11668ae976634b3bf0caad669a9464a4c041
This commit is contained in:
Nathan Binkert 2006-03-03 14:17:48 -05:00
parent 0fed64a6a4
commit 7546fabe68
7 changed files with 17 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
dev/ns_gige.cc
View file

@ -767,6 +767,8 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
reg |= M5REG_RX_THREAD;
if (params()->tx_thread)
reg |= M5REG_TX_THREAD;
if (params()->rss)
reg |= M5REG_RSS;
break;
default:
@ -3009,6 +3011,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
Param<string> hardware_address;
Param<bool> rx_thread;
Param<bool> tx_thread;
Param<bool> rss;
END_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
@ -3048,7 +3051,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
INIT_PARAM(rx_filter, "Enable Receive Filter"),
INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
INIT_PARAM(rx_thread, ""),
INIT_PARAM(tx_thread, "")
INIT_PARAM(tx_thread, ""),
INIT_PARAM(rss, "")
END_INIT_SIM_OBJECT_PARAMS(NSGigE)
@ -3093,6 +3097,7 @@ CREATE_SIM_OBJECT(NSGigE)
params->eaddr = hardware_address;
params->rx_thread = rx_thread;
params->tx_thread = tx_thread;
params->rss = rss;
return new NSGigE(params);
}

1
dev/ns_gige.hh
View file

@ -385,6 +385,7 @@ class NSGigE : public PciDev
uint32_t rx_fifo_size;
bool rx_thread;
bool tx_thread;
bool rss;
bool dma_no_allocate;
};

1
dev/ns_gige_reg.h
View file

@ -306,6 +306,7 @@
/* M5 control register */
#define M5REG_RESERVED 0xfffffffc
#define M5REG_RSS 0x00000004
#define M5REG_RX_THREAD 0x00000002
#define M5REG_TX_THREAD 0x00000001

7
dev/sinic.cc
View file

@ -761,6 +761,8 @@ Device::reset()
regs.Config |= Config_RxThread;
if (params()->tx_thread)
regs.Config |= Config_TxThread;
if (params()->rss)
regs.Config |= Config_RSS;
regs.IntrMask = Intr_Soft | Intr_RxHigh | Intr_RxPacket | Intr_TxLow;
regs.RxMaxCopy = params()->rx_max_copy;
regs.TxMaxCopy = params()->tx_max_copy;
@ -1624,6 +1626,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device)
Param<string> hardware_address;
Param<bool> rx_thread;
Param<bool> tx_thread;
Param<bool> rss;
END_DECLARE_SIM_OBJECT_PARAMS(Device)
@ -1666,7 +1669,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Device)
INIT_PARAM(rx_filter, "Enable Receive Filter"),
INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
INIT_PARAM(rx_thread, ""),
INIT_PARAM(tx_thread, "")
INIT_PARAM(tx_thread, ""),
INIT_PARAM(rss, "")
END_INIT_SIM_OBJECT_PARAMS(Device)
@ -1714,6 +1718,7 @@ CREATE_SIM_OBJECT(Device)
params->eaddr = hardware_address;
params->rx_thread = rx_thread;
params->tx_thread = tx_thread;
params->rss = rss;
return new Device(params);
}

1
dev/sinic.hh
View file

@ -355,6 +355,7 @@ class Device : public Base
bool dma_no_allocate;
bool rx_thread;
bool tx_thread;
bool rss;
};
protected:

1
dev/sinicreg.hh
View file

@ -81,6 +81,7 @@ __SINIC_REG32(HwAddr, 0x60); // 64: mac address
__SINIC_REG32(Size, 0x68); // register addres space size
// Config register bits
__SINIC_VAL32(Config_RSS, 10, 1); // enable receive side scaling
__SINIC_VAL32(Config_RxThread, 9, 1); // enable receive threads
__SINIC_VAL32(Config_TxThread, 8, 1); // enable transmit thread
__SINIC_VAL32(Config_Filter, 7, 1); // enable receive filter

1
python/m5/objects/Ethernet.py
View file

@ -86,6 +86,7 @@ class EtherDevBase(PciDevice):
intr_delay = Param.Latency('10us', "Interrupt propagation delay")
rx_thread = Param.Bool(False, "dedicated kernel thread for transmit")
tx_thread = Param.Bool(False, "dedicated kernel threads for receive")
rss = Param.Bool(False, "Receive Side Scaling")
class NSGigE(EtherDevBase):
type = 'NSGigE'