gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.111167                       # Number of seconds simulated
sim_ticks                                51111167268500                       # Number of ticks simulated
final_tick                               51111167268500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 933162                       # Simulator instruction rate (inst/s)
host_op_rate                                  1096667                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            48559439795                       # Simulator tick rate (ticks/s)
host_mem_usage                                 681072                       # Number of bytes of host memory used
host_seconds                                  1052.55                       # Real time elapsed on the host
sim_insts                                   982198023                       # Number of instructions simulated
sim_ops                                    1154295627                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker       206336                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       188224                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          3278004                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         38031624                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       207616                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       185152                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          2205440                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         36882368                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        436800                       # Number of bytes read from this memory
system.physmem.bytes_read::total             81621564                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      3278004                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      2205440                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         5483444                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks    103278592                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total         103299172                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         3224                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         2941                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             91626                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            594257                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         3244                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         2893                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             34460                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            576287                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6825                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1315757                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1613728                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1616301                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          4037                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          3683                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               64135                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              744096                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          4062                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          3623                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               43150                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              721611                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8546                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1596942                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          64135                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          43150                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             107285                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2020666                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                403                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2021069                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2020666                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         4037                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         3683                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              64135                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             744499                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         4062                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         3623                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              43150                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             721611                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8546                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3618010                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                3                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                   145515                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               145515                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walkWaitTime::samples       145515                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0         145515    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       145515                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples     22846000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0       22846000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total     22846000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K       108307     85.67%     85.67% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        18122     14.33%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       126429                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       145515                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       145515                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       126429                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       126429                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       271944                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    91812952                       # DTB read hits
system.cpu0.dtb.read_misses                    108269                       # DTB read misses
system.cpu0.dtb.write_hits                   84016904                       # DTB write hits
system.cpu0.dtb.write_misses                    37246                       # DTB write misses
system.cpu0.dtb.flush_tlb                       51122                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              25430                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                    574                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   56668                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  4782                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    10953                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                91921221                       # DTB read accesses
system.cpu0.dtb.write_accesses               84054150                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        175829856                       # DTB hits
system.cpu0.dtb.misses                         145515                       # DTB misses
system.cpu0.dtb.accesses                    175975371                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                    70816                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                70816                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walkWaitTime::samples        70816                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          70816    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        70816                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples     22844500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0       22844500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total     22844500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        62041     96.03%     96.03% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M         2564      3.97%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        64605                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        70816                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        70816                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        64605                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        64605                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       135421                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   492374883                       # ITB inst hits
system.cpu0.itb.inst_misses                     70816                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                       51122                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              25430                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                    574                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   40442                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               492445699                       # ITB inst accesses
system.cpu0.itb.hits                        492374883                       # DTB hits
system.cpu0.itb.misses                          70816                       # DTB misses
system.cpu0.itb.accesses                    492445699                       # DTB accesses
system.cpu0.numPwrStateTransitions              16972                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples         8486                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    5850237301.708461                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   113494821184.972778                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         3706     43.67%     43.67% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10         4716     55.57%     99.25% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11            1      0.01%     99.26% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11           45      0.53%     99.79% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11            5      0.06%     99.85% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11            1      0.01%     99.86% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::overflows           12      0.14%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 3977575161560                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total           8486                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON   1466053526202                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 49645113742298                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                     98039867564                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   16775                       # number of quiesce instructions executed
system.cpu0.committedInsts                  492156218                       # Number of instructions committed
system.cpu0.committedOps                    578106768                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            529626923                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                450865                       # Number of float alu accesses
system.cpu0.num_func_calls                   28493046                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     76041586                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   529626923                       # number of integer instructions
system.cpu0.num_fp_insts                       450865                       # number of float instructions
system.cpu0.num_int_register_reads          782885196                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         420741799                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              732662                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             369512                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           132705210                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          132383544                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    175953589                       # number of memory refs
system.cpu0.num_load_insts                   91907608                       # Number of load instructions
system.cpu0.num_store_insts                  84045981                       # Number of store instructions
system.cpu0.num_idle_cycles              96932341935.251450                       # Number of idle cycles
system.cpu0.num_busy_cycles              1107525628.748547                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.011297                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.988703                       # Percentage of idle cycles
system.cpu0.Branches                        110098917                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                401201785     69.36%     69.36% # Class of executed instruction
system.cpu0.op_class::IntMult                 1174308      0.20%     69.56% # Class of executed instruction
system.cpu0.op_class::IntDiv                    49945      0.01%     69.57% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.57% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.57% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.57% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.57% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.57% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.57% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.57% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.57% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.57% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.57% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.57% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.57% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.57% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.57% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.57% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.57% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             53536      0.01%     69.58% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.58% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.58% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.58% # Class of executed instruction
system.cpu0.op_class::MemRead                91907608     15.89%     85.47% # Class of executed instruction
system.cpu0.op_class::MemWrite               84045981     14.53%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 578433163                       # Class of executed instruction
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements         11606055                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.999719                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          339854312                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs         11606567                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            29.281209                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         33050500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   263.642169                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   248.357550                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.514926                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.485073                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          199                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          297                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses       1417450148                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses      1417450148                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data     85600060                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     85509890                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total      171109950                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     79551757                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data     79538240                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total     159089997                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       209327                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       214988                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       424315                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       144230                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data       192053                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       336283                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      2149020                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      2154529                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      4303549                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2274909                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data      2280735                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      4555644                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    165296047                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data    165240183                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       330536230                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    165505374                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data    165455171                       # number of overall hits
system.cpu0.dcache.overall_hits::total      330960545                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      3016323                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data      2986728                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      6003051                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1286923                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      1264627                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      2551550                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       788168                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data       797714                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total      1585882                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       761557                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data       485215                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total      1246772                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       126793                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       127105                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       253898                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data            1                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      5064803                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      4736570                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       9801373                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      5852971                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      5534284                       # number of overall misses
system.cpu0.dcache.overall_misses::total     11387255                       # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data     88616383                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     88496618                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total    177113001                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     80838680                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data     80802867                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total    161641547                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       997495                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data      1012702                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total      2010197                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       905787                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       677268                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1583055                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2275813                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2281634                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      4557447                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2274909                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      2280736                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      4555645                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    170360850                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data    169976753                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    340337603                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    171358345                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data    170989455                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    342347800                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.034038                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033750                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.033894                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015920                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.015651                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.015785                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.790147                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.787709                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.788919                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.840768                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.716430                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.787573                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.055713                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.055708                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.055711                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000000                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029730                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.027866                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.028799                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.034156                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.032366                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.033262                       # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks      8918956                       # number of writebacks
system.cpu0.dcache.writebacks::total          8918956                       # number of writebacks
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements         14265255                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.984599                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          968523793                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs         14265767                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            67.891463                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       6061932500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   268.597080                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   243.387519                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.524604                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.475366                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999970                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          184                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          239                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           89                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        997055337                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       997055337                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst    485300804                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst    483222989                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      968523793                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    485300804                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst    483222989                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       968523793                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    485300804                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst    483222989                       # number of overall hits
system.cpu0.icache.overall_hits::total      968523793                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      7138684                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      7127088                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total     14265772                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      7138684                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      7127088                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total      14265772                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      7138684                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      7127088                       # number of overall misses
system.cpu0.icache.overall_misses::total     14265772                       # number of overall misses
system.cpu0.icache.ReadReq_accesses::cpu0.inst    492439488                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst    490350077                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    982789565                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    492439488                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst    490350077                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    982789565                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    492439488                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst    490350077                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    982789565                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014497                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014535                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.014516                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014497                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.014535                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.014516                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014497                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.014535                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.014516                       # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks     14265255                       # number of writebacks
system.cpu0.icache.writebacks::total         14265255                       # number of writebacks
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                   143141                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               143141                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walkWaitTime::samples       143141                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0         143141    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       143141                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walksPending::samples   1000001000                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1000001000    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   1000001000                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K       106696     85.47%     85.47% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        18135     14.53%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total       124831                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       143141                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       143141                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       124831                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       124831                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       267972                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    91711544                       # DTB read hits
system.cpu1.dtb.read_misses                    106091                       # DTB read misses
system.cpu1.dtb.write_hits                   83754683                       # DTB write hits
system.cpu1.dtb.write_misses                    37050                       # DTB write misses
system.cpu1.dtb.flush_tlb                       51111                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              24341                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                    565                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   56242                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  4763                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    10698                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                91817635                       # DTB read accesses
system.cpu1.dtb.write_accesses               83791733                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        175466227                       # DTB hits
system.cpu1.dtb.misses                         143141                       # DTB misses
system.cpu1.dtb.accesses                    175609368                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                    69344                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                69344                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walkWaitTime::samples        69344                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          69344    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        69344                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        60893     96.02%     96.02% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M         2524      3.98%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        63417                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        69344                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        69344                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        63417                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        63417                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       132761                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   490286660                       # ITB inst hits
system.cpu1.itb.inst_misses                     69344                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                       51111                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              24341                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                    565                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   40468                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               490356004                       # ITB inst accesses
system.cpu1.itb.hits                        490286660                       # DTB hits
system.cpu1.itb.misses                          69344                       # DTB misses
system.cpu1.itb.accesses                    490356004                       # DTB accesses
system.cpu1.numPwrStateTransitions              16542                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         8271                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    6033690194.397533                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   129465330065.337860                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows         3733     45.13%     45.13% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10         4474     54.09%     99.23% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11            2      0.02%     99.25% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            4      0.05%     99.30% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11           44      0.53%     99.83% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            1      0.01%     99.84% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11            3      0.04%     99.88% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::overflows           10      0.12%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 5966367222968                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           8271                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON   1206515670638                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 49904651597862                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                     97462078889                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu1.committedInsts                  490041805                       # Number of instructions committed
system.cpu1.committedOps                    576188859                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            528250212                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                430484                       # Number of float alu accesses
system.cpu1.num_func_calls                   28340797                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     75581054                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   528250212                       # number of integer instructions
system.cpu1.num_fp_insts                       430484                       # number of float instructions
system.cpu1.num_int_register_reads          777868472                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         419771352                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              687105                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             379048                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           131312247                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes          131056135                       # number of times the CC registers were written
system.cpu1.num_mem_refs                    175584466                       # number of memory refs
system.cpu1.num_load_insts                   91803674                       # Number of load instructions
system.cpu1.num_store_insts                  83780792                       # Number of store instructions
system.cpu1.num_idle_cycles              96359431608.339264                       # Number of idle cycles
system.cpu1.num_busy_cycles              1102647280.660740                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.011314                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.988686                       # Percentage of idle cycles
system.cpu1.Branches                        109433272                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                399627658     69.32%     69.32% # Class of executed instruction
system.cpu1.op_class::IntMult                 1180080      0.20%     69.52% # Class of executed instruction
system.cpu1.op_class::IntDiv                    50598      0.01%     69.53% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.53% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.53% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.53% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.53% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.53% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.53% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.53% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.53% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.53% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.53% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.53% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.53% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.53% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.53% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.53% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.53% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.53% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.53% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.53% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.53% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.53% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.53% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             54286      0.01%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::MemRead                91803674     15.92%     85.47% # Class of executed instruction
system.cpu1.op_class::MemWrite               83780792     14.53%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 576497131                       # Class of executed instruction
system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                40242                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40242                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136515                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136515                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47598                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122480                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230954                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       230954                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353514                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47618                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155610                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7491944                       # Cumulative packet size per connected master and slave (bytes)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements               115459                       # number of replacements
system.iocache.tags.tagsinuse               10.407111                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115475                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13082113307009                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.554597                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.852514                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.222162                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.428282                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.650444                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039650                       # Number of tag accesses
system.iocache.tags.data_accesses             1039650                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8813                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8850                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide       115477                       # number of demand (read+write) misses
system.iocache.demand_misses::total            115517                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide       115477                       # number of overall misses
system.iocache.overall_misses::total           115517                       # number of overall misses
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8813                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8850                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide       115477                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total          115517                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide       115477                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total         115517                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks          106631                       # number of writebacks
system.iocache.writebacks::total               106631                       # number of writebacks
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                  1725813                       # number of replacements
system.l2c.tags.tagsinuse                65403.901917                       # Cycle average of tags in use
system.l2c.tags.total_refs                   49468109                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1788889                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    27.652978                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                395496000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks    9615.108088                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   224.707200                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   268.802991                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3426.785629                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    22887.229719                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   209.300949                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   228.038258                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2648.603044                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data    25895.326039                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.146715                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.003429                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.004102                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.052289                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.349231                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.003194                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.003480                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.040414                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.395131                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.997984                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023          371                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        62705                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          371                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          329                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         1444                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5122                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        55700                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.005661                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.956802                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                423190040                       # Number of tag accesses
system.l2c.tags.data_accesses               423190040                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.l2c.ReadReq_hits::cpu0.dtb.walker       265559                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker       135827                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker       262154                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker       132135                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 795675                       # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks      8918956                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         8918956                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks     14263678                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total        14263678                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data           15680                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data           15013                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               30693                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           852174                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           837196                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total              1689370                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst       7090159                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst       7092615                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total          14182774                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data      3753733                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data      3744979                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          7498712                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       340283                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       354274                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           694557                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker        265559                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker        135827                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst             7090159                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data             4605907                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker        262154                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker        132135                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst             7092615                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data             4582175                       # number of demand (read+write) hits
system.l2c.demand_hits::total                24166531                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker       265559                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker       135827                       # number of overall hits
system.l2c.overall_hits::cpu0.inst            7090159                       # number of overall hits
system.l2c.overall_hits::cpu0.data            4605907                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker       262154                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker       132135                       # number of overall hits
system.l2c.overall_hits::cpu1.inst            7092615                       # number of overall hits
system.l2c.overall_hits::cpu1.data            4582175                       # number of overall hits
system.l2c.overall_hits::total               24166531                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         3224                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         2941                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker         3244                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker         2893                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                12302                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1907                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1973                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              3880                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data            1                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               1                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         417162                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         410445                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             827607                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        48525                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst        34473                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           82998                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       177551                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       166568                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         344119                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       421274                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data       130941                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         552215                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         3224                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         2941                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             48525                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            594713                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         3244                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         2893                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             34473                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            577013                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1267026                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         3224                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         2941                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            48525                       # number of overall misses
system.l2c.overall_misses::cpu0.data           594713                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         3244                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         2893                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            34473                       # number of overall misses
system.l2c.overall_misses::cpu1.data           577013                       # number of overall misses
system.l2c.overall_misses::total              1267026                       # number of overall misses
system.l2c.ReadReq_accesses::cpu0.dtb.walker       268783                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker       138768                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker       265398                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker       135028                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             807977                       # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks      8918956                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      8918956                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks     14263678                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total     14263678                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        17587                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        16986                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           34573                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data      1269336                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data      1247641                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          2516977                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst      7138684                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst      7127088                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total      14265772                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data      3931284                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data      3911547                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      7842831                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       761557                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       485215                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total      1246772                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker       268783                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker       138768                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst         7138684                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         5200620                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker       265398                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker       135028                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst         7127088                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         5159188                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total            25433557                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker       268783                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker       138768                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst        7138684                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        5200620                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker       265398                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker       135028                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst        7127088                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        5159188                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total           25433557                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.011995                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.021194                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.012223                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.021425                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.015226                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.108432                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.116154                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.112226                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.328646                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.328977                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.328810                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006797                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.004837                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.005818                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.045164                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.042584                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.043877                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.553175                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.269862                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.442916                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.011995                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.021194                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.006797                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.114354                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.012223                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.021425                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.004837                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.111842                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.049817                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.011995                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.021194                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.006797                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.114354                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.012223                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.021425                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.004837                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.111842                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.049817                       # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks             1507097                       # number of writebacks
system.l2c.writebacks::total                  1507097                       # number of writebacks
system.membus.snoop_filter.tot_requests       3778676                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests      1875347                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests         2861                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               76679                       # Transaction distribution
system.membus.trans_dist::ReadResp             524948                       # Transaction distribution
system.membus.trans_dist::WriteReq              33606                       # Transaction distribution
system.membus.trans_dist::WriteResp             33606                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1613728                       # Transaction distribution
system.membus.trans_dist::CleanEvict           226309                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4447                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4448                       # Transaction distribution
system.membus.trans_dist::ReadExReq            827050                       # Transaction distribution
system.membus.trans_dist::ReadExResp           827050                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        448269                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        658872                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       658872                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122480                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6654                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5462200                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      5591392                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       346493                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       346493                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5937885                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155610                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13308                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    177701344                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    177870394                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7390784                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7390784                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               185261178                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples           3888961                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.009406                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.096529                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 3852380     99.06%     99.06% # Request fanout histogram
system.membus.snoop_fanout::1                   36581      0.94%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3888961                       # Request fanout histogram
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests     52388021                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests     26515676                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests         1744                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops           2694                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops         2694                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq            1320370                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp          23428973                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             33606                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            33606                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      8918956                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean     14265255                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2687099                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           34573                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             1                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          34574                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          2516977                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         2516977                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq      14265772                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      7842831                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq      1246772                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp      1246772                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     42883049                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     35022683                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       830232                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1657150                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              80393114                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1826158228                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1234030566                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3320928                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6628600                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total             3070138322                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         1762508                       # Total snoops (count)
system.toL2Bus.snoopTraffic                  96494720                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples         54893925                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.011221                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.105334                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0               54277951     98.88%     98.88% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 615974      1.12%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           54893925                       # Request fanout histogram

---------- End Simulation Statistics   ----------