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gem5/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt

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Add short memtest run to quick regressions. Caveats: - Even though memtest is ISA-independent, it will only run for the Alpha builds, since there's no way to specify ISA-independent reference files and I didn't want to commit 3 copies since I'm not sure we want to run it for all the different ISAs anyway. - Reference outputs were generated on my laptop, so performance numbers will be low compared to zizzer. --HG-- extra : convert_revision : 210fe4abecc19fbab0b15402c6cb4863650bab66
2007-02-07 06:16:33 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
sim_seconds 0.000667 # Number of seconds simulated
sim_ticks 666669000 # Number of ticks simulated
final_tick 666669000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
host_tick_rate 89799840 # Simulator tick rate (ticks/s)
host_mem_usage 343700 # Number of bytes of host memory used
host_seconds 7.42 # Real time elapsed on the host
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.bytes_read::cpu0 77587 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1 78424 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2 78448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3 79552 # Number of bytes read from this memory
system.physmem.bytes_read::cpu4 79510 # Number of bytes read from this memory
system.physmem.bytes_read::cpu5 77345 # Number of bytes read from this memory
system.physmem.bytes_read::cpu6 78315 # Number of bytes read from this memory
system.physmem.bytes_read::cpu7 77919 # Number of bytes read from this memory
system.physmem.bytes_read::total 627100 # Number of bytes read from this memory
system.physmem.bytes_written::writebacks 389952 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0 5508 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1 5505 # Number of bytes written to this memory
system.physmem.bytes_written::cpu2 5430 # Number of bytes written to this memory
system.physmem.bytes_written::cpu3 5540 # Number of bytes written to this memory
system.physmem.bytes_written::cpu4 5369 # Number of bytes written to this memory
system.physmem.bytes_written::cpu5 5487 # Number of bytes written to this memory
system.physmem.bytes_written::cpu6 5602 # Number of bytes written to this memory
system.physmem.bytes_written::cpu7 5488 # Number of bytes written to this memory
system.physmem.bytes_written::total 433881 # Number of bytes written to this memory
system.physmem.num_reads::cpu0 10807 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1 10825 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2 10786 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3 10945 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu4 10966 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu5 10880 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu6 10905 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu7 10824 # Number of read requests responded to by this memory
system.physmem.num_reads::total 86938 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 6093 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0 5508 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1 5505 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2 5430 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu3 5540 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu4 5369 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu5 5487 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu6 5602 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu7 5488 # Number of write requests responded to by this memory
system.physmem.num_writes::total 50022 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0 116380093 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1 117635588 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2 117671588 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3 119327582 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu4 119264583 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu5 116017094 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu6 117472089 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu7 116878091 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 940646708 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 584925953 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0 8261971 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1 8257471 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2 8144971 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu3 8309971 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu4 8053472 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu5 8230471 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu6 8402971 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu7 8231971 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 650819222 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 584925953 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0 124642064 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1 125893059 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2 125816560 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3 127637553 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu4 127318054 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu5 124247565 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu6 125875059 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu7 125110062 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1591465930 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 1591365430 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 83865 # Transaction distribution
system.membus.trans_dist::ReadResp 83861 # Transaction distribution
system.membus.trans_dist::WriteReq 43929 # Transaction distribution
system.membus.trans_dist::WriteResp 43926 # Transaction distribution
system.membus.trans_dist::Writeback 6093 # Transaction distribution
system.membus.trans_dist::UpgradeReq 58314 # Transaction distribution
system.membus.trans_dist::UpgradeResp 47560 # Transaction distribution
system.membus.trans_dist::ReadExReq 50259 # Transaction distribution
system.membus.trans_dist::ReadExResp 3073 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 420880 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 420880 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 1060914 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 1060914 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 1060914 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.membus.reqLayer0.occupancy 288472152 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 43.3 # Layer utilization (%)
system.membus.respLayer0.occupancy 310892000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 46.6 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.l2c.tags.replacements 13077 # number of replacements
system.l2c.tags.tagsinuse 783.417350 # Cycle average of tags in use
system.l2c.tags.total_refs 150095 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 13853 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 10.834837 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.l2c.tags.occ_blocks::writebacks 730.528683 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0 6.960741 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1 6.211335 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2 6.682597 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3 6.340197 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu4 6.666463 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu5 5.896963 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu6 7.159072 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu7 6.971301 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.713407 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0 0.006798 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1 0.006066 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2 0.006526 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3 0.006192 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu4 0.006510 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu5 0.005759 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu6 0.006991 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu7 0.006808 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.765056 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 776 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 556 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 1967301 # Number of tag accesses
system.l2c.tags.data_accesses 1967301 # Number of data accesses
system.l2c.ReadReq_hits::cpu0 10709 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1 10684 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2 10837 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3 10726 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu4 10661 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu5 10672 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu6 10767 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu7 10772 # number of ReadReq hits
system.l2c.ReadReq_hits::total 85828 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 76131 # number of Writeback hits
system.l2c.Writeback_hits::total 76131 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0 391 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1 342 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2 290 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3 349 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu4 346 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu5 350 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu6 327 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu7 361 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 2756 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0 1947 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1 1955 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2 1901 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3 1956 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu4 1993 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu5 1935 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu6 1923 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu7 1905 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 15515 # number of ReadExReq hits
system.l2c.demand_hits::cpu0 12656 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1 12639 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2 12738 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3 12682 # number of demand (read+write) hits
system.l2c.demand_hits::cpu4 12654 # number of demand (read+write) hits
system.l2c.demand_hits::cpu5 12607 # number of demand (read+write) hits
system.l2c.demand_hits::cpu6 12690 # number of demand (read+write) hits
system.l2c.demand_hits::cpu7 12677 # number of demand (read+write) hits
system.l2c.demand_hits::total 101343 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0 12656 # number of overall hits
system.l2c.overall_hits::cpu1 12639 # number of overall hits
system.l2c.overall_hits::cpu2 12738 # number of overall hits
system.l2c.overall_hits::cpu3 12682 # number of overall hits
system.l2c.overall_hits::cpu4 12654 # number of overall hits
system.l2c.overall_hits::cpu5 12607 # number of overall hits
system.l2c.overall_hits::cpu6 12690 # number of overall hits
system.l2c.overall_hits::cpu7 12677 # number of overall hits
system.l2c.overall_hits::total 101343 # number of overall hits
system.l2c.ReadReq_misses::cpu0 711 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1 677 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2 686 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3 704 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu4 731 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu5 661 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu6 687 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu7 695 # number of ReadReq misses
system.l2c.ReadReq_misses::total 5552 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0 1900 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1 1921 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2 1938 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3 1929 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu4 1958 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu5 1980 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu6 1936 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu7 1909 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 15471 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0 4356 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1 4370 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2 4398 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3 4380 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu4 4410 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu5 4536 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu6 4403 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu7 4341 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 35194 # number of ReadExReq misses
system.l2c.demand_misses::cpu0 5067 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1 5047 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2 5084 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3 5084 # number of demand (read+write) misses
system.l2c.demand_misses::cpu4 5141 # number of demand (read+write) misses
system.l2c.demand_misses::cpu5 5197 # number of demand (read+write) misses
system.l2c.demand_misses::cpu6 5090 # number of demand (read+write) misses
system.l2c.demand_misses::cpu7 5036 # number of demand (read+write) misses
system.l2c.demand_misses::total 40746 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0 5067 # number of overall misses
system.l2c.overall_misses::cpu1 5047 # number of overall misses
system.l2c.overall_misses::cpu2 5084 # number of overall misses
system.l2c.overall_misses::cpu3 5084 # number of overall misses
system.l2c.overall_misses::cpu4 5141 # number of overall misses
system.l2c.overall_misses::cpu5 5197 # number of overall misses
system.l2c.overall_misses::cpu6 5090 # number of overall misses
system.l2c.overall_misses::cpu7 5036 # number of overall misses
system.l2c.overall_misses::total 40746 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0 44350412 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1 42088920 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2 42842422 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3 43387924 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu4 44233435 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu5 40432424 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu6 42285920 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu7 43294412 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 342915869 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0 53982500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1 57751996 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2 56478495 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3 54930999 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu4 55403495 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu5 57236497 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu6 57195998 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu7 53900999 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 446880979 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0 234747448 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1 235575440 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2 236263447 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3 235909448 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu4 237652448 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu5 244314939 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu6 237512440 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu7 233621439 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 1895597049 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0 279097860 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1 277664360 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2 279105869 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3 279297372 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu4 281885883 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu5 284747363 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu6 279798360 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu7 276915851 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 2238512918 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0 279097860 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1 277664360 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2 279105869 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3 279297372 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu4 281885883 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu5 284747363 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu6 279798360 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu7 276915851 # number of overall miss cycles
system.l2c.overall_miss_latency::total 2238512918 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0 11420 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1 11361 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2 11523 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3 11430 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu4 11392 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu5 11333 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu6 11454 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu7 11467 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 91380 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 76131 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 76131 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0 2291 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1 2263 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2 2228 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3 2278 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu4 2304 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu5 2330 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu6 2263 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu7 2270 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 18227 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0 6303 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1 6325 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2 6299 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3 6336 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu4 6403 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu5 6471 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu6 6326 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu7 6246 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 50709 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0 17723 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1 17686 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2 17822 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3 17766 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu4 17795 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu5 17804 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu6 17780 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu7 17713 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 142089 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0 17723 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1 17686 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2 17822 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3 17766 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu4 17795 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu5 17804 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu6 17780 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu7 17713 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 142089 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0 0.062259 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1 0.059590 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2 0.059533 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3 0.061592 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu4 0.064168 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu5 0.058325 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu6 0.059979 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu7 0.060609 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.060757 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0 0.829332 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1 0.848873 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2 0.869838 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3 0.846795 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu4 0.849826 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu5 0.849785 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu6 0.855502 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu7 0.840969 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.848796 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0 0.691099 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1 0.690909 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2 0.698206 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3 0.691288 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu4 0.688740 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu5 0.700974 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu6 0.696016 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu7 0.695005 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.694039 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0 0.285900 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1 0.285367 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2 0.285265 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3 0.286165 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu4 0.288901 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu5 0.291901 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu6 0.286277 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu7 0.284311 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.286764 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0 0.285900 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1 0.285367 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2 0.285265 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3 0.286165 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu4 0.288901 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu5 0.291901 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu6 0.286277 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu7 0.284311 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.286764 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0 62377.513361 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1 62169.748892 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2 62452.510204 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3 61630.573864 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu4 60510.854993 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu5 61168.568835 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu6 61551.557496 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu7 62294.117986 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 61764.385627 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0 28411.842105 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1 30063.506507 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2 29142.670279 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3 28476.412131 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu4 28295.962717 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu5 28907.321717 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu6 29543.387397 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu7 28235.201152 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 28885.073945 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0 53890.598714 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1 53907.423341 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2 53720.656435 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3 53860.604566 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu4 53889.443991 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu5 53861.318122 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu6 53943.320463 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu7 53817.424326 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 53861.369807 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0 55081.480166 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1 55015.724193 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2 54898.872738 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3 54936.540519 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu4 54830.943980 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu5 54790.718299 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu6 54970.208251 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu7 54987.261914 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 54938.225053 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0 55081.480166 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1 55015.724193 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2 54898.872738 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3 54936.540519 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu4 54830.943980 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu5 54790.718299 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu6 54970.208251 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu7 54987.261914 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 54938.225053 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 12282 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.l2c.blocked::no_mshrs 1706 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.l2c.avg_blocked_cycles::no_mshrs 7.199297 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.l2c.writebacks::writebacks 6093 # number of writebacks
system.l2c.writebacks::total 6093 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1 4 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2 2 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3 7 # number of ReadReq MSHR hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_mshr_hits::cpu4 6 # number of ReadReq MSHR hits
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.l2c.ReadReq_mshr_hits::cpu5 10 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu6 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu7 7 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 38 # number of ReadReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu2 1 # number of UpgradeReq MSHR hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu0 2 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu1 6 # number of ReadExReq MSHR hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.l2c.ReadExReq_mshr_hits::cpu3 6 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu4 6 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu5 2 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu6 6 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu7 4 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::total 35 # number of ReadExReq MSHR hits
system.l2c.demand_mshr_hits::cpu0 3 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1 10 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2 5 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3 13 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu4 12 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu5 12 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu6 7 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu7 11 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0 3 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1 10 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2 5 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3 13 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu4 12 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu5 12 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu6 7 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu7 11 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 73 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0 710 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1 673 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2 684 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3 697 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu4 725 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu5 651 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu6 686 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu7 688 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 5514 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0 1900 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1 1921 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2 1937 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3 1928 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu4 1957 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu5 1980 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu6 1936 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu7 1909 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 15468 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0 4354 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1 4364 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2 4395 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3 4374 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu4 4404 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu5 4534 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu6 4397 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu7 4337 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 35159 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0 5064 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1 5037 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2 5079 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3 5071 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu4 5129 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu5 5185 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu6 5083 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu7 5025 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 40673 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0 5064 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1 5037 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2 5079 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3 5071 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu4 5129 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu5 5185 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu6 5083 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu7 5025 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 40673 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0 35751412 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1 33806921 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2 34429923 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3 34692924 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu4 35248936 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu5 32226426 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu6 33940420 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu7 34712413 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 274809375 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0 77994997 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1 78725495 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2 79510490 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3 79106497 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu4 80259995 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu5 81257495 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu6 79519997 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu7 78273997 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 634648963 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0 181946449 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1 182532940 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2 182934447 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3 182700448 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu4 184033448 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu5 189305939 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu6 184033940 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu7 180980939 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 1468468550 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0 217697861 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1 216339861 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2 217364370 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3 217393372 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu4 219282384 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu5 221532365 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu6 217974360 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu7 215693352 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 1743277925 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0 217697861 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1 216339861 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2 217364370 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3 217393372 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu4 219282384 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu5 221532365 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu6 217974360 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu7 215693352 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 1743277925 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 401967952 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 402344948 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 400970454 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 406380953 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 407457452 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 405842942 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 405383447 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 402958951 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 3233307099 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 231807968 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 231164475 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 229115474 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 232479973 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 225183971 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 232284466 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 236479465 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 230210970 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 1848726762 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0 633775920 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1 633509423 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2 630085928 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3 638860926 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu4 632641423 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu5 638127408 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu6 641862912 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu7 633169921 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 5082033861 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0 0.062172 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1 0.059238 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2 0.059360 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3 0.060980 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu4 0.063641 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu5 0.057443 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu6 0.059892 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu7 0.059998 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.060341 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.829332 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.848873 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.869390 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.846356 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.849392 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.849785 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.855502 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.840969 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.848631 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.690782 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.689960 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.697730 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.690341 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.687803 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.700665 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.695068 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.694364 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.693348 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0 0.285730 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1 0.284802 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2 0.284985 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3 0.285433 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu4 0.288227 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu5 0.291227 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu6 0.285883 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu7 0.283690 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.286250 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0 0.285730 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1 0.284802 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2 0.284985 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3 0.285433 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu4 0.288227 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu5 0.291227 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu6 0.285883 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu7 0.283690 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.286250 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50354.101408 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 50233.166419 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50336.144737 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49774.639885 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 48619.222069 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49502.958525 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49475.830904 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50454.088663 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 49838.479325 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41049.998421 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40981.517439 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41048.265359 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41030.340768 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41011.750128 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41039.138889 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41074.378616 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41002.617601 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41029.801073 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41788.343822 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41826.979835 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41623.309898 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41769.649749 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41787.794732 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41752.522938 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41854.432568 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41729.522481 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 41766.505020 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0 42989.309044 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1 42950.141155 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2 42796.686356 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3 42869.921514 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu4 42753.438097 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu5 42725.624879 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu6 42883.013968 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu7 42924.050149 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 42860.814914 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0 42989.309044 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1 42950.141155 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2 42796.686356 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3 42869.921514 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu4 42753.438097 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu5 42725.624879 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu6 42883.013968 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu7 42924.050149 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 42860.814914 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.funcbus.throughput 0 # Throughput (bytes/s)
system.funcbus.data_through_bus 0 # Total data (bytes)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.toL2Bus.throughput 51067763763 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 370706 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 370692 # Transaction distribution
system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 43929 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 43926 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 76131 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 28975 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 28973 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 161585 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 161579 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120187 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120466 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120142 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120511 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120525 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120784 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120880 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120421 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 963916 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1756245 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1754904 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1765350 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1754211 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1769359 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1771216 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1757581 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1758989 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total 14087855 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 14087855 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 19957440 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 655042579 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 98.3 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 160407425 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer0.utilization 24.1 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.toL2Bus.respLayer1.occupancy 161285735 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer1.utilization 24.2 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.toL2Bus.respLayer2.occupancy 160748299 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 24.1 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 160702936 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 24.1 # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy 160745511 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 24.1 # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy 160832963 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 24.1 # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy 161488791 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer6.utilization 24.2 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.toL2Bus.respLayer7.occupancy 160912467 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 24.1 # Layer utilization (%)
system.cpu0.num_reads 99051 # number of read accesses completed
system.cpu0.num_writes 54715 # number of write accesses completed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.num_copies 0 # number of copy accesses completed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu0.l1c.tags.replacements 22485 # number of replacements
system.cpu0.l1c.tags.tagsinuse 393.562401 # Cycle average of tags in use
system.cpu0.l1c.tags.total_refs 13294 # Total number of references to valid blocks.
system.cpu0.l1c.tags.sampled_refs 22895 # Sample count of references to valid blocks.
system.cpu0.l1c.tags.avg_refs 0.580651 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu0.l1c.tags.occ_blocks::cpu0 393.562401 # Average occupied blocks per requestor
system.cpu0.l1c.tags.occ_percent::cpu0 0.768677 # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_percent::total 0.768677 # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_task_id_blocks::1024 410 # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id
system.cpu0.l1c.tags.occ_task_id_percent::1024 0.800781 # Percentage of cache occupancy per task id
system.cpu0.l1c.tags.tag_accesses 336265 # Number of tag accesses
system.cpu0.l1c.tags.data_accesses 336265 # Number of data accesses
system.cpu0.l1c.ReadReq_hits::cpu0 8671 # number of ReadReq hits
system.cpu0.l1c.ReadReq_hits::total 8671 # number of ReadReq hits
system.cpu0.l1c.WriteReq_hits::cpu0 1068 # number of WriteReq hits
system.cpu0.l1c.WriteReq_hits::total 1068 # number of WriteReq hits
system.cpu0.l1c.demand_hits::cpu0 9739 # number of demand (read+write) hits
system.cpu0.l1c.demand_hits::total 9739 # number of demand (read+write) hits
system.cpu0.l1c.overall_hits::cpu0 9739 # number of overall hits
system.cpu0.l1c.overall_hits::total 9739 # number of overall hits
system.cpu0.l1c.ReadReq_misses::cpu0 36428 # number of ReadReq misses
system.cpu0.l1c.ReadReq_misses::total 36428 # number of ReadReq misses
system.cpu0.l1c.WriteReq_misses::cpu0 23756 # number of WriteReq misses
system.cpu0.l1c.WriteReq_misses::total 23756 # number of WriteReq misses
system.cpu0.l1c.demand_misses::cpu0 60184 # number of demand (read+write) misses
system.cpu0.l1c.demand_misses::total 60184 # number of demand (read+write) misses
system.cpu0.l1c.overall_misses::cpu0 60184 # number of overall misses
system.cpu0.l1c.overall_misses::total 60184 # number of overall misses
system.cpu0.l1c.ReadReq_miss_latency::cpu0 963275637 # number of ReadReq miss cycles
system.cpu0.l1c.ReadReq_miss_latency::total 963275637 # number of ReadReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::cpu0 887897909 # number of WriteReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::total 887897909 # number of WriteReq miss cycles
system.cpu0.l1c.demand_miss_latency::cpu0 1851173546 # number of demand (read+write) miss cycles
system.cpu0.l1c.demand_miss_latency::total 1851173546 # number of demand (read+write) miss cycles
system.cpu0.l1c.overall_miss_latency::cpu0 1851173546 # number of overall miss cycles
system.cpu0.l1c.overall_miss_latency::total 1851173546 # number of overall miss cycles
system.cpu0.l1c.ReadReq_accesses::cpu0 45099 # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.ReadReq_accesses::total 45099 # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::cpu0 24824 # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::total 24824 # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.demand_accesses::cpu0 69923 # number of demand (read+write) accesses
system.cpu0.l1c.demand_accesses::total 69923 # number of demand (read+write) accesses
system.cpu0.l1c.overall_accesses::cpu0 69923 # number of overall (read+write) accesses
system.cpu0.l1c.overall_accesses::total 69923 # number of overall (read+write) accesses
system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807734 # miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_miss_rate::total 0.807734 # miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956977 # miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_miss_rate::total 0.956977 # miss rate for WriteReq accesses
system.cpu0.l1c.demand_miss_rate::cpu0 0.860718 # miss rate for demand accesses
system.cpu0.l1c.demand_miss_rate::total 0.860718 # miss rate for demand accesses
system.cpu0.l1c.overall_miss_rate::cpu0 0.860718 # miss rate for overall accesses
system.cpu0.l1c.overall_miss_rate::total 0.860718 # miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 26443.275420 # average ReadReq miss latency
system.cpu0.l1c.ReadReq_avg_miss_latency::total 26443.275420 # average ReadReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 37375.732825 # average WriteReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::total 37375.732825 # average WriteReq miss latency
system.cpu0.l1c.demand_avg_miss_latency::cpu0 30758.566164 # average overall miss latency
system.cpu0.l1c.demand_avg_miss_latency::total 30758.566164 # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::cpu0 30758.566164 # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::total 30758.566164 # average overall miss latency
system.cpu0.l1c.blocked_cycles::no_mshrs 1029913 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu0.l1c.blocked::no_mshrs 62692 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu0.l1c.avg_blocked_cycles::no_mshrs 16.428141 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu0.l1c.writebacks::writebacks 9798 # number of writebacks
system.cpu0.l1c.writebacks::total 9798 # number of writebacks
system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36428 # number of ReadReq MSHR misses
system.cpu0.l1c.ReadReq_mshr_misses::total 36428 # number of ReadReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23756 # number of WriteReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::total 23756 # number of WriteReq MSHR misses
system.cpu0.l1c.demand_mshr_misses::cpu0 60184 # number of demand (read+write) MSHR misses
system.cpu0.l1c.demand_mshr_misses::total 60184 # number of demand (read+write) MSHR misses
system.cpu0.l1c.overall_mshr_misses::cpu0 60184 # number of overall MSHR misses
system.cpu0.l1c.overall_mshr_misses::total 60184 # number of overall MSHR misses
system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 885441811 # number of ReadReq MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_miss_latency::total 885441811 # number of ReadReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 837618111 # number of WriteReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::total 837618111 # number of WriteReq MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1723059922 # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::total 1723059922 # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1723059922 # number of overall MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::total 1723059922 # number of overall MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 694921548 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 694921548 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1720175961 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1720175961 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2415097509 # number of overall MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2415097509 # number of overall MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807734 # mshr miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807734 # mshr miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956977 # mshr miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956977 # mshr miss rate for WriteReq accesses
system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860718 # mshr miss rate for demand accesses
system.cpu0.l1c.demand_mshr_miss_rate::total 0.860718 # mshr miss rate for demand accesses
system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860718 # mshr miss rate for overall accesses
system.cpu0.l1c.overall_mshr_miss_rate::total 0.860718 # mshr miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 24306.627073 # average ReadReq mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 24306.627073 # average ReadReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 35259.223396 # average WriteReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 35259.223396 # average WriteReq mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 28629.867108 # average overall mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::total 28629.867108 # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28629.867108 # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28629.867108 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu1.num_reads 99180 # number of read accesses completed
system.cpu1.num_writes 55130 # number of write accesses completed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.num_copies 0 # number of copy accesses completed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu1.l1c.tags.replacements 22560 # number of replacements
system.cpu1.l1c.tags.tagsinuse 393.358014 # Cycle average of tags in use
system.cpu1.l1c.tags.total_refs 13364 # Total number of references to valid blocks.
system.cpu1.l1c.tags.sampled_refs 22961 # Sample count of references to valid blocks.
system.cpu1.l1c.tags.avg_refs 0.582030 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu1.l1c.tags.occ_blocks::cpu1 393.358014 # Average occupied blocks per requestor
system.cpu1.l1c.tags.occ_percent::cpu1 0.768277 # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_percent::total 0.768277 # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
system.cpu1.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id
system.cpu1.l1c.tags.tag_accesses 338096 # Number of tag accesses
system.cpu1.l1c.tags.data_accesses 338096 # Number of data accesses
system.cpu1.l1c.ReadReq_hits::cpu1 8639 # number of ReadReq hits
system.cpu1.l1c.ReadReq_hits::total 8639 # number of ReadReq hits
system.cpu1.l1c.WriteReq_hits::cpu1 1152 # number of WriteReq hits
system.cpu1.l1c.WriteReq_hits::total 1152 # number of WriteReq hits
system.cpu1.l1c.demand_hits::cpu1 9791 # number of demand (read+write) hits
system.cpu1.l1c.demand_hits::total 9791 # number of demand (read+write) hits
system.cpu1.l1c.overall_hits::cpu1 9791 # number of overall hits
system.cpu1.l1c.overall_hits::total 9791 # number of overall hits
system.cpu1.l1c.ReadReq_misses::cpu1 36744 # number of ReadReq misses
system.cpu1.l1c.ReadReq_misses::total 36744 # number of ReadReq misses
system.cpu1.l1c.WriteReq_misses::cpu1 23766 # number of WriteReq misses
system.cpu1.l1c.WriteReq_misses::total 23766 # number of WriteReq misses
system.cpu1.l1c.demand_misses::cpu1 60510 # number of demand (read+write) misses
system.cpu1.l1c.demand_misses::total 60510 # number of demand (read+write) misses
system.cpu1.l1c.overall_misses::cpu1 60510 # number of overall misses
system.cpu1.l1c.overall_misses::total 60510 # number of overall misses
system.cpu1.l1c.ReadReq_miss_latency::cpu1 969995629 # number of ReadReq miss cycles
system.cpu1.l1c.ReadReq_miss_latency::total 969995629 # number of ReadReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::cpu1 886374819 # number of WriteReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::total 886374819 # number of WriteReq miss cycles
system.cpu1.l1c.demand_miss_latency::cpu1 1856370448 # number of demand (read+write) miss cycles
system.cpu1.l1c.demand_miss_latency::total 1856370448 # number of demand (read+write) miss cycles
system.cpu1.l1c.overall_miss_latency::cpu1 1856370448 # number of overall miss cycles
system.cpu1.l1c.overall_miss_latency::total 1856370448 # number of overall miss cycles
system.cpu1.l1c.ReadReq_accesses::cpu1 45383 # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.ReadReq_accesses::total 45383 # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::cpu1 24918 # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::total 24918 # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.demand_accesses::cpu1 70301 # number of demand (read+write) accesses
system.cpu1.l1c.demand_accesses::total 70301 # number of demand (read+write) accesses
system.cpu1.l1c.overall_accesses::cpu1 70301 # number of overall (read+write) accesses
system.cpu1.l1c.overall_accesses::total 70301 # number of overall (read+write) accesses
system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.809642 # miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_miss_rate::total 0.809642 # miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953768 # miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_miss_rate::total 0.953768 # miss rate for WriteReq accesses
system.cpu1.l1c.demand_miss_rate::cpu1 0.860727 # miss rate for demand accesses
system.cpu1.l1c.demand_miss_rate::total 0.860727 # miss rate for demand accesses
system.cpu1.l1c.overall_miss_rate::cpu1 0.860727 # miss rate for overall accesses
system.cpu1.l1c.overall_miss_rate::total 0.860727 # miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 26398.748884 # average ReadReq miss latency
system.cpu1.l1c.ReadReq_avg_miss_latency::total 26398.748884 # average ReadReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 37295.919339 # average WriteReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::total 37295.919339 # average WriteReq miss latency
system.cpu1.l1c.demand_avg_miss_latency::cpu1 30678.738192 # average overall miss latency
system.cpu1.l1c.demand_avg_miss_latency::total 30678.738192 # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::cpu1 30678.738192 # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::total 30678.738192 # average overall miss latency
system.cpu1.l1c.blocked_cycles::no_mshrs 1031479 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu1.l1c.blocked::no_mshrs 63034 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu1.l1c.avg_blocked_cycles::no_mshrs 16.363851 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu1.l1c.writebacks::writebacks 9822 # number of writebacks
system.cpu1.l1c.writebacks::total 9822 # number of writebacks
system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36744 # number of ReadReq MSHR misses
system.cpu1.l1c.ReadReq_mshr_misses::total 36744 # number of ReadReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23766 # number of WriteReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::total 23766 # number of WriteReq MSHR misses
system.cpu1.l1c.demand_mshr_misses::cpu1 60510 # number of demand (read+write) MSHR misses
system.cpu1.l1c.demand_mshr_misses::total 60510 # number of demand (read+write) MSHR misses
system.cpu1.l1c.overall_mshr_misses::cpu1 60510 # number of overall MSHR misses
system.cpu1.l1c.overall_mshr_misses::total 60510 # number of overall MSHR misses
system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 891488909 # number of ReadReq MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_miss_latency::total 891488909 # number of ReadReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 836075987 # number of WriteReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::total 836075987 # number of WriteReq MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1727564896 # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::total 1727564896 # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1727564896 # number of overall MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::total 1727564896 # number of overall MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 694858067 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 694858067 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1710734008 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1710734008 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2405592075 # number of overall MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2405592075 # number of overall MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.809642 # mshr miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.809642 # mshr miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953768 # mshr miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953768 # mshr miss rate for WriteReq accesses
system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860727 # mshr miss rate for demand accesses
system.cpu1.l1c.demand_mshr_miss_rate::total 0.860727 # mshr miss rate for demand accesses
system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860727 # mshr miss rate for overall accesses
system.cpu1.l1c.overall_mshr_miss_rate::total 0.860727 # mshr miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 24262.162775 # average ReadReq mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 24262.162775 # average ReadReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 35179.499579 # average WriteReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 35179.499579 # average WriteReq mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28550.072649 # average overall mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28550.072649 # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28550.072649 # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28550.072649 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu2.num_reads 99086 # number of read accesses completed
system.cpu2.num_writes 55118 # number of write accesses completed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu2.num_copies 0 # number of copy accesses completed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu2.l1c.tags.replacements 22404 # number of replacements
system.cpu2.l1c.tags.tagsinuse 393.163299 # Cycle average of tags in use
system.cpu2.l1c.tags.total_refs 13438 # Total number of references to valid blocks.
system.cpu2.l1c.tags.sampled_refs 22793 # Sample count of references to valid blocks.
system.cpu2.l1c.tags.avg_refs 0.589567 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu2.l1c.tags.occ_blocks::cpu2 393.163299 # Average occupied blocks per requestor
system.cpu2.l1c.tags.occ_percent::cpu2 0.767897 # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_percent::total 0.767897 # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::0 372 # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id
system.cpu2.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id
system.cpu2.l1c.tags.tag_accesses 337674 # Number of tag accesses
system.cpu2.l1c.tags.data_accesses 337674 # Number of data accesses
system.cpu2.l1c.ReadReq_hits::cpu2 8791 # number of ReadReq hits
system.cpu2.l1c.ReadReq_hits::total 8791 # number of ReadReq hits
system.cpu2.l1c.WriteReq_hits::cpu2 1160 # number of WriteReq hits
system.cpu2.l1c.WriteReq_hits::total 1160 # number of WriteReq hits
system.cpu2.l1c.demand_hits::cpu2 9951 # number of demand (read+write) hits
system.cpu2.l1c.demand_hits::total 9951 # number of demand (read+write) hits
system.cpu2.l1c.overall_hits::cpu2 9951 # number of overall hits
system.cpu2.l1c.overall_hits::total 9951 # number of overall hits
system.cpu2.l1c.ReadReq_misses::cpu2 36516 # number of ReadReq misses
system.cpu2.l1c.ReadReq_misses::total 36516 # number of ReadReq misses
system.cpu2.l1c.WriteReq_misses::cpu2 23770 # number of WriteReq misses
system.cpu2.l1c.WriteReq_misses::total 23770 # number of WriteReq misses
system.cpu2.l1c.demand_misses::cpu2 60286 # number of demand (read+write) misses
system.cpu2.l1c.demand_misses::total 60286 # number of demand (read+write) misses
system.cpu2.l1c.overall_misses::cpu2 60286 # number of overall misses
system.cpu2.l1c.overall_misses::total 60286 # number of overall misses
system.cpu2.l1c.ReadReq_miss_latency::cpu2 967487980 # number of ReadReq miss cycles
system.cpu2.l1c.ReadReq_miss_latency::total 967487980 # number of ReadReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::cpu2 890162777 # number of WriteReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::total 890162777 # number of WriteReq miss cycles
system.cpu2.l1c.demand_miss_latency::cpu2 1857650757 # number of demand (read+write) miss cycles
system.cpu2.l1c.demand_miss_latency::total 1857650757 # number of demand (read+write) miss cycles
system.cpu2.l1c.overall_miss_latency::cpu2 1857650757 # number of overall miss cycles
system.cpu2.l1c.overall_miss_latency::total 1857650757 # number of overall miss cycles
system.cpu2.l1c.ReadReq_accesses::cpu2 45307 # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.ReadReq_accesses::total 45307 # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::cpu2 24930 # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::total 24930 # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.demand_accesses::cpu2 70237 # number of demand (read+write) accesses
system.cpu2.l1c.demand_accesses::total 70237 # number of demand (read+write) accesses
system.cpu2.l1c.overall_accesses::cpu2 70237 # number of overall (read+write) accesses
system.cpu2.l1c.overall_accesses::total 70237 # number of overall (read+write) accesses
system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805968 # miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_miss_rate::total 0.805968 # miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953470 # miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_miss_rate::total 0.953470 # miss rate for WriteReq accesses
system.cpu2.l1c.demand_miss_rate::cpu2 0.858323 # miss rate for demand accesses
system.cpu2.l1c.demand_miss_rate::total 0.858323 # miss rate for demand accesses
system.cpu2.l1c.overall_miss_rate::cpu2 0.858323 # miss rate for overall accesses
system.cpu2.l1c.overall_miss_rate::total 0.858323 # miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 26494.905795 # average ReadReq miss latency
system.cpu2.l1c.ReadReq_avg_miss_latency::total 26494.905795 # average ReadReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 37449.001977 # average WriteReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::total 37449.001977 # average WriteReq miss latency
system.cpu2.l1c.demand_avg_miss_latency::cpu2 30813.966045 # average overall miss latency
system.cpu2.l1c.demand_avg_miss_latency::total 30813.966045 # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::cpu2 30813.966045 # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::total 30813.966045 # average overall miss latency
system.cpu2.l1c.blocked_cycles::no_mshrs 1030263 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu2.l1c.blocked::no_mshrs 62774 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu2.l1c.avg_blocked_cycles::no_mshrs 16.412257 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu2.l1c.writebacks::writebacks 9856 # number of writebacks
system.cpu2.l1c.writebacks::total 9856 # number of writebacks
system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36516 # number of ReadReq MSHR misses
system.cpu2.l1c.ReadReq_mshr_misses::total 36516 # number of ReadReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23770 # number of WriteReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::total 23770 # number of WriteReq MSHR misses
system.cpu2.l1c.demand_mshr_misses::cpu2 60286 # number of demand (read+write) MSHR misses
system.cpu2.l1c.demand_mshr_misses::total 60286 # number of demand (read+write) MSHR misses
system.cpu2.l1c.overall_mshr_misses::cpu2 60286 # number of overall MSHR misses
system.cpu2.l1c.overall_mshr_misses::total 60286 # number of overall MSHR misses
system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 889398318 # number of ReadReq MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_miss_latency::total 889398318 # number of ReadReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 839809073 # number of WriteReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::total 839809073 # number of WriteReq MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1729207391 # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::total 1729207391 # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1729207391 # number of overall MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::total 1729207391 # number of overall MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 693154089 # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 693154089 # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1689336031 # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1689336031 # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2382490120 # number of overall MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2382490120 # number of overall MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805968 # mshr miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805968 # mshr miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953470 # mshr miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953470 # mshr miss rate for WriteReq accesses
system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858323 # mshr miss rate for demand accesses
system.cpu2.l1c.demand_mshr_miss_rate::total 0.858323 # mshr miss rate for demand accesses
system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858323 # mshr miss rate for overall accesses
system.cpu2.l1c.overall_mshr_miss_rate::total 0.858323 # mshr miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 24356.400427 # average ReadReq mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 24356.400427 # average ReadReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 35330.629912 # average WriteReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 35330.629912 # average WriteReq mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 28683.398982 # average overall mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::total 28683.398982 # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 28683.398982 # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::total 28683.398982 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu3.num_reads 99021 # number of read accesses completed
system.cpu3.num_writes 54970 # number of write accesses completed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu3.num_copies 0 # number of copy accesses completed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu3.l1c.tags.replacements 22272 # number of replacements
system.cpu3.l1c.tags.tagsinuse 393.391803 # Cycle average of tags in use
system.cpu3.l1c.tags.total_refs 13521 # Total number of references to valid blocks.
system.cpu3.l1c.tags.sampled_refs 22662 # Sample count of references to valid blocks.
system.cpu3.l1c.tags.avg_refs 0.596638 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu3.l1c.tags.occ_blocks::cpu3 393.391803 # Average occupied blocks per requestor
system.cpu3.l1c.tags.occ_percent::cpu3 0.768343 # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_percent::total 0.768343 # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_task_id_blocks::1024 390 # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::0 367 # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id
system.cpu3.l1c.tags.occ_task_id_percent::1024 0.761719 # Percentage of cache occupancy per task id
system.cpu3.l1c.tags.tag_accesses 337590 # Number of tag accesses
system.cpu3.l1c.tags.data_accesses 337590 # Number of data accesses
system.cpu3.l1c.ReadReq_hits::cpu3 8806 # number of ReadReq hits
system.cpu3.l1c.ReadReq_hits::total 8806 # number of ReadReq hits
system.cpu3.l1c.WriteReq_hits::cpu3 1159 # number of WriteReq hits
system.cpu3.l1c.WriteReq_hits::total 1159 # number of WriteReq hits
system.cpu3.l1c.demand_hits::cpu3 9965 # number of demand (read+write) hits
system.cpu3.l1c.demand_hits::total 9965 # number of demand (read+write) hits
system.cpu3.l1c.overall_hits::cpu3 9965 # number of overall hits
system.cpu3.l1c.overall_hits::total 9965 # number of overall hits
system.cpu3.l1c.ReadReq_misses::cpu3 36397 # number of ReadReq misses
system.cpu3.l1c.ReadReq_misses::total 36397 # number of ReadReq misses
system.cpu3.l1c.WriteReq_misses::cpu3 23878 # number of WriteReq misses
system.cpu3.l1c.WriteReq_misses::total 23878 # number of WriteReq misses
system.cpu3.l1c.demand_misses::cpu3 60275 # number of demand (read+write) misses
system.cpu3.l1c.demand_misses::total 60275 # number of demand (read+write) misses
system.cpu3.l1c.overall_misses::cpu3 60275 # number of overall misses
system.cpu3.l1c.overall_misses::total 60275 # number of overall misses
system.cpu3.l1c.ReadReq_miss_latency::cpu3 959708337 # number of ReadReq miss cycles
system.cpu3.l1c.ReadReq_miss_latency::total 959708337 # number of ReadReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::cpu3 888157516 # number of WriteReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::total 888157516 # number of WriteReq miss cycles
system.cpu3.l1c.demand_miss_latency::cpu3 1847865853 # number of demand (read+write) miss cycles
system.cpu3.l1c.demand_miss_latency::total 1847865853 # number of demand (read+write) miss cycles
system.cpu3.l1c.overall_miss_latency::cpu3 1847865853 # number of overall miss cycles
system.cpu3.l1c.overall_miss_latency::total 1847865853 # number of overall miss cycles
system.cpu3.l1c.ReadReq_accesses::cpu3 45203 # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.ReadReq_accesses::total 45203 # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::cpu3 25037 # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::total 25037 # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.demand_accesses::cpu3 70240 # number of demand (read+write) accesses
system.cpu3.l1c.demand_accesses::total 70240 # number of demand (read+write) accesses
system.cpu3.l1c.overall_accesses::cpu3 70240 # number of overall (read+write) accesses
system.cpu3.l1c.overall_accesses::total 70240 # number of overall (read+write) accesses
system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.805190 # miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_miss_rate::total 0.805190 # miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953709 # miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_miss_rate::total 0.953709 # miss rate for WriteReq accesses
system.cpu3.l1c.demand_miss_rate::cpu3 0.858129 # miss rate for demand accesses
system.cpu3.l1c.demand_miss_rate::total 0.858129 # miss rate for demand accesses
system.cpu3.l1c.overall_miss_rate::cpu3 0.858129 # miss rate for overall accesses
system.cpu3.l1c.overall_miss_rate::total 0.858129 # miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 26367.786823 # average ReadReq miss latency
system.cpu3.l1c.ReadReq_avg_miss_latency::total 26367.786823 # average ReadReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 37195.641008 # average WriteReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::total 37195.641008 # average WriteReq miss latency
system.cpu3.l1c.demand_avg_miss_latency::cpu3 30657.251813 # average overall miss latency
system.cpu3.l1c.demand_avg_miss_latency::total 30657.251813 # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::cpu3 30657.251813 # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::total 30657.251813 # average overall miss latency
system.cpu3.l1c.blocked_cycles::no_mshrs 1032981 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu3.l1c.blocked::no_mshrs 63001 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu3.l1c.avg_blocked_cycles::no_mshrs 16.396264 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu3.l1c.writebacks::writebacks 9730 # number of writebacks
system.cpu3.l1c.writebacks::total 9730 # number of writebacks
system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36397 # number of ReadReq MSHR misses
system.cpu3.l1c.ReadReq_mshr_misses::total 36397 # number of ReadReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23878 # number of WriteReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::total 23878 # number of WriteReq MSHR misses
system.cpu3.l1c.demand_mshr_misses::cpu3 60275 # number of demand (read+write) MSHR misses
system.cpu3.l1c.demand_mshr_misses::total 60275 # number of demand (read+write) MSHR misses
system.cpu3.l1c.overall_mshr_misses::cpu3 60275 # number of overall MSHR misses
system.cpu3.l1c.overall_mshr_misses::total 60275 # number of overall MSHR misses
system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 882022203 # number of ReadReq MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_miss_latency::total 882022203 # number of ReadReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 837608778 # number of WriteReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::total 837608778 # number of WriteReq MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1719630981 # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::total 1719630981 # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1719630981 # number of overall MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::total 1719630981 # number of overall MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 701721013 # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 701721013 # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1702236593 # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1702236593 # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2403957606 # number of overall MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2403957606 # number of overall MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805190 # mshr miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805190 # mshr miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953709 # mshr miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953709 # mshr miss rate for WriteReq accesses
system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858129 # mshr miss rate for demand accesses
system.cpu3.l1c.demand_mshr_miss_rate::total 0.858129 # mshr miss rate for demand accesses
system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858129 # mshr miss rate for overall accesses
system.cpu3.l1c.overall_mshr_miss_rate::total 0.858129 # mshr miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 24233.376460 # average ReadReq mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 24233.376460 # average ReadReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 35078.682385 # average WriteReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 35078.682385 # average WriteReq mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 28529.754973 # average overall mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28529.754973 # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28529.754973 # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28529.754973 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu4.num_reads 99302 # number of read accesses completed
system.cpu4.num_writes 55134 # number of write accesses completed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu4.num_copies 0 # number of copy accesses completed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu4.l1c.tags.replacements 22459 # number of replacements
system.cpu4.l1c.tags.tagsinuse 393.483256 # Cycle average of tags in use
system.cpu4.l1c.tags.total_refs 13509 # Total number of references to valid blocks.
system.cpu4.l1c.tags.sampled_refs 22848 # Sample count of references to valid blocks.
system.cpu4.l1c.tags.avg_refs 0.591255 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu4.l1c.tags.occ_blocks::cpu4 393.483256 # Average occupied blocks per requestor
system.cpu4.l1c.tags.occ_percent::cpu4 0.768522 # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_percent::total 0.768522 # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::0 356 # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
system.cpu4.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id
system.cpu4.l1c.tags.tag_accesses 337715 # Number of tag accesses
system.cpu4.l1c.tags.data_accesses 337715 # Number of data accesses
system.cpu4.l1c.ReadReq_hits::cpu4 8739 # number of ReadReq hits
system.cpu4.l1c.ReadReq_hits::total 8739 # number of ReadReq hits
system.cpu4.l1c.WriteReq_hits::cpu4 1196 # number of WriteReq hits
system.cpu4.l1c.WriteReq_hits::total 1196 # number of WriteReq hits
system.cpu4.l1c.demand_hits::cpu4 9935 # number of demand (read+write) hits
system.cpu4.l1c.demand_hits::total 9935 # number of demand (read+write) hits
system.cpu4.l1c.overall_hits::cpu4 9935 # number of overall hits
system.cpu4.l1c.overall_hits::total 9935 # number of overall hits
system.cpu4.l1c.ReadReq_misses::cpu4 36407 # number of ReadReq misses
system.cpu4.l1c.ReadReq_misses::total 36407 # number of ReadReq misses
system.cpu4.l1c.WriteReq_misses::cpu4 23914 # number of WriteReq misses
system.cpu4.l1c.WriteReq_misses::total 23914 # number of WriteReq misses
system.cpu4.l1c.demand_misses::cpu4 60321 # number of demand (read+write) misses
system.cpu4.l1c.demand_misses::total 60321 # number of demand (read+write) misses
system.cpu4.l1c.overall_misses::cpu4 60321 # number of overall misses
system.cpu4.l1c.overall_misses::total 60321 # number of overall misses
system.cpu4.l1c.ReadReq_miss_latency::cpu4 962640133 # number of ReadReq miss cycles
system.cpu4.l1c.ReadReq_miss_latency::total 962640133 # number of ReadReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::cpu4 889456301 # number of WriteReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::total 889456301 # number of WriteReq miss cycles
system.cpu4.l1c.demand_miss_latency::cpu4 1852096434 # number of demand (read+write) miss cycles
system.cpu4.l1c.demand_miss_latency::total 1852096434 # number of demand (read+write) miss cycles
system.cpu4.l1c.overall_miss_latency::cpu4 1852096434 # number of overall miss cycles
system.cpu4.l1c.overall_miss_latency::total 1852096434 # number of overall miss cycles
system.cpu4.l1c.ReadReq_accesses::cpu4 45146 # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.ReadReq_accesses::total 45146 # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::cpu4 25110 # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::total 25110 # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.demand_accesses::cpu4 70256 # number of demand (read+write) accesses
system.cpu4.l1c.demand_accesses::total 70256 # number of demand (read+write) accesses
system.cpu4.l1c.overall_accesses::cpu4 70256 # number of overall (read+write) accesses
system.cpu4.l1c.overall_accesses::total 70256 # number of overall (read+write) accesses
system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.806428 # miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_miss_rate::total 0.806428 # miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952370 # miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_miss_rate::total 0.952370 # miss rate for WriteReq accesses
system.cpu4.l1c.demand_miss_rate::cpu4 0.858589 # miss rate for demand accesses
system.cpu4.l1c.demand_miss_rate::total 0.858589 # miss rate for demand accesses
system.cpu4.l1c.overall_miss_rate::cpu4 0.858589 # miss rate for overall accesses
system.cpu4.l1c.overall_miss_rate::total 0.858589 # miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 26441.072678 # average ReadReq miss latency
system.cpu4.l1c.ReadReq_avg_miss_latency::total 26441.072678 # average ReadReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 37193.957556 # average WriteReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::total 37193.957556 # average WriteReq miss latency
system.cpu4.l1c.demand_avg_miss_latency::cpu4 30704.007460 # average overall miss latency
system.cpu4.l1c.demand_avg_miss_latency::total 30704.007460 # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::cpu4 30704.007460 # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::total 30704.007460 # average overall miss latency
system.cpu4.l1c.blocked_cycles::no_mshrs 1036597 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu4.l1c.blocked::no_mshrs 63051 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu4.l1c.avg_blocked_cycles::no_mshrs 16.440612 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu4.l1c.writebacks::writebacks 9933 # number of writebacks
system.cpu4.l1c.writebacks::total 9933 # number of writebacks
system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36407 # number of ReadReq MSHR misses
system.cpu4.l1c.ReadReq_mshr_misses::total 36407 # number of ReadReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23914 # number of WriteReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::total 23914 # number of WriteReq MSHR misses
system.cpu4.l1c.demand_mshr_misses::cpu4 60321 # number of demand (read+write) MSHR misses
system.cpu4.l1c.demand_mshr_misses::total 60321 # number of demand (read+write) MSHR misses
system.cpu4.l1c.overall_mshr_misses::cpu4 60321 # number of overall MSHR misses
system.cpu4.l1c.overall_mshr_misses::total 60321 # number of overall MSHR misses
system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 884868259 # number of ReadReq MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_miss_latency::total 884868259 # number of ReadReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 838892397 # number of WriteReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::total 838892397 # number of WriteReq MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1723760656 # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::total 1723760656 # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1723760656 # number of overall MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::total 1723760656 # number of overall MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 703520432 # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 703520432 # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1658146550 # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1658146550 # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2361666982 # number of overall MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2361666982 # number of overall MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.806428 # mshr miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.806428 # mshr miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952370 # mshr miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952370 # mshr miss rate for WriteReq accesses
system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858589 # mshr miss rate for demand accesses
system.cpu4.l1c.demand_mshr_miss_rate::total 0.858589 # mshr miss rate for demand accesses
system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858589 # mshr miss rate for overall accesses
system.cpu4.l1c.overall_mshr_miss_rate::total 0.858589 # mshr miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 24304.893537 # average ReadReq mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24304.893537 # average ReadReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 35079.551602 # average WriteReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 35079.551602 # average WriteReq mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 28576.460205 # average overall mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::total 28576.460205 # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 28576.460205 # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::total 28576.460205 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu5.num_reads 99936 # number of read accesses completed
system.cpu5.num_writes 55294 # number of write accesses completed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu5.num_copies 0 # number of copy accesses completed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu5.l1c.tags.replacements 22607 # number of replacements
system.cpu5.l1c.tags.tagsinuse 394.741985 # Cycle average of tags in use
system.cpu5.l1c.tags.total_refs 13577 # Total number of references to valid blocks.
system.cpu5.l1c.tags.sampled_refs 23024 # Sample count of references to valid blocks.
system.cpu5.l1c.tags.avg_refs 0.589689 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu5.l1c.tags.occ_blocks::cpu5 394.741985 # Average occupied blocks per requestor
system.cpu5.l1c.tags.occ_percent::cpu5 0.770980 # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_percent::total 0.770980 # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_task_id_blocks::1024 417 # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::0 390 # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id
system.cpu5.l1c.tags.occ_task_id_percent::1024 0.814453 # Percentage of cache occupancy per task id
system.cpu5.l1c.tags.tag_accesses 338075 # Number of tag accesses
system.cpu5.l1c.tags.data_accesses 338075 # Number of data accesses
system.cpu5.l1c.ReadReq_hits::cpu5 8826 # number of ReadReq hits
system.cpu5.l1c.ReadReq_hits::total 8826 # number of ReadReq hits
system.cpu5.l1c.WriteReq_hits::cpu5 1123 # number of WriteReq hits
system.cpu5.l1c.WriteReq_hits::total 1123 # number of WriteReq hits
system.cpu5.l1c.demand_hits::cpu5 9949 # number of demand (read+write) hits
system.cpu5.l1c.demand_hits::total 9949 # number of demand (read+write) hits
system.cpu5.l1c.overall_hits::cpu5 9949 # number of overall hits
system.cpu5.l1c.overall_hits::total 9949 # number of overall hits
system.cpu5.l1c.ReadReq_misses::cpu5 36440 # number of ReadReq misses
system.cpu5.l1c.ReadReq_misses::total 36440 # number of ReadReq misses
system.cpu5.l1c.WriteReq_misses::cpu5 23955 # number of WriteReq misses
system.cpu5.l1c.WriteReq_misses::total 23955 # number of WriteReq misses
system.cpu5.l1c.demand_misses::cpu5 60395 # number of demand (read+write) misses
system.cpu5.l1c.demand_misses::total 60395 # number of demand (read+write) misses
system.cpu5.l1c.overall_misses::cpu5 60395 # number of overall misses
system.cpu5.l1c.overall_misses::total 60395 # number of overall misses
system.cpu5.l1c.ReadReq_miss_latency::cpu5 954691213 # number of ReadReq miss cycles
system.cpu5.l1c.ReadReq_miss_latency::total 954691213 # number of ReadReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::cpu5 898328721 # number of WriteReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::total 898328721 # number of WriteReq miss cycles
system.cpu5.l1c.demand_miss_latency::cpu5 1853019934 # number of demand (read+write) miss cycles
system.cpu5.l1c.demand_miss_latency::total 1853019934 # number of demand (read+write) miss cycles
system.cpu5.l1c.overall_miss_latency::cpu5 1853019934 # number of overall miss cycles
system.cpu5.l1c.overall_miss_latency::total 1853019934 # number of overall miss cycles
system.cpu5.l1c.ReadReq_accesses::cpu5 45266 # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.ReadReq_accesses::total 45266 # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::cpu5 25078 # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::total 25078 # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.demand_accesses::cpu5 70344 # number of demand (read+write) accesses
system.cpu5.l1c.demand_accesses::total 70344 # number of demand (read+write) accesses
system.cpu5.l1c.overall_accesses::cpu5 70344 # number of overall (read+write) accesses
system.cpu5.l1c.overall_accesses::total 70344 # number of overall (read+write) accesses
system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.805019 # miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_miss_rate::total 0.805019 # miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.955220 # miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_miss_rate::total 0.955220 # miss rate for WriteReq accesses
system.cpu5.l1c.demand_miss_rate::cpu5 0.858566 # miss rate for demand accesses
system.cpu5.l1c.demand_miss_rate::total 0.858566 # miss rate for demand accesses
system.cpu5.l1c.overall_miss_rate::cpu5 0.858566 # miss rate for overall accesses
system.cpu5.l1c.overall_miss_rate::total 0.858566 # miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26198.990477 # average ReadReq miss latency
system.cpu5.l1c.ReadReq_avg_miss_latency::total 26198.990477 # average ReadReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 37500.677145 # average WriteReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::total 37500.677145 # average WriteReq miss latency
system.cpu5.l1c.demand_avg_miss_latency::cpu5 30681.677854 # average overall miss latency
system.cpu5.l1c.demand_avg_miss_latency::total 30681.677854 # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::cpu5 30681.677854 # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::total 30681.677854 # average overall miss latency
system.cpu5.l1c.blocked_cycles::no_mshrs 1031399 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu5.l1c.blocked::no_mshrs 62997 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu5.l1c.avg_blocked_cycles::no_mshrs 16.372192 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu5.l1c.writebacks::writebacks 9959 # number of writebacks
system.cpu5.l1c.writebacks::total 9959 # number of writebacks
system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36440 # number of ReadReq MSHR misses
system.cpu5.l1c.ReadReq_mshr_misses::total 36440 # number of ReadReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23955 # number of WriteReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::total 23955 # number of WriteReq MSHR misses
system.cpu5.l1c.demand_mshr_misses::cpu5 60395 # number of demand (read+write) MSHR misses
system.cpu5.l1c.demand_mshr_misses::total 60395 # number of demand (read+write) MSHR misses
system.cpu5.l1c.overall_mshr_misses::cpu5 60395 # number of overall MSHR misses
system.cpu5.l1c.overall_mshr_misses::total 60395 # number of overall MSHR misses
system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 876841351 # number of ReadReq MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_miss_latency::total 876841351 # number of ReadReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 847650833 # number of WriteReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::total 847650833 # number of WriteReq MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1724492184 # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::total 1724492184 # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1724492184 # number of overall MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::total 1724492184 # number of overall MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 699333550 # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 699333550 # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1696976001 # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1696976001 # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2396309551 # number of overall MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2396309551 # number of overall MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.805019 # mshr miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.805019 # mshr miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.955220 # mshr miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.955220 # mshr miss rate for WriteReq accesses
system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858566 # mshr miss rate for demand accesses
system.cpu5.l1c.demand_mshr_miss_rate::total 0.858566 # mshr miss rate for demand accesses
system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858566 # mshr miss rate for overall accesses
system.cpu5.l1c.overall_mshr_miss_rate::total 0.858566 # mshr miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 24062.605681 # average ReadReq mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 24062.605681 # average ReadReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 35385.131831 # average WriteReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 35385.131831 # average WriteReq mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 28553.558805 # average overall mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28553.558805 # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28553.558805 # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28553.558805 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu6.num_reads 100001 # number of read accesses completed
system.cpu6.num_writes 55113 # number of write accesses completed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu6.num_copies 0 # number of copy accesses completed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu6.l1c.tags.replacements 22596 # number of replacements
system.cpu6.l1c.tags.tagsinuse 393.612008 # Cycle average of tags in use
system.cpu6.l1c.tags.total_refs 13438 # Total number of references to valid blocks.
system.cpu6.l1c.tags.sampled_refs 23004 # Sample count of references to valid blocks.
system.cpu6.l1c.tags.avg_refs 0.584159 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu6.l1c.tags.occ_blocks::cpu6 393.612008 # Average occupied blocks per requestor
system.cpu6.l1c.tags.occ_percent::cpu6 0.768773 # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_percent::total 0.768773 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu6.l1c.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu6.l1c.tags.age_task_id_blocks_1024::0 386 # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu6.l1c.tags.occ_task_id_percent::1024 0.796875 # Percentage of cache occupancy per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu6.l1c.tags.tag_accesses 338625 # Number of tag accesses
system.cpu6.l1c.tags.data_accesses 338625 # Number of data accesses
system.cpu6.l1c.ReadReq_hits::cpu6 8756 # number of ReadReq hits
system.cpu6.l1c.ReadReq_hits::total 8756 # number of ReadReq hits
system.cpu6.l1c.WriteReq_hits::cpu6 1144 # number of WriteReq hits
system.cpu6.l1c.WriteReq_hits::total 1144 # number of WriteReq hits
system.cpu6.l1c.demand_hits::cpu6 9900 # number of demand (read+write) hits
system.cpu6.l1c.demand_hits::total 9900 # number of demand (read+write) hits
system.cpu6.l1c.overall_hits::cpu6 9900 # number of overall hits
system.cpu6.l1c.overall_hits::total 9900 # number of overall hits
system.cpu6.l1c.ReadReq_misses::cpu6 36780 # number of ReadReq misses
system.cpu6.l1c.ReadReq_misses::total 36780 # number of ReadReq misses
system.cpu6.l1c.WriteReq_misses::cpu6 23744 # number of WriteReq misses
system.cpu6.l1c.WriteReq_misses::total 23744 # number of WriteReq misses
system.cpu6.l1c.demand_misses::cpu6 60524 # number of demand (read+write) misses
system.cpu6.l1c.demand_misses::total 60524 # number of demand (read+write) misses
system.cpu6.l1c.overall_misses::cpu6 60524 # number of overall misses
system.cpu6.l1c.overall_misses::total 60524 # number of overall misses
system.cpu6.l1c.ReadReq_miss_latency::cpu6 967768080 # number of ReadReq miss cycles
system.cpu6.l1c.ReadReq_miss_latency::total 967768080 # number of ReadReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::cpu6 885331630 # number of WriteReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::total 885331630 # number of WriteReq miss cycles
system.cpu6.l1c.demand_miss_latency::cpu6 1853099710 # number of demand (read+write) miss cycles
system.cpu6.l1c.demand_miss_latency::total 1853099710 # number of demand (read+write) miss cycles
system.cpu6.l1c.overall_miss_latency::cpu6 1853099710 # number of overall miss cycles
system.cpu6.l1c.overall_miss_latency::total 1853099710 # number of overall miss cycles
system.cpu6.l1c.ReadReq_accesses::cpu6 45536 # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.ReadReq_accesses::total 45536 # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::cpu6 24888 # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::total 24888 # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.demand_accesses::cpu6 70424 # number of demand (read+write) accesses
system.cpu6.l1c.demand_accesses::total 70424 # number of demand (read+write) accesses
system.cpu6.l1c.overall_accesses::cpu6 70424 # number of overall (read+write) accesses
system.cpu6.l1c.overall_accesses::total 70424 # number of overall (read+write) accesses
system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807713 # miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_miss_rate::total 0.807713 # miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954034 # miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_miss_rate::total 0.954034 # miss rate for WriteReq accesses
system.cpu6.l1c.demand_miss_rate::cpu6 0.859423 # miss rate for demand accesses
system.cpu6.l1c.demand_miss_rate::total 0.859423 # miss rate for demand accesses
system.cpu6.l1c.overall_miss_rate::cpu6 0.859423 # miss rate for overall accesses
system.cpu6.l1c.overall_miss_rate::total 0.859423 # miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26312.345840 # average ReadReq miss latency
system.cpu6.l1c.ReadReq_avg_miss_latency::total 26312.345840 # average ReadReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 37286.541021 # average WriteReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::total 37286.541021 # average WriteReq miss latency
system.cpu6.l1c.demand_avg_miss_latency::cpu6 30617.601447 # average overall miss latency
system.cpu6.l1c.demand_avg_miss_latency::total 30617.601447 # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::cpu6 30617.601447 # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::total 30617.601447 # average overall miss latency
system.cpu6.l1c.blocked_cycles::no_mshrs 1031115 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu6.l1c.blocked::no_mshrs 63035 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu6.l1c.avg_blocked_cycles::no_mshrs 16.357817 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu6.l1c.writebacks::writebacks 9778 # number of writebacks
system.cpu6.l1c.writebacks::total 9778 # number of writebacks
system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36780 # number of ReadReq MSHR misses
system.cpu6.l1c.ReadReq_mshr_misses::total 36780 # number of ReadReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23744 # number of WriteReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::total 23744 # number of WriteReq MSHR misses
system.cpu6.l1c.demand_mshr_misses::cpu6 60524 # number of demand (read+write) MSHR misses
system.cpu6.l1c.demand_mshr_misses::total 60524 # number of demand (read+write) MSHR misses
system.cpu6.l1c.overall_mshr_misses::cpu6 60524 # number of overall MSHR misses
system.cpu6.l1c.overall_mshr_misses::total 60524 # number of overall MSHR misses
system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 889223312 # number of ReadReq MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_miss_latency::total 889223312 # number of ReadReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 835020954 # number of WriteReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::total 835020954 # number of WriteReq MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1724244266 # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::total 1724244266 # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1724244266 # number of overall MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::total 1724244266 # number of overall MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 698387416 # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 698387416 # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1741021536 # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1741021536 # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2439408952 # number of overall MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2439408952 # number of overall MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807713 # mshr miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807713 # mshr miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954034 # mshr miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954034 # mshr miss rate for WriteReq accesses
system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859423 # mshr miss rate for demand accesses
system.cpu6.l1c.demand_mshr_miss_rate::total 0.859423 # mshr miss rate for demand accesses
system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859423 # mshr miss rate for overall accesses
system.cpu6.l1c.overall_mshr_miss_rate::total 0.859423 # mshr miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 24176.816531 # average ReadReq mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 24176.816531 # average ReadReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 35167.661472 # average WriteReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 35167.661472 # average WriteReq mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 28488.603959 # average overall mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::total 28488.603959 # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 28488.603959 # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::total 28488.603959 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu7.num_reads 99455 # number of read accesses completed
system.cpu7.num_writes 55321 # number of write accesses completed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu7.num_copies 0 # number of copy accesses completed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu7.l1c.tags.replacements 22276 # number of replacements
system.cpu7.l1c.tags.tagsinuse 392.282274 # Cycle average of tags in use
system.cpu7.l1c.tags.total_refs 13267 # Total number of references to valid blocks.
system.cpu7.l1c.tags.sampled_refs 22648 # Sample count of references to valid blocks.
system.cpu7.l1c.tags.avg_refs 0.585791 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu7.l1c.tags.occ_blocks::cpu7 392.282274 # Average occupied blocks per requestor
system.cpu7.l1c.tags.occ_percent::cpu7 0.766176 # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_percent::total 0.766176 # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_task_id_blocks::1024 372 # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::0 356 # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id
system.cpu7.l1c.tags.occ_task_id_percent::1024 0.726562 # Percentage of cache occupancy per task id
system.cpu7.l1c.tags.tag_accesses 337172 # Number of tag accesses
system.cpu7.l1c.tags.data_accesses 337172 # Number of data accesses
system.cpu7.l1c.ReadReq_hits::cpu7 8517 # number of ReadReq hits
system.cpu7.l1c.ReadReq_hits::total 8517 # number of ReadReq hits
system.cpu7.l1c.WriteReq_hits::cpu7 1168 # number of WriteReq hits
system.cpu7.l1c.WriteReq_hits::total 1168 # number of WriteReq hits
system.cpu7.l1c.demand_hits::cpu7 9685 # number of demand (read+write) hits
system.cpu7.l1c.demand_hits::total 9685 # number of demand (read+write) hits
system.cpu7.l1c.overall_hits::cpu7 9685 # number of overall hits
system.cpu7.l1c.overall_hits::total 9685 # number of overall hits
system.cpu7.l1c.ReadReq_misses::cpu7 36632 # number of ReadReq misses
system.cpu7.l1c.ReadReq_misses::total 36632 # number of ReadReq misses
system.cpu7.l1c.WriteReq_misses::cpu7 23782 # number of WriteReq misses
system.cpu7.l1c.WriteReq_misses::total 23782 # number of WriteReq misses
system.cpu7.l1c.demand_misses::cpu7 60414 # number of demand (read+write) misses
system.cpu7.l1c.demand_misses::total 60414 # number of demand (read+write) misses
system.cpu7.l1c.overall_misses::cpu7 60414 # number of overall misses
system.cpu7.l1c.overall_misses::total 60414 # number of overall misses
system.cpu7.l1c.ReadReq_miss_latency::cpu7 969238606 # number of ReadReq miss cycles
system.cpu7.l1c.ReadReq_miss_latency::total 969238606 # number of ReadReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::cpu7 880763834 # number of WriteReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::total 880763834 # number of WriteReq miss cycles
system.cpu7.l1c.demand_miss_latency::cpu7 1850002440 # number of demand (read+write) miss cycles
system.cpu7.l1c.demand_miss_latency::total 1850002440 # number of demand (read+write) miss cycles
system.cpu7.l1c.overall_miss_latency::cpu7 1850002440 # number of overall miss cycles
system.cpu7.l1c.overall_miss_latency::total 1850002440 # number of overall miss cycles
system.cpu7.l1c.ReadReq_accesses::cpu7 45149 # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.ReadReq_accesses::total 45149 # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::cpu7 24950 # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::total 24950 # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.demand_accesses::cpu7 70099 # number of demand (read+write) accesses
system.cpu7.l1c.demand_accesses::total 70099 # number of demand (read+write) accesses
system.cpu7.l1c.overall_accesses::cpu7 70099 # number of overall (read+write) accesses
system.cpu7.l1c.overall_accesses::total 70099 # number of overall (read+write) accesses
system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.811358 # miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_miss_rate::total 0.811358 # miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953186 # miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_miss_rate::total 0.953186 # miss rate for WriteReq accesses
system.cpu7.l1c.demand_miss_rate::cpu7 0.861838 # miss rate for demand accesses
system.cpu7.l1c.demand_miss_rate::total 0.861838 # miss rate for demand accesses
system.cpu7.l1c.overall_miss_rate::cpu7 0.861838 # miss rate for overall accesses
system.cpu7.l1c.overall_miss_rate::total 0.861838 # miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 26458.795752 # average ReadReq miss latency
system.cpu7.l1c.ReadReq_avg_miss_latency::total 26458.795752 # average ReadReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37034.893365 # average WriteReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::total 37034.893365 # average WriteReq miss latency
system.cpu7.l1c.demand_avg_miss_latency::cpu7 30622.081637 # average overall miss latency
system.cpu7.l1c.demand_avg_miss_latency::total 30622.081637 # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::cpu7 30622.081637 # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::total 30622.081637 # average overall miss latency
system.cpu7.l1c.blocked_cycles::no_mshrs 1029627 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu7.l1c.blocked::no_mshrs 62765 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu7.l1c.avg_blocked_cycles::no_mshrs 16.404477 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu7.l1c.writebacks::writebacks 9888 # number of writebacks
system.cpu7.l1c.writebacks::total 9888 # number of writebacks
system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36632 # number of ReadReq MSHR misses
system.cpu7.l1c.ReadReq_mshr_misses::total 36632 # number of ReadReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23782 # number of WriteReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::total 23782 # number of WriteReq MSHR misses
system.cpu7.l1c.demand_mshr_misses::cpu7 60414 # number of demand (read+write) MSHR misses
system.cpu7.l1c.demand_mshr_misses::total 60414 # number of demand (read+write) MSHR misses
system.cpu7.l1c.overall_mshr_misses::cpu7 60414 # number of overall MSHR misses
system.cpu7.l1c.overall_mshr_misses::total 60414 # number of overall MSHR misses
system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 891054702 # number of ReadReq MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_miss_latency::total 891054702 # number of ReadReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 830452960 # number of WriteReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::total 830452960 # number of WriteReq MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1721507662 # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::total 1721507662 # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1721507662 # number of overall MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::total 1721507662 # number of overall MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 698299057 # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 698299057 # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1725454906 # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1725454906 # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2423753963 # number of overall MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2423753963 # number of overall MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.811358 # mshr miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.811358 # mshr miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953186 # mshr miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953186 # mshr miss rate for WriteReq accesses
system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.861838 # mshr miss rate for demand accesses
system.cpu7.l1c.demand_mshr_miss_rate::total 0.861838 # mshr miss rate for demand accesses
system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.861838 # mshr miss rate for overall accesses
system.cpu7.l1c.overall_mshr_miss_rate::total 0.861838 # mshr miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 24324.489572 # average ReadReq mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 24324.489572 # average ReadReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 34919.391136 # average WriteReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 34919.391136 # average WriteReq mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 28495.177641 # average overall mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::total 28495.177641 # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 28495.177641 # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::total 28495.177641 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
Add short memtest run to quick regressions. Caveats: - Even though memtest is ISA-independent, it will only run for the Alpha builds, since there's no way to specify ISA-independent reference files and I didn't want to commit 3 copies since I'm not sure we want to run it for all the different ISAs anyway. - Reference outputs were generated on my laptop, so performance numbers will be low compared to zizzer. --HG-- extra : convert_revision : 210fe4abecc19fbab0b15402c6cb4863650bab66
2007-02-07 06:16:33 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink