2010-07-27 07:03:44 +02:00
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---------- Begin Simulation Statistics ----------
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2012-10-15 14:09:54 +02:00
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sim_seconds 0.232072 # Number of seconds simulated
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sim_ticks 232072304000 # Number of ticks simulated
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final_tick 232072304000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2012-01-25 18:19:50 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2012-10-15 14:09:54 +02:00
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host_inst_rate 603492 # Simulator instruction rate (inst/s)
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host_op_rate 660888 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 815011792 # Simulator tick rate (ticks/s)
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host_mem_usage 237088 # Number of bytes of host memory used
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host_seconds 284.75 # Real time elapsed on the host
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2012-06-29 17:19:03 +02:00
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sim_insts 171842483 # Number of instructions simulated
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sim_ops 188185920 # Number of ops (including micro ops) simulated
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2012-06-05 07:23:16 +02:00
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system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory
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system.physmem.bytes_read::total 220992 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 110656 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 110656 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory
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2012-10-15 14:09:54 +02:00
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system.physmem.bw_read::cpu.inst 476817 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 475438 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 952255 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 476817 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 476817 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 476817 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 475438 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 952255 # Total bandwidth to/from this memory (bytes/s)
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2010-11-08 20:59:35 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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2010-07-27 07:03:44 +02:00
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2012-01-25 18:19:50 +01:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 400 # Number of system calls
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2012-10-15 14:09:54 +02:00
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system.cpu.numCycles 464144608 # number of cpu cycles simulated
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2012-01-25 18:19:50 +01:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2012-06-29 17:19:03 +02:00
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system.cpu.committedInsts 171842483 # Number of instructions committed
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system.cpu.committedOps 188185920 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 150106218 # Number of integer alu accesses
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2012-01-25 18:19:50 +01:00
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system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
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2012-06-29 17:19:03 +02:00
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system.cpu.num_func_calls 3545028 # number of times a function call or return occured
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2012-09-25 18:49:41 +02:00
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system.cpu.num_conditional_control_insts 32494341 # number of instructions that are conditional controls
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2012-06-29 17:19:03 +02:00
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system.cpu.num_int_insts 150106218 # number of integer instructions
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2012-01-25 18:19:50 +01:00
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system.cpu.num_fp_insts 1752310 # number of float instructions
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2012-06-29 17:19:03 +02:00
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system.cpu.num_int_register_reads 898652246 # number of times the integer registers were read
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system.cpu.num_int_register_writes 294073517 # number of times the integer registers were written
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2012-01-25 18:19:50 +01:00
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system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
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2012-06-29 17:19:03 +02:00
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system.cpu.num_mem_refs 42494119 # number of memory refs
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system.cpu.num_load_insts 29849484 # Number of load instructions
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2012-01-25 18:19:50 +01:00
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system.cpu.num_store_insts 12644635 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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2012-10-15 14:09:54 +02:00
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system.cpu.num_busy_cycles 464144608 # Number of busy cycles
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2012-01-25 18:19:50 +01:00
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 1506 # number of replacements
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2012-10-15 14:09:54 +02:00
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system.cpu.icache.tagsinuse 1147.986161 # Cycle average of tags in use
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2012-06-29 17:19:03 +02:00
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system.cpu.icache.total_refs 189857001 # Total number of references to valid blocks.
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2012-01-25 18:19:50 +01:00
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system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks.
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2012-06-29 17:19:03 +02:00
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system.cpu.icache.avg_refs 62227.794494 # Average number of references to valid blocks.
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2012-01-25 18:19:50 +01:00
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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2012-10-15 14:09:54 +02:00
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system.cpu.icache.occ_blocks::cpu.inst 1147.986161 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.560540 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.560540 # Average percentage of cache occupancy
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2012-06-29 17:19:03 +02:00
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system.cpu.icache.ReadReq_hits::cpu.inst 189857001 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 189857001 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 189857001 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 189857001 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 189857001 # number of overall hits
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system.cpu.icache.overall_hits::total 189857001 # number of overall hits
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2012-02-12 23:07:43 +01:00
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system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 3051 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 3051 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses
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system.cpu.icache.overall_misses::total 3051 # number of overall misses
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2012-10-15 14:09:54 +02:00
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 112281000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 112281000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 112281000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 112281000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 112281000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 112281000 # number of overall miss cycles
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2012-06-29 17:19:03 +02:00
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system.cpu.icache.ReadReq_accesses::cpu.inst 189860052 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 189860052 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 189860052 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 189860052 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 189860052 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 189860052 # number of overall (read+write) accesses
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2012-02-12 23:07:43 +01:00
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses
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2012-06-05 07:23:16 +02:00
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system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
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2012-02-12 23:07:43 +01:00
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system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses
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2012-06-05 07:23:16 +02:00
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system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
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2012-02-12 23:07:43 +01:00
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
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2012-06-05 07:23:16 +02:00
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system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses
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2012-10-15 14:09:54 +02:00
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36801.376598 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 36801.376598 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 36801.376598 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 36801.376598 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 36801.376598 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 36801.376598 # average overall miss latency
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2010-07-27 07:03:44 +02:00
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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2012-01-25 18:19:50 +01:00
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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2012-05-09 20:52:14 +02:00
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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2012-01-25 18:19:50 +01:00
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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2010-07-27 07:03:44 +02:00
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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2012-02-12 23:07:43 +01:00
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3051 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 3051 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 3051 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 106179000 # number of ReadReq MSHR miss cycles
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|
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system.cpu.icache.ReadReq_mshr_miss_latency::total 106179000 # number of ReadReq MSHR miss cycles
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|
|
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 106179000 # number of demand (read+write) MSHR miss cycles
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|
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|
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system.cpu.icache.demand_mshr_miss_latency::total 106179000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 106179000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 106179000 # number of overall MSHR miss cycles
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|
|
|
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses
|
2012-06-05 07:23:16 +02:00
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|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses
|
2012-02-12 23:07:43 +01:00
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|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34801.376598 # average ReadReq mshr miss latency
|
2012-06-05 07:23:16 +02:00
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|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34801.376598 # average ReadReq mshr miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency
|
2012-06-05 07:23:16 +02:00
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|
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system.cpu.icache.demand_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency
|
2012-02-12 23:07:43 +01:00
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|
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency
|
2012-06-05 07:23:16 +02:00
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|
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system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency
|
2012-01-25 18:19:50 +01:00
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|
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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|
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system.cpu.dcache.replacements 40 # number of replacements
|
2012-10-15 14:09:54 +02:00
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|
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system.cpu.dcache.tagsinuse 1363.611259 # Cycle average of tags in use
|
2012-06-29 17:19:03 +02:00
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|
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system.cpu.dcache.total_refs 42007358 # Total number of references to valid blocks.
|
2012-01-25 18:19:50 +01:00
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|
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system.cpu.dcache.sampled_refs 1789 # Sample count of references to valid blocks.
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2012-06-29 17:19:03 +02:00
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|
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system.cpu.dcache.avg_refs 23480.915595 # Average number of references to valid blocks.
|
2012-01-25 18:19:50 +01:00
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|
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-10-15 14:09:54 +02:00
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|
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system.cpu.dcache.occ_blocks::cpu.data 1363.611259 # Average occupied blocks per requestor
|
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system.cpu.dcache.occ_percent::cpu.data 0.332913 # Average percentage of cache occupancy
|
|
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system.cpu.dcache.occ_percent::total 0.332913 # Average percentage of cache occupancy
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 29599357 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 29599357 # number of ReadReq hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.dcache.demand_hits::cpu.data 41962544 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 41962544 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 41962544 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 41962544 # number of overall hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 689 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 689 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses::cpu.data 1789 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 1789 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 1789 # number of overall misses
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 35501000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 35501000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 60164000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 60164000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 95665000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 95665000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 95665000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 95665000 # number of overall miss cycles
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 29600046 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 29600046 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 41964333 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 41964333 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 41964333 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 41964333 # number of overall (read+write) accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51525.399129 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 51525.399129 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54694.545455 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 54694.545455 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 53474.007826 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::total 53474.007826 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 53474.007826 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::total 53474.007826 # average overall miss latency
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 16 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 689 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 689 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1789 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 1789 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34123000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 34123000 # number of ReadReq MSHR miss cycles
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57964000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 57964000 # number of WriteReq MSHR miss cycles
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 92087000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92087000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 92087000 # number of overall MSHR miss cycles
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for demand accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for overall accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49525.399129 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49525.399129 # average ReadReq mshr miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52694.545455 # average WriteReq mshr miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52694.545455 # average WriteReq mshr miss latency
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 1675.655740 # Cycle average of tags in use
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.l2cache.total_refs 1380 # Total number of references to valid blocks.
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.l2cache.sampled_refs 2369 # Sample count of references to valid blocks.
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.l2cache.avg_refs 0.582524 # Average number of references to valid blocks.
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::writebacks 3.038044 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 1169.032828 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.data 503.584868 # Average occupied blocks per requestor
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.occ_percent::total 0.051137 # Average percentage of cache occupancy
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 1322 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 57 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 1379 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1322 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 65 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 1387 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1322 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 65 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 1387 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 1729 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 632 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 2361 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 1092 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 1092 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 1729 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 1724 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 3453 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 3453 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 89908000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32864000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 122772000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56784000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 56784000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 89908000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 89648000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 179556000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 89908000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 89648000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 179556000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3051 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 689 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 3740 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1100 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1100 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 3051 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1789 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 4840 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 3051 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1789 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 4840 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.566699 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.917271 # miss rate for ReadReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.631283 # miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992727 # miss rate for ReadExReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.992727 # miss rate for ReadExReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.566699 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.963667 # miss rate for demand accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.demand_miss_rate::total 0.713430 # miss rate for demand accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1729 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 632 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 2361 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1092 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 1092 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1729 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 1724 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 3453 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 69160000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25280000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94440000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43680000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43680000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 69160000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68960000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 138120000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 69160000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68960000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 138120000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.631283 # mshr miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 # mshr miss rate for ReadExReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for demand accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 # mshr miss rate for demand accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-07-27 07:03:44 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
