2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
2016-08-12 15:12:59 +02:00
sim_seconds 47.374315 # Number of seconds simulated
sim_ticks 47374315410500 # Number of ticks simulated
final_tick 47374315410500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-08-12 15:12:59 +02:00
host_inst_rate 573964 # Simulator instruction rate (inst/s)
host_op_rate 675116 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 30496109280 # Simulator tick rate (ticks/s)
host_mem_usage 762100 # Number of bytes of host memory used
host_seconds 1553.45 # Real time elapsed on the host
sim_insts 891626325 # Number of instructions simulated
sim_ops 1048762579 # Number of ops (including micro ops) simulated
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-08-12 15:12:59 +02:00
system.physmem.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 107264 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 103104 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 3762996 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 12951880 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 13484096 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 112000 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 117056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 2426936 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 10199632 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 12856576 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 431488 # Number of bytes read from this memory
system.physmem.bytes_read::total 56553028 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 3762996 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 2426936 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 6189932 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 74832448 # Number of bytes written to this memory
2015-05-05 09:22:39 +02:00
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
2014-12-02 12:08:25 +01:00
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
2016-08-12 15:12:59 +02:00
system.physmem.bytes_written::total 74853032 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 1676 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1611 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 99204 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 202386 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 210689 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1750 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1829 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 38009 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 159382 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 200884 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6742 # Number of read requests responded to by this memory
system.physmem.num_reads::total 924162 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1169257 # Number of write requests responded to by this memory
2015-05-05 09:22:39 +02:00
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
2014-12-02 12:08:25 +01:00
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
2016-08-12 15:12:59 +02:00
system.physmem.num_writes::total 1171831 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 2264 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 2176 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 79431 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 273395 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 284629 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 2364 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 2471 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 51229 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 215299 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 271383 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 9108 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1193749 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 79431 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 51229 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 130660 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1579600 # Write bandwidth from this memory (bytes/s)
2016-07-21 18:19:18 +02:00
system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
2014-12-02 12:08:25 +01:00
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
2016-08-12 15:12:59 +02:00
system.physmem.bw_write::total 1580034 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1579600 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 2264 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 2176 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 79431 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 273829 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 284629 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 2364 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 2471 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 51229 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 215299 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 271383 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 9108 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2773783 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 924162 # Number of read requests accepted
system.physmem.writeReqs 1171831 # Number of write requests accepted
system.physmem.readBursts 924162 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1171831 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 59123712 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 22656 # Total number of bytes read from write queue
system.physmem.bytesWritten 74852544 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 56553028 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 74853032 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 354 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-08-12 15:12:59 +02:00
system.physmem.perBankRdBursts::0 54791 # Per bank write bursts
system.physmem.perBankRdBursts::1 60963 # Per bank write bursts
system.physmem.perBankRdBursts::2 51680 # Per bank write bursts
system.physmem.perBankRdBursts::3 61600 # Per bank write bursts
system.physmem.perBankRdBursts::4 56399 # Per bank write bursts
system.physmem.perBankRdBursts::5 67623 # Per bank write bursts
system.physmem.perBankRdBursts::6 62592 # Per bank write bursts
system.physmem.perBankRdBursts::7 58195 # Per bank write bursts
system.physmem.perBankRdBursts::8 51047 # Per bank write bursts
system.physmem.perBankRdBursts::9 95684 # Per bank write bursts
system.physmem.perBankRdBursts::10 47816 # Per bank write bursts
system.physmem.perBankRdBursts::11 53141 # Per bank write bursts
system.physmem.perBankRdBursts::12 48535 # Per bank write bursts
system.physmem.perBankRdBursts::13 54663 # Per bank write bursts
system.physmem.perBankRdBursts::14 49130 # Per bank write bursts
system.physmem.perBankRdBursts::15 49949 # Per bank write bursts
system.physmem.perBankWrBursts::0 71660 # Per bank write bursts
system.physmem.perBankWrBursts::1 78743 # Per bank write bursts
system.physmem.perBankWrBursts::2 71851 # Per bank write bursts
system.physmem.perBankWrBursts::3 78616 # Per bank write bursts
system.physmem.perBankWrBursts::4 73485 # Per bank write bursts
system.physmem.perBankWrBursts::5 81529 # Per bank write bursts
system.physmem.perBankWrBursts::6 75635 # Per bank write bursts
system.physmem.perBankWrBursts::7 74455 # Per bank write bursts
system.physmem.perBankWrBursts::8 70456 # Per bank write bursts
system.physmem.perBankWrBursts::9 72917 # Per bank write bursts
system.physmem.perBankWrBursts::10 67611 # Per bank write bursts
system.physmem.perBankWrBursts::11 70918 # Per bank write bursts
system.physmem.perBankWrBursts::12 67621 # Per bank write bursts
system.physmem.perBankWrBursts::13 71486 # Per bank write bursts
system.physmem.perBankWrBursts::14 70570 # Per bank write bursts
system.physmem.perBankWrBursts::15 72018 # Per bank write bursts
2014-10-30 05:50:15 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2016-08-12 15:12:59 +02:00
system.physmem.numWrRetry 85 # Number of times write queue was full causing retry
system.physmem.totGap 47374312061000 # Total gap between requests
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 43195 # Read request sizes (log2)
2015-05-05 09:22:39 +02:00
system.physmem.readPktSize::3 25 # Read request sizes (log2)
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::4 5 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-08-12 15:12:59 +02:00
system.physmem.readPktSize::6 880937 # Read request sizes (log2)
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
2015-05-05 09:22:39 +02:00
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2016-08-12 15:12:59 +02:00
system.physmem.writePktSize::6 1169257 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 656925 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 77551 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 38628 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 33370 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 28745 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 25204 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 22090 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 18063 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 15811 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 2611 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1283 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 912 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 744 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 565 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 402 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 317 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 250 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 187 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 88 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see
2016-05-31 12:07:18 +02:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
2014-12-23 15:31:20 +01:00
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
2014-10-30 05:50:15 +01:00
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2016-08-12 15:12:59 +02:00
system.physmem.wrQLenPdf::15 29578 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 37673 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 49096 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 55472 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 61395 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 64054 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 66659 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 68456 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 71033 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 71567 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 75072 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 77359 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 72847 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 72784 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 77929 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 71715 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 66943 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 64345 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 2561 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 1786 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 1329 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 960 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 633 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 524 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 522 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 378 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 453 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 384 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 332 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 426 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 345 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 416 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 315 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 285 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 313 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 294 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 291 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 299 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 349 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 308 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 309 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 289 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 258 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 252 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 237 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 201 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 141 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 145 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 259 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 927168 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 144.500035 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 98.409552 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 191.008164 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 615708 66.41% 66.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 189300 20.42% 86.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 44500 4.80% 91.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 20695 2.23% 93.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 14869 1.60% 95.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 9173 0.99% 96.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 6380 0.69% 97.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 5518 0.60% 97.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 21025 2.27% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 927168 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 60983 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 15.148533 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 130.608088 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 60979 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes
2016-02-24 10:16:59 +01:00
system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
2016-08-12 15:12:59 +02:00
system.physmem.rdPerTurnAround::total 60983 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 60983 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 19.178640 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.436589 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 7.785486 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 49393 80.99% 80.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 4571 7.50% 88.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 2800 4.59% 93.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 1776 2.91% 95.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 1006 1.65% 97.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 308 0.51% 98.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 149 0.24% 98.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 125 0.20% 98.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 64 0.10% 98.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 38 0.06% 98.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 29 0.05% 98.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 41 0.07% 98.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 435 0.71% 99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 54 0.09% 99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 52 0.09% 99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 40 0.07% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 33 0.05% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 5 0.01% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 3 0.00% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 1 0.00% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 5 0.01% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 2 0.00% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 5 0.01% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 3 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 14 0.02% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 3 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 3 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 4 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 9 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175 2 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 60983 # Writes before turning the bus around for reads
system.physmem.totQLat 30413749694 # Total ticks spent queuing
system.physmem.totMemAccLat 47735149694 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 4619040000 # Total ticks spent in databus transfers
system.physmem.avgQLat 32922.15 # Average queueing delay per DRAM burst
2014-10-30 05:50:15 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-08-12 15:12:59 +02:00
system.physmem.avgMemAccLat 51672.15 # Average memory access latency per DRAM burst
2016-05-31 12:07:18 +02:00
system.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s
2016-08-12 15:12:59 +02:00
system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s
2016-05-31 12:07:18 +02:00
system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s
2016-08-12 15:12:59 +02:00
system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s
2014-10-30 05:50:15 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2016-03-16 21:03:49 +01:00
system.physmem.busUtil 0.02 # Data bus utilization in percentage
2015-11-06 09:26:50 +01:00
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
2015-07-03 16:15:03 +02:00
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
2016-08-12 15:12:59 +02:00
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.27 # Average write queue length when enqueuing
system.physmem.readRowHits 683627 # Number of row buffer hits during reads
system.physmem.writeRowHits 482581 # Number of row buffer hits during writes
system.physmem.readRowHitRate 74.00 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 41.26 # Row buffer hit rate for writes
system.physmem.avgGap 22602323.61 # Average gap between requests
system.physmem.pageHitRate 55.71 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 3700302480 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 2019014250 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 3695975400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 3926705040 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3094259578800 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1192499073090 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 27378533808750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 31678634457810 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.688048 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 45546210437205 # Time in different power states
system.physmem_0.memoryStateTime::REF 1581932300000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-08-12 15:12:59 +02:00
system.physmem_0.memoryStateTime::ACT 246167130795 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-08-12 15:12:59 +02:00
system.physmem_1.actEnergy 3308936400 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1805471250 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 3509181000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 3651784560 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3094259578800 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1178425765395 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 27390878815500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 31675839532905 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.629051 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 45566794873385 # Time in different power states
system.physmem_1.memoryStateTime::REF 1581932300000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-08-12 15:12:59 +02:00
system.physmem_1.memoryStateTime::ACT 225582219115 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-08-12 15:12:59 +02:00
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
2016-08-12 15:12:59 +02:00
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
2014-10-30 05:50:15 +01:00
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
2016-08-12 15:12:59 +02:00
system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1674 # Number of DMA write transactions.
2014-11-12 15:05:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2016-08-12 15:12:59 +02:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 101108 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 101108 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9051 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76906 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 101094 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 101094 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 101094 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 85971 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 24170.842493 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 22339.898543 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 14600.032387 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-32767 76182 88.61% 88.61% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-65535 8727 10.15% 98.76% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-98303 200 0.23% 99.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-131071 718 0.84% 99.83% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-163839 29 0.03% 99.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::163840-196607 15 0.02% 99.88% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-229375 34 0.04% 99.92% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::229376-262143 15 0.02% 99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-294911 12 0.01% 99.95% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::294912-327679 19 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-360447 11 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
2016-07-21 18:19:18 +02:00
system.cpu0.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.walker.walkCompletionTime::total 85971 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples -250064880 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.334382 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.471774 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 -166447796 66.56% 66.56% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1 -83617084 33.44% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total -250064880 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 76906 89.47% 89.47% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 9051 10.53% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 85957 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 101108 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 101108 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85957 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85957 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 187065 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.read_hits 84046306 # DTB read hits
system.cpu0.dtb.read_misses 73432 # DTB read misses
system.cpu0.dtb.write_hits 77237834 # DTB write hits
system.cpu0.dtb.write_misses 27676 # DTB write misses
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 35922 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.prefetch_faults 4635 # Number of TLB faults due to prefetch
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.perms_faults 9711 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 84119738 # DTB read accesses
system.cpu0.dtb.write_accesses 77265510 # DTB write accesses
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.hits 161284140 # DTB hits
system.cpu0.dtb.misses 101108 # DTB misses
system.cpu0.dtb.accesses 161385248 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-08-12 15:12:59 +02:00
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 58460 # Table walker walks requested
system.cpu0.itb.walker.walksLong 58460 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 540 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52669 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples 58460 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 58460 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 58460 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 53209 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 26190.982728 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 24044.890366 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 17871.734437 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-32767 47169 88.65% 88.65% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-65535 4943 9.29% 97.94% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-98303 65 0.12% 98.06% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::98304-131071 859 1.61% 99.67% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-163839 39 0.07% 99.75% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::163840-196607 17 0.03% 99.78% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-229375 47 0.09% 99.87% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::229376-262143 13 0.02% 99.89% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-294911 25 0.05% 99.94% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::294912-327679 20 0.04% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 53209 # Table walker service (enqueue to completion) latency
2016-05-31 12:07:18 +02:00
system.cpu0.itb.walker.walksPending::samples -282313796 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 -282313796 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total -282313796 # Table walker pending requests distribution
2016-08-12 15:12:59 +02:00
system.cpu0.itb.walker.walkPageSizes::4K 52669 98.99% 98.99% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 540 1.01% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 53209 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 58460 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 58460 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 53209 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 53209 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 111669 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 449335815 # ITB inst hits
system.cpu0.itb.inst_misses 58460 # ITB inst misses
2014-10-30 05:50:15 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-08-12 15:12:59 +02:00
system.cpu0.itb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 24946 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
2016-08-12 15:12:59 +02:00
system.cpu0.itb.inst_accesses 449394275 # ITB inst accesses
system.cpu0.itb.hits 449335815 # DTB hits
system.cpu0.itb.misses 58460 # DTB misses
system.cpu0.itb.accesses 449394275 # DTB accesses
system.cpu0.numPwrStateTransitions 8624 # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples 4312 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean 10857440365.954313 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev 156382311444.961365 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows 3059 70.94% 70.94% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10 1229 28.50% 99.44% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 2 0.05% 99.49% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.05% 99.54% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.05% 99.58% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 1 0.02% 99.61% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.63% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.65% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.68% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::overflows 14 0.32% 100.00% # Distribution of time spent in the clock gated state
2016-07-21 18:19:18 +02:00
system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
2016-08-12 15:12:59 +02:00
system.cpu0.pwrStateClkGateDist::max_value 7470353528320 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total 4312 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON 557032552505 # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 46817282857995 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 94748630821 # number of cpu cycles simulated
2014-10-30 05:50:15 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-10-10 23:45:41 +02:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
2016-08-12 15:12:59 +02:00
system.cpu0.kern.inst.quiesce 4312 # number of quiesce instructions executed
system.cpu0.committedInsts 449083110 # Number of instructions committed
system.cpu0.committedOps 528384419 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 485390643 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 507449 # Number of float alu accesses
system.cpu0.num_func_calls 26866500 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 68160489 # number of instructions that are conditional controls
system.cpu0.num_int_insts 485390643 # number of integer instructions
system.cpu0.num_fp_insts 507449 # number of float instructions
system.cpu0.num_int_register_reads 703891240 # number of times the integer registers were read
system.cpu0.num_int_register_writes 384865941 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 816779 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 435492 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 117650799 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 117386896 # number of times the CC registers were written
system.cpu0.num_mem_refs 161276211 # number of memory refs
system.cpu0.num_load_insts 84042257 # Number of load instructions
system.cpu0.num_store_insts 77233954 # Number of store instructions
system.cpu0.num_idle_cycles 93634565715.988022 # Number of idle cycles
system.cpu0.num_busy_cycles 1114065105.011976 # Number of busy cycles
system.cpu0.not_idle_fraction 0.011758 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.988242 # Percentage of idle cycles
system.cpu0.Branches 100200450 # Number of branches fetched
system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu 366086093 69.25% 69.25% # Class of executed instruction
system.cpu0.op_class::IntMult 1185979 0.22% 69.47% # Class of executed instruction
system.cpu0.op_class::IntDiv 59083 0.01% 69.48% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 72839 0.01% 69.49% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::MemRead 84042257 15.90% 85.39% # Class of executed instruction
system.cpu0.op_class::MemWrite 77233954 14.61% 100.00% # Class of executed instruction
2014-10-30 05:50:15 +01:00
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
2016-08-12 15:12:59 +02:00
system.cpu0.op_class::total 528680248 # Class of executed instruction
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 5566798 # number of replacements
system.cpu0.dcache.tags.tagsinuse 502.671926 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 155470196 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 5567308 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 27.925560 # Average number of references to valid blocks.
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.tags.warmup_cycle 4031081000 # Cycle when the warmup percentage was hit.
2016-08-12 15:12:59 +02:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.671926 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.981781 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.981781 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 419 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 328131694 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 328131694 # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 78275725 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 78275725 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 72837974 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 72837974 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200143 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 200143 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 232092 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 232092 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1764306 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 1764306 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1721538 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 1721538 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 151345791 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 151345791 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 151545934 # number of overall hits
system.cpu0.dcache.overall_hits::total 151545934 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 2974115 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 2974115 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1412109 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1412109 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 649854 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 649854 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 801670 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 801670 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 161158 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 161158 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 202775 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 202775 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 5187894 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 5187894 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 5837748 # number of overall misses
system.cpu0.dcache.overall_misses::total 5837748 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 44497648000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 44497648000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 28844482000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 28844482000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25694293000 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 25694293000 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2462602000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 2462602000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4821620000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 4821620000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2416000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2416000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 99036423000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 99036423000 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 99036423000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 99036423000 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 81249840 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 81249840 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 74250083 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 74250083 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 849997 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 849997 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1033762 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 1033762 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1925464 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 1925464 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1924313 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 1924313 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 156533685 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 156533685 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 157383682 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 157383682 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036605 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.036605 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019018 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.019018 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.764537 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.764537 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.775488 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.775488 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083698 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083698 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.105375 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.105375 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033142 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.033142 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037092 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.037092 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14961.643380 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14961.643380 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20426.526564 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 20426.526564 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32050.959871 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32050.959871 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15280.668661 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15280.668661 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23778.177783 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23778.177783 # average StoreCondReq miss latency
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2016-08-12 15:12:59 +02:00
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19089.908738 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 19089.908738 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16964.833528 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 16964.833528 # average overall miss latency
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu0.dcache.writebacks::writebacks 5566798 # number of writebacks
system.cpu0.dcache.writebacks::total 5566798 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 29633 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 29633 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21518 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 21518 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 45711 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 45711 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 51151 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 51151 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 51151 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 51151 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2944482 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 2944482 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1390591 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 1390591 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 648168 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 648168 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 801670 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 801670 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 115447 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 115447 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 202775 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 202775 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 5136743 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 5136743 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 5784911 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 5784911 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 21025 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 21025 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 22388 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 22388 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 43413 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 43413 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 40085054500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 40085054500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 26946583500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 26946583500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14957704500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14957704500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24892623000 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24892623000 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1575244000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1575244000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4618898000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4618898000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2363000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2363000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 91924261000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 91924261000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 106881965500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 106881965500 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3989550000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3989550000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3989550000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3989550000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036240 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036240 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018728 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018728 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.762553 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.762553 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.775488 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.775488 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059958 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059958 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.105375 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.105375 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032816 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.032816 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036757 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.036757 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13613.618456 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13613.618456 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19377.792248 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19377.792248 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23076.894416 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23076.894416 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31050.959871 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31050.959871 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13644.737412 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13644.737412 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22778.439157 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22778.439157 # average StoreCondReq mshr miss latency
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2016-08-12 15:12:59 +02:00
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17895.437050 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17895.437050 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18475.991333 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18475.991333 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189752.675386 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189752.675386 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 91897.588280 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 91897.588280 # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 5174135 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.907744 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 444161163 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 5174647 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 85.834099 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 30089682000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.907744 # Average occupied blocks per requestor
2016-07-21 18:19:18 +02:00
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999820 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999820 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 186 # Occupied blocks per task id
2014-10-30 05:50:15 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-08-12 15:12:59 +02:00
system.cpu0.icache.tags.tag_accesses 903846282 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 903846282 # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 444161163 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 444161163 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 444161163 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 444161163 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 444161163 # number of overall hits
system.cpu0.icache.overall_hits::total 444161163 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 5174652 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 5174652 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 5174652 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 5174652 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 5174652 # number of overall misses
system.cpu0.icache.overall_misses::total 5174652 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 55704586500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 55704586500 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 55704586500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 55704586500 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 55704586500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 55704586500 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 449335815 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 449335815 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 449335815 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 449335815 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 449335815 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 449335815 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011516 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.011516 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011516 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.011516 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011516 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.011516 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10764.895205 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10764.895205 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10764.895205 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10764.895205 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10764.895205 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10764.895205 # average overall miss latency
2014-10-30 05:50:15 +01:00
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu0.icache.writebacks::writebacks 5174135 # number of writebacks
system.cpu0.icache.writebacks::total 5174135 # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5174652 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 5174652 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 5174652 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 5174652 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 5174652 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 5174652 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses
2016-08-12 15:12:59 +02:00
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 53117260500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 53117260500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 53117260500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 53117260500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 53117260500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 53117260500 # number of overall MSHR miss cycles
2016-05-31 12:07:18 +02:00
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3819470000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 3819470000 # number of overall MSHR uncacheable cycles
2016-08-12 15:12:59 +02:00
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011516 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011516 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011516 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.011516 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011516 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.011516 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10264.895205 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10264.895205 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10264.895205 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10264.895205 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10264.895205 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10264.895205 # average overall mshr miss latency
2016-05-31 12:07:18 +02:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88567.420290 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88567.420290 # average overall mshr uncacheable latency
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued 7568346 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 7568354 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue
2014-12-23 15:31:20 +01:00
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.prefetcher.pfSpanPage 981182 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements 2342884 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 15723.839714 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 9135802 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 2358598 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 3.873404 # Average number of references to valid blocks.
2016-05-31 12:07:18 +02:00
system.cpu0.l2cache.tags.warmup_cycle 5100393500 # Cycle when the warmup percentage was hit.
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.tags.occ_blocks::writebacks 15407.459260 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 38.158261 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 27.135006 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 251.087187 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.940397 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002329 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001656 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.015325 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.959707 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 345 # Occupied blocks per task id
2016-07-21 18:19:18 +02:00
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15297 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 130 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 167 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 29 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 18 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 53 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1333 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5696 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7896 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 254 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.021057 # Percentage of cache occupancy per task id
2016-07-21 18:19:18 +02:00
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004395 # Percentage of cache occupancy per task id
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.933655 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 370311903 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 370311903 # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 225709 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 148168 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 373877 # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks 3696575 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total 3696575 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks 7043197 # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total 7043197 # number of WritebackClean hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 878685 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 878685 # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4695575 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total 4695575 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2752703 # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total 2752703 # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 216682 # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total 216682 # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 225709 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 148168 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 4695575 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 3631388 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 8700840 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 225709 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 148168 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 4695575 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 3631388 # number of overall hits
system.cpu0.l2cache.overall_hits::total 8700840 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 18676 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10607 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 29283 # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 251664 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 251664 # number of UpgradeReq misses
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system.cpu0.l2cache.SCUpgradeReq_misses::total 202763 # number of SCUpgradeReq misses
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system.cpu0.l2cache.SCUpgradeFailReq_misses::total 12 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 278535 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 278535 # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 479077 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total 479077 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 955394 # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total 955394 # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 582714 # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total 582714 # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 18676 # number of demand (read+write) misses
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system.cpu0.l2cache.demand_misses::cpu0.inst 479077 # number of demand (read+write) misses
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system.cpu0.l2cache.demand_misses::total 1742289 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 18676 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10607 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 479077 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 1233929 # number of overall misses
system.cpu0.l2cache.overall_misses::total 1742289 # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 564732000 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 371950000 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total 936682000 # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 916815500 # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total 916815500 # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 321936500 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 321936500 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2282499 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2282499 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12626438998 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total 12626438998 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 17151939500 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total 17151939500 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 33121351500 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total 33121351500 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 399249500 # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total 399249500 # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 564732000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 371950000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 17151939500 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data 45747790498 # number of demand (read+write) miss cycles
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system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 564732000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 371950000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 17151939500 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data 45747790498 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 63836411998 # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 244385 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 158775 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 403160 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3696575 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total 3696575 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks 7043197 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total 7043197 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 251664 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 251664 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 202763 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 202763 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 12 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 12 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1157220 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 1157220 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5174652 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total 5174652 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3708097 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total 3708097 # number of ReadSharedReq accesses(hits+misses)
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system.cpu0.l2cache.InvalidateReq_accesses::total 799396 # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 244385 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 158775 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 5174652 # number of demand (read+write) accesses
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system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 244385 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 158775 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 5174652 # number of overall (read+write) accesses
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system.cpu0.l2cache.overall_accesses::total 10443129 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.076420 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.066805 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.072634 # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.240693 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.240693 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.092581 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.092581 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.257651 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.257651 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.728943 # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.728943 # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.076420 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.066805 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.092581 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.253617 # miss rate for demand accesses
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system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.076420 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.066805 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.092581 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.253617 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.166836 # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 30238.380810 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 35066.465542 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31987.228085 # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3643.014098 # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3643.014098 # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1587.747765 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1587.747765 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 190208.250000 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 190208.250000 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 45331.606434 # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 45331.606434 # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 35802.051653 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 35802.051653 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34667.740744 # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34667.740744 # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 685.155153 # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 685.155153 # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 30238.380810 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 35066.465542 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 35802.051653 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37074.896933 # average overall miss latency
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system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 30238.380810 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 35066.465542 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 35802.051653 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37074.896933 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 36639.393349 # average overall miss latency
2014-12-23 15:31:20 +01:00
system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.unused_prefetches 41508 # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks 1560695 # number of writebacks
system.cpu0.l2cache.writebacks::total 1560695 # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5412 # number of ReadExReq MSHR hits
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system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 417 # number of ReadSharedReq MSHR hits
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system.cpu0.l2cache.ReadReq_mshr_misses::total 29283 # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 726457 # number of HardPFReq MSHR misses
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system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10607 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 479077 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1228100 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 726457 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total 2462917 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 21025 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 64150 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 22388 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 22388 # number of WriteReq MSHR uncacheable
2015-05-05 09:22:39 +02:00
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 43413 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 86538 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 452676000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 308308000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 760984000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 31463015041 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 31463015041 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4662148500 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4662148500 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3097020500 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3097020500 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1964499 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1964499 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10454677998 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10454677998 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 14277477500 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 14277477500 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 27353907000 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 27353907000 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18732640000 # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18732640000 # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 452676000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 308308000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 14277477500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 37808584998 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 52847046498 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 452676000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 308308000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 14277477500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 37808584998 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 31463015041 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 84310061539 # number of overall MSHR miss cycles
2016-05-31 12:07:18 +02:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3496032500 # number of ReadReq MSHR uncacheable cycles
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3820807000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7316839500 # number of ReadReq MSHR uncacheable cycles
2016-05-31 12:07:18 +02:00
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3496032500 # number of overall MSHR uncacheable cycles
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 3820807000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7316839500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.076420 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.066805 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.072634 # mshr miss rate for ReadReq accesses
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.236016 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.236016 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092581 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092581 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.257538 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.257538 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.728943 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.728943 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.076420 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.066805 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092581 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.252419 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.166278 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.076420 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.066805 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092581 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.252419 # mshr miss rate for overall accesses
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.235841 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25987.228085 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43310.223511 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 43310.223511 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18525.289672 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18525.289672 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15274.090934 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15274.090934 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 163708.250000 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 163708.250000 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38278.277545 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38278.277545 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29802.051653 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29802.051653 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28643.524399 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28643.524399 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32147.228314 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32147.228314 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29802.051653 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30786.242975 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30433.782810 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29802.051653 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30786.242975 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43310.223511 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34231.791627 # average overall mshr miss latency
2016-05-31 12:07:18 +02:00
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average ReadReq mshr uncacheable latency
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 181726.848989 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114058.293063 # average ReadReq mshr uncacheable latency
2016-05-31 12:07:18 +02:00
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average overall mshr uncacheable latency
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 88010.665008 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 84550.596270 # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests 22270826 # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11431607 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1159 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops 634641 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 634635 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq 532548 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 9516927 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 22389 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 22388 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty 5262772 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean 7044356 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict 1133181 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 892107 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 438346 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 371201 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 524392 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 1190804 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 1167926 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5174652 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4606140 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq 845268 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp 799396 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15609689 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18074319 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 333482 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 538074 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 34555564 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 662494868 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 674962485 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1270200 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1955080 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 1340682633 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 5171785 # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic 107950516 # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples 16772894 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 0.051983 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.221994 # Request fanout histogram
2014-10-30 05:50:15 +01:00
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.cpu0.toL2Bus.snoop_fanout::0 15900995 94.80% 94.80% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 871893 5.20% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram
2014-10-30 05:50:15 +01:00
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.cpu0.toL2Bus.snoop_fanout::total 16772894 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 22046960997 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu0.toL2Bus.snoopLayer0.occupancy 203834159 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu0.toL2Bus.respLayer0.occupancy 7805103000 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu0.toL2Bus.respLayer1.occupancy 7957435977 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu0.toL2Bus.respLayer2.occupancy 174707000 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu0.toL2Bus.respLayer3.occupancy 293689000 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 113512 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 113512 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10824 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 86665 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 27 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 113485 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 0.290787 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 77.918264 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-2047 113483 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
2016-07-21 18:19:18 +02:00
system.cpu1.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.walker.walkWaitTime::total 113485 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 97516 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 23769.576275 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 22071.904189 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 14608.572728 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767 88342 90.59% 90.59% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535 8042 8.25% 98.84% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-98303 147 0.15% 98.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-131071 810 0.83% 99.82% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-163839 21 0.02% 99.84% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::163840-196607 18 0.02% 99.86% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-229375 45 0.05% 99.91% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::229376-262143 20 0.02% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911 17 0.02% 99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::294912-327679 36 0.04% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-425983 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::425984-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 97516 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 14762172 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 194.841712 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 -2861524688 -19384.17% -19384.17% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1 2876286860 19484.17% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 14762172 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 86666 88.90% 88.90% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 10824 11.10% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 97490 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 113512 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 113512 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97490 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97490 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 211002 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.read_hits 83873503 # DTB read hits
system.cpu1.dtb.read_misses 85876 # DTB read misses
system.cpu1.dtb.write_hits 75393075 # DTB write hits
system.cpu1.dtb.write_misses 27636 # DTB write misses
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 39012 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.prefetch_faults 3907 # Number of TLB faults due to prefetch
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.perms_faults 10199 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 83959379 # DTB read accesses
system.cpu1.dtb.write_accesses 75420711 # DTB write accesses
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.hits 159266578 # DTB hits
system.cpu1.dtb.misses 113512 # DTB misses
system.cpu1.dtb.accesses 159380090 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-08-12 15:12:59 +02:00
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 59776 # Table walker walks requested
system.cpu1.itb.walker.walksLong 59776 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 674 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 53293 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples 59776 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 59776 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 59776 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 53967 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 25622.306224 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 23504.254601 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 18586.945639 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535 52820 97.87% 97.87% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071 977 1.81% 99.68% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607 34 0.06% 99.75% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143 58 0.11% 99.86% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679 61 0.11% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 53967 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples -1314622148 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 -1314622148 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total -1314622148 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 53293 98.75% 98.75% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 674 1.25% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 53967 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 59776 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 59776 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53967 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53967 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 113743 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 442849873 # ITB inst hits
system.cpu1.itb.inst_misses 59776 # ITB inst misses
2014-10-30 05:50:15 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-08-12 15:12:59 +02:00
system.cpu1.itb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 27503 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
2016-08-12 15:12:59 +02:00
system.cpu1.itb.inst_accesses 442909649 # ITB inst accesses
system.cpu1.itb.hits 442849873 # DTB hits
system.cpu1.itb.misses 59776 # DTB misses
system.cpu1.itb.accesses 442909649 # DTB accesses
system.cpu1.numPwrStateTransitions 28574 # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples 14287 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean 3279405691.982362 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev 123453533761.994095 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows 4140 28.98% 28.98% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10 10126 70.88% 99.85% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11 7 0.05% 99.90% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.92% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.92% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.93% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::overflows 10 0.07% 100.00% # Distribution of time spent in the clock gated state
2016-07-21 18:19:18 +02:00
system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
2016-08-12 15:12:59 +02:00
system.cpu1.pwrStateClkGateDist::max_value 11813601970000 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total 14287 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON 521446289148 # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 46852869121352 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 94748630821 # number of cpu cycles simulated
2014-10-30 05:50:15 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-10-10 23:45:41 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
2016-08-12 15:12:59 +02:00
system.cpu1.kern.inst.quiesce 14287 # number of quiesce instructions executed
system.cpu1.committedInsts 442543215 # Number of instructions committed
system.cpu1.committedOps 520378160 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 478315040 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 404780 # Number of float alu accesses
system.cpu1.num_func_calls 26483096 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 67217461 # number of instructions that are conditional controls
system.cpu1.num_int_insts 478315040 # number of integer instructions
system.cpu1.num_fp_insts 404780 # number of float instructions
system.cpu1.num_int_register_reads 696723237 # number of times the integer registers were read
system.cpu1.num_int_register_writes 379679857 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 664337 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 317564 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 114632172 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 114267384 # number of times the CC registers were written
system.cpu1.num_mem_refs 159256484 # number of memory refs
system.cpu1.num_load_insts 83870110 # Number of load instructions
system.cpu1.num_store_insts 75386374 # Number of store instructions
system.cpu1.num_idle_cycles 93705738242.702026 # Number of idle cycles
system.cpu1.num_busy_cycles 1042892578.297978 # Number of busy cycles
system.cpu1.not_idle_fraction 0.011007 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.988993 # Percentage of idle cycles
system.cpu1.Branches 98643380 # Number of branches fetched
system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu 360264761 69.19% 69.19% # Class of executed instruction
system.cpu1.op_class::IntMult 1062033 0.20% 69.39% # Class of executed instruction
system.cpu1.op_class::IntDiv 60918 0.01% 69.41% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 40731 0.01% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::MemRead 83870110 16.11% 85.52% # Class of executed instruction
system.cpu1.op_class::MemWrite 75386374 14.48% 100.00% # Class of executed instruction
2014-10-30 05:50:15 +01:00
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
2016-08-12 15:12:59 +02:00
system.cpu1.op_class::total 520684927 # Class of executed instruction
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 5203972 # number of replacements
system.cpu1.dcache.tags.tagsinuse 424.411021 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 153866536 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 5204484 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 29.564225 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 8378899013000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 424.411021 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.828928 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.828928 # Average percentage of cache occupancy
2016-07-21 18:19:18 +02:00
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
2016-07-21 18:19:18 +02:00
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-08-12 15:12:59 +02:00
system.cpu1.dcache.tags.tag_accesses 323742508 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 323742508 # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 78110378 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 78110378 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 71558729 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 71558729 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 177304 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 177304 # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data 95899 # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total 95899 # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1773602 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 1773602 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1738086 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 1738086 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 149765006 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 149765006 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 149942310 # number of overall hits
system.cpu1.dcache.overall_hits::total 149942310 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 2993339 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 2993339 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 1322577 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 1322577 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 630415 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 630415 # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data 446111 # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total 446111 # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 170906 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 170906 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 205163 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 205163 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 4762027 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 4762027 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 5392442 # number of overall misses
system.cpu1.dcache.overall_misses::total 5392442 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43487315000 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 43487315000 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 24009342500 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 24009342500 # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10785817000 # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total 10785817000 # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2544188500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 2544188500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4864957000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 4864957000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2180500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2180500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 78282474500 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 78282474500 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 78282474500 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 78282474500 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 81103717 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 81103717 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 72881306 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 72881306 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 807719 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 807719 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 542010 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total 542010 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1944508 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 1944508 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1943249 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 1943249 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 154527033 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 154527033 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 155334752 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 155334752 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036908 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.036908 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018147 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.018147 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.780488 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.780488 # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.823068 # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total 0.823068 # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.087892 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.087892 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105577 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105577 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.030817 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.030817 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034715 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.034715 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14528.028733 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14528.028733 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18153.455338 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 18153.455338 # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24177.428936 # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24177.428936 # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14886.478532 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14886.478532 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23712.643118 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23712.643118 # average StoreCondReq miss latency
2014-11-12 15:05:25 +01:00
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2016-08-12 15:12:59 +02:00
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16438.897658 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 16438.897658 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14517.073063 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 14517.073063 # average overall miss latency
2014-11-12 15:05:25 +01:00
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu1.dcache.writebacks::writebacks 5203972 # number of writebacks
system.cpu1.dcache.writebacks::total 5203972 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 14156 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 14156 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 216 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 216 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44175 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44175 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 14372 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 14372 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 14372 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 14372 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2979183 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 2979183 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1322361 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 1322361 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 630415 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 630415 # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 446111 # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total 446111 # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 126731 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 126731 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 205163 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 205163 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 4747655 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 4747655 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 5378070 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 5378070 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17577 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17577 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 16125 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 16125 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 33702 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 33702 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39805955500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39805955500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22681350000 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22681350000 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12330973000 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12330973000 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10339706000 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10339706000 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1686365000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1686365000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4659843000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4659843000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2131500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2131500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 72827011500 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 72827011500 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 85157984500 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 85157984500 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2978895500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2978895500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2978895500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2978895500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036733 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036733 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018144 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018144 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.780488 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.780488 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.823068 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.823068 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065174 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065174 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105577 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105577 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030724 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.030724 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034622 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.034622 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13361.366354 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13361.366354 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17152.161929 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17152.161929 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19560.088196 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19560.088196 # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23177.428936 # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23177.428936 # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13306.649517 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13306.649517 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22712.881952 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22712.881952 # average StoreCondReq mshr miss latency
2014-11-12 15:05:25 +01:00
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2016-08-12 15:12:59 +02:00
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15339.575327 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15339.575327 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15834.301989 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15834.301989 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169476.901633 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 169476.901633 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 88389.279568 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 88389.279568 # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 4895837 # number of replacements
system.cpu1.icache.tags.tagsinuse 496.209399 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 437953524 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 4896349 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 89.444916 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 8378871626000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.209399 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969159 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.969159 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu1.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id
2014-10-30 05:50:15 +01:00
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-08-12 15:12:59 +02:00
system.cpu1.icache.tags.tag_accesses 890596095 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 890596095 # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 437953524 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 437953524 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 437953524 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 437953524 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 437953524 # number of overall hits
system.cpu1.icache.overall_hits::total 437953524 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 4896349 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 4896349 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 4896349 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 4896349 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 4896349 # number of overall misses
system.cpu1.icache.overall_misses::total 4896349 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 51444170000 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 51444170000 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 51444170000 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 51444170000 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 51444170000 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 51444170000 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 442849873 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 442849873 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 442849873 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 442849873 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 442849873 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 442849873 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011056 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.011056 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011056 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.011056 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011056 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.011056 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10506.638722 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10506.638722 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10506.638722 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10506.638722 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10506.638722 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10506.638722 # average overall miss latency
2014-10-30 05:50:15 +01:00
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu1.icache.writebacks::writebacks 4895837 # number of writebacks
system.cpu1.icache.writebacks::total 4895837 # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4896349 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 4896349 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 4896349 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 4896349 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 4896349 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 4896349 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses
2016-08-12 15:12:59 +02:00
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 48995995500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 48995995500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 48995995500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 48995995500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 48995995500 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 48995995500 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10402000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10402000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10402000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 10402000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011056 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011056 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011056 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.011056 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011056 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.011056 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10006.638722 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10006.638722 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10006.638722 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 10006.638722 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10006.638722 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 10006.638722 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94563.636364 # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 94563.636364 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94563.636364 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 94563.636364 # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued 7252070 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 7252079 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 8 # number of redundant prefetches already in prefetch queue
2014-12-23 15:31:20 +01:00
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.prefetcher.pfSpanPage 909185 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements 1859788 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 13078.836793 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 8983696 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 1875537 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 4.789933 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 12823.617935 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 17.493162 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 11.479573 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 226.246124 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.782692 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001068 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000701 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.013809 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.798269 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 286 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 54 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15409 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 107 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 144 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 23 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 39 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 868 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6435 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7258 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 673 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017456 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003296 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.940491 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 348956442 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 348956442 # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 258658 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 151547 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 410205 # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks 3266667 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total 3266667 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks 6832390 # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total 6832390 # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 881671 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 881671 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4452144 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 4452144 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2841120 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 2841120 # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 192152 # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total 192152 # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 258658 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 151547 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 4452144 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 3722791 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 8585140 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 258658 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 151547 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 4452144 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 3722791 # number of overall hits
system.cpu1.l2cache.overall_hits::total 8585140 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 18381 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9249 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 27630 # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 207506 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 207506 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 205160 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 205160 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 235234 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 235234 # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 444205 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total 444205 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 895209 # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total 895209 # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 252043 # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total 252043 # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 18381 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9249 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 444205 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 1130443 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 1602278 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 18381 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9249 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 444205 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 1130443 # number of overall misses
system.cpu1.l2cache.overall_misses::total 1602278 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 560546000 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 349476500 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 910022500 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 940760500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 940760500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 308144500 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 308144500 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2058000 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2058000 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9879714999 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 9879714999 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 14896666000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total 14896666000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 29710253000 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total 29710253000 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 322403500 # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total 322403500 # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 560546000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 349476500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 14896666000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 39589967999 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 55396656499 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 560546000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 349476500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 14896666000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 39589967999 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 55396656499 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 277039 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 160796 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 437835 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3266667 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total 3266667 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks 6832390 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total 6832390 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 207506 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 207506 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 205160 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 205160 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1116905 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 1116905 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4896349 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total 4896349 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3736329 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total 3736329 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 444195 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total 444195 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 277039 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 160796 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 4896349 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 4853234 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 10187418 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 277039 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 160796 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 4896349 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 4853234 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 10187418 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.066348 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.057520 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.063106 # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
2015-11-06 09:26:50 +01:00
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.210612 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.210612 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.090722 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.090722 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.239596 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.239596 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.567415 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.567415 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.066348 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.057520 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.090722 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.232926 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.157280 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.066348 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.057520 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.090722 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.232926 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.157280 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 30495.946902 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 37785.328144 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32936.029678 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4533.654449 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4533.654449 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1501.971632 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1501.971632 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 686000 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 686000 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 41999.519623 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41999.519623 # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 33535.565786 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 33535.565786 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 33188.063346 # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 33188.063346 # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1279.160699 # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1279.160699 # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 30495.946902 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 37785.328144 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 33535.565786 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 35021.640188 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 34573.686026 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 30495.946902 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 37785.328144 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 33535.565786 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 35021.640188 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 34573.686026 # average overall miss latency
2014-12-23 15:31:20 +01:00
system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.unused_prefetches 39888 # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks 1080406 # number of writebacks
system.cpu1.l2cache.writebacks::total 1080406 # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 5355 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 5355 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 314 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 314 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 2 # number of InvalidateReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::total 2 # number of InvalidateReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 5669 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total 5669 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 5669 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 5669 # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 18381 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9249 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total 27630 # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 700284 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 700284 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 207506 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 207506 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 205160 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 205160 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 229879 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total 229879 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 444205 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 444205 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 894895 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 894895 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 252041 # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total 252041 # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 18381 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9249 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 444205 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1124774 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total 1596609 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 18381 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9249 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 444205 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1124774 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 700284 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total 2296893 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 17577 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 17687 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 16125 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 16125 # number of WriteReq MSHR uncacheable
2015-05-05 09:22:39 +02:00
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 33702 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 33812 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 450260000 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 293982500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 744242500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 29274832519 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 29274832519 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3856981999 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3856981999 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3119783996 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3119783996 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1764000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1764000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7964098999 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7964098999 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 12231436000 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 12231436000 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 24307582500 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 24307582500 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6863337500 # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6863337500 # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 450260000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 293982500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 12231436000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 32271681499 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 45247359999 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 450260000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 293982500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 12231436000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 32271681499 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 29274832519 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 74522192518 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9577000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2837977500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2847554500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9577000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2837977500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2847554500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.066348 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.057520 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.063106 # mshr miss rate for ReadReq accesses
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2015-11-06 09:26:50 +01:00
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.205818 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.205818 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.090722 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.090722 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.239512 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239512 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.567411 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.567411 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.066348 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.057520 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.090722 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.231758 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.156724 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.066348 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.057520 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.090722 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.231758 # mshr miss rate for overall accesses
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.225464 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26936.029678 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41804.228740 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41804.228740 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18587.327591 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18587.327591 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15206.589959 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15206.589959 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 588000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 588000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34644.743535 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34644.743535 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 27535.565786 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27535.565786 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 27162.496717 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27162.496717 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27231.035824 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27231.035824 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27535.565786 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28691.702955 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28339.662371 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27535.565786 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28691.702955 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41804.228740 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32444.781937 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87063.636364 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161459.720089 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 160997.031718 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87063.636364 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 84207.984689 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 84217.274932 # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests 20954555 # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10760929 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 751 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops 564007 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 564007 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq 525208 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 9244496 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 16125 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 16125 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty 4351848 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean 6833141 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict 1083593 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 850253 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 408331 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 372440 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 477174 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 56 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 1146242 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 1123232 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4896349 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4644090 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 493781 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp 444195 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14688755 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16849115 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 339302 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 606054 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 32483226 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 626700344 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 649733422 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1286368 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2216312 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 1279936446 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 4601099 # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic 75959664 # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples 15521649 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 0.052382 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.222797 # Request fanout histogram
2014-10-30 05:50:15 +01:00
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.cpu1.toL2Bus.snoop_fanout::0 14708591 94.76% 94.76% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 813058 5.24% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-10-30 05:50:15 +01:00
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 15521649 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 20731667993 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu1.toL2Bus.snoopLayer0.occupancy 171895510 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu1.toL2Bus.respLayer0.occupancy 7344633500 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu1.toL2Bus.respLayer1.occupancy 7734220026 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu1.toL2Bus.respLayer2.occupancy 178506000 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu1.toL2Bus.respLayer3.occupancy 329015998 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 40399 # Transaction distribution
system.iobus.trans_dist::ReadResp 40399 # Transaction distribution
system.iobus.trans_dist::WriteReq 136980 # Transaction distribution
system.iobus.trans_dist::WriteResp 136980 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47798 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.iobus.pkt_count_system.bridge.master::total 122940 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231738 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231738 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.iobus.pkt_count::total 354758 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47818 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.iobus.pkt_size_system.bridge.master::total 155955 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355304 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7355304 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.iobus.pkt_size::total 7513345 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 37010502 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer2.occupancy 320500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer23.occupancy 26741000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer24.occupancy 37418500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer25.occupancy 570750713 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.respLayer0.occupancy 92947000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.respLayer3.occupancy 148178000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-07-03 16:15:03 +02:00
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 115853 # number of replacements
system.iocache.tags.tagsinuse 11.245503 # Cycle average of tags in use
2016-02-10 10:08:27 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2016-08-12 15:12:59 +02:00
system.iocache.tags.sampled_refs 115869 # Sample count of references to valid blocks.
2016-02-10 10:08:27 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2016-08-12 15:12:59 +02:00
system.iocache.tags.warmup_cycle 9136243501000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.839816 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 7.405687 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.239988 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.462855 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.702844 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2016-08-12 15:12:59 +02:00
system.iocache.tags.tag_accesses 1043178 # Number of tag accesses
system.iocache.tags.data_accesses 1043178 # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2016-08-12 15:12:59 +02:00
system.iocache.ReadReq_misses::realview.ide 8885 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8922 # number of ReadReq misses
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2016-08-12 15:12:59 +02:00
system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2016-08-12 15:12:59 +02:00
system.iocache.demand_misses::realview.ide 115869 # number of demand (read+write) misses
system.iocache.demand_misses::total 115909 # number of demand (read+write) misses
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2016-08-12 15:12:59 +02:00
system.iocache.overall_misses::realview.ide 115869 # number of overall misses
system.iocache.overall_misses::total 115909 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5278000 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1633593087 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1638871087 # number of ReadReq miss cycles
2015-03-02 11:04:20 +01:00
system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
2016-08-12 15:12:59 +02:00
system.iocache.WriteLineReq_miss_latency::realview.ide 12911092626 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 12911092626 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5647000 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 14544685713 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 14550332713 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5647000 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 14544685713 # number of overall miss cycles
system.iocache.overall_miss_latency::total 14550332713 # number of overall miss cycles
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2016-08-12 15:12:59 +02:00
system.iocache.ReadReq_accesses::realview.ide 8885 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8922 # number of ReadReq accesses(hits+misses)
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2016-08-12 15:12:59 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses)
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2016-08-12 15:12:59 +02:00
system.iocache.demand_accesses::realview.ide 115869 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 115909 # number of demand (read+write) accesses
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2016-08-12 15:12:59 +02:00
system.iocache.overall_accesses::realview.ide 115869 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 115909 # number of overall (read+write) accesses
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2016-02-10 10:08:27 +01:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2016-08-12 15:12:59 +02:00
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 142648.648649 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 183859.660889 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 183688.756669 # average ReadReq miss latency
2015-03-02 11:04:20 +01:00
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
2016-08-12 15:12:59 +02:00
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120682.463041 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 120682.463041 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 141175 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 125526.980582 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 125532.380687 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 141175 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 125526.980582 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 125532.380687 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 31750 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.iocache.blocked::no_mshrs 3454 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 9.192241 # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.iocache.writebacks::writebacks 106953 # number of writebacks
system.iocache.writebacks::total 106953 # number of writebacks
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2016-08-12 15:12:59 +02:00
system.iocache.ReadReq_mshr_misses::realview.ide 8885 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8922 # number of ReadReq MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2016-08-12 15:12:59 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2016-08-12 15:12:59 +02:00
system.iocache.demand_mshr_misses::realview.ide 115869 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 115909 # number of demand (read+write) MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2016-08-12 15:12:59 +02:00
system.iocache.overall_mshr_misses::realview.ide 115869 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 115909 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3428000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1189343087 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1192771087 # number of ReadReq MSHR miss cycles
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
2016-08-12 15:12:59 +02:00
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7553188799 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 7553188799 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3647000 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 8742531886 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8746178886 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3647000 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 8742531886 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8746178886 # number of overall MSHR miss cycles
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2016-02-10 10:08:27 +01:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2016-08-12 15:12:59 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92648.648649 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133859.660889 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 133688.756669 # average ReadReq mshr miss latency
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
2016-08-12 15:12:59 +02:00
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70601.106698 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70601.106698 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 91175 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 75451.862759 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 75457.288787 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 91175 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75451.862759 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75457.288787 # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 1378015 # number of replacements
system.l2c.tags.tagsinuse 64998.786153 # Cycle average of tags in use
system.l2c.tags.total_refs 6107230 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1440978 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 4.238253 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 9552186500 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 11716.268844 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 133.184810 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 146.917074 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4004.381376 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 14231.433494 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7902.194687 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 315.518093 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 369.695425 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 2763.350410 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 11175.503416 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 12240.338524 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.178776 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002032 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.002242 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.061102 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.217154 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.120578 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004814 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.005641 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.042165 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.170525 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.186773 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.991803 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 12060 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 189 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 50714 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::0 60 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1 153 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 1009 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 1115 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 9723 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 184 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 1849 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 9563 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 39124 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.184021 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.002884 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.773834 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 69629880 # Number of tag accesses
system.l2c.tags.data_accesses 69629880 # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 2641101 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 2641101 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data 213424 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 155298 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 368722 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 50511 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 50527 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 101038 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 63650 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 48993 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 112643 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 10681 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5935 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 422841 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 567260 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 276728 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 9775 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4116 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 406188 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 512398 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 278781 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 2494703 # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data 136557 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data 120325 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total 256882 # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker 10681 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 5935 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 422841 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 630910 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 276728 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 9775 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 4116 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 406188 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 561391 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 278781 # number of demand (read+write) hits
system.l2c.demand_hits::total 2607346 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 10681 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 5935 # number of overall hits
system.l2c.overall_hits::cpu0.inst 422841 # number of overall hits
system.l2c.overall_hits::cpu0.data 630910 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 276728 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 9775 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 4116 # number of overall hits
system.l2c.overall_hits::cpu1.inst 406188 # number of overall hits
system.l2c.overall_hits::cpu1.data 561391 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 278781 # number of overall hits
system.l2c.overall_hits::total 2607346 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 24497 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 25507 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 50004 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 796 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 825 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1621 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 72583 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 52296 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 124879 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1676 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1611 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst 56236 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 130395 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 210895 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1750 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1829 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst 38017 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 107679 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 200910 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 750998 # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data 430773 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data 119101 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total 549874 # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker 1676 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 1611 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 56236 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 202978 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 210895 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 1750 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 1829 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 38017 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 159975 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher 200910 # number of demand (read+write) misses
system.l2c.demand_misses::total 875877 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 1676 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 1611 # number of overall misses
system.l2c.overall_misses::cpu0.inst 56236 # number of overall misses
system.l2c.overall_misses::cpu0.data 202978 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 210895 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 1750 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 1829 # number of overall misses
system.l2c.overall_misses::cpu1.inst 38017 # number of overall misses
system.l2c.overall_misses::cpu1.data 159975 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 200910 # number of overall misses
system.l2c.overall_misses::total 875877 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data 177641500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 151031500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 328673000 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 8353500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 8021500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 16375000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 6466021500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 4532203999 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 10998225499 # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 151916500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 149670500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst 4848581000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 11828995999 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 26350487356 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 157377000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 162435000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3283945500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 9698473500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 24221293566 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 80853175921 # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data 43381500 # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data 30876500 # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total 74258000 # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 151916500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 149670500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 4848581000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 18295017499 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 26350487356 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 157377000 # number of demand (read+write) miss cycles
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system.l2c.demand_miss_latency::total 91851401420 # number of demand (read+write) miss cycles
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system.l2c.overall_miss_latency::cpu1.dtb.walker 157377000 # number of overall miss cycles
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system.l2c.overall_miss_latency::cpu1.inst 3283945500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 14230677499 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 24221293566 # number of overall miss cycles
system.l2c.overall_miss_latency::total 91851401420 # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks 2641101 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 2641101 # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 237921 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 180805 # number of UpgradeReq accesses(hits+misses)
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system.l2c.SCUpgradeReq_accesses::cpu0.data 51307 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 51352 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 102659 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 136233 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 101289 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 237522 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 12357 # number of ReadSharedReq accesses(hits+misses)
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system.l2c.ReadSharedReq_accesses::cpu0.data 697655 # number of ReadSharedReq accesses(hits+misses)
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system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 11525 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5945 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst 444205 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 620077 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 479691 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 3245701 # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data 567330 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data 239426 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total 806756 # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 12357 # number of demand (read+write) accesses
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system.l2c.demand_accesses::cpu0.l2cache.prefetcher 487623 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 11525 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 5945 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 444205 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 721366 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher 479691 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 3483223 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 12357 # number of overall (read+write) accesses
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system.l2c.overall_accesses::cpu0.inst 479077 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 833888 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 487623 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 11525 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 5945 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 444205 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 721366 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher 479691 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 3483223 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.102963 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.141075 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.119419 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.015514 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.016066 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.015790 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.532786 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.516305 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.525758 # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.135632 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.213491 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.117384 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.186905 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.432496 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.151844 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.307653 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.085584 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.173654 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.418832 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.231382 # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data 0.759299 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data 0.497444 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total 0.681587 # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.135632 # miss rate for demand accesses
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system.l2c.demand_miss_rate::cpu0.inst 0.117384 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.243412 # miss rate for demand accesses
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system.l2c.demand_miss_rate::cpu1.dtb.walker 0.151844 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.307653 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.085584 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.221767 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.418832 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.251456 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.135632 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.213491 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.117384 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.243412 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.432496 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.151844 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.307653 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.085584 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.221767 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.418832 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.251456 # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 7251.561416 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5921.178500 # average UpgradeReq miss latency
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system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 10494.346734 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9723.030303 # average SCUpgradeReq miss latency
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system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 124946.003253 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89929.714286 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 88810.825588 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86380.974301 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90068.383807 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 120557.929252 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 107660.973692 # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 100.706172 # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 259.246354 # average InvalidateReq miss latency
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system.l2c.demand_avg_miss_latency::cpu0.data 90133.007020 # average overall miss latency
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system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89929.714286 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88810.825588 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 86380.974301 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 88955.633687 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 120557.929252 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 104867.922574 # average overall miss latency
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system.l2c.overall_avg_miss_latency::cpu0.itb.walker 92905.338299 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 86218.454371 # average overall miss latency
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system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 124946.003253 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89929.714286 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88810.825588 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 86380.974301 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 88955.633687 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 120557.929252 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 104867.922574 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 424 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.l2c.blocked::no_mshrs 5 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.l2c.avg_blocked_cycles::no_mshrs 84.800000 # average number of cycles each access was blocked
2014-11-12 15:05:25 +01:00
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.l2c.writebacks::writebacks 1062304 # number of writebacks
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system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 133 # number of ReadSharedReq MSHR hits
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system.l2c.demand_mshr_hits::cpu1.data 16 # number of demand (read+write) MSHR hits
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system.l2c.overall_mshr_hits::cpu1.data 16 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 302 # number of overall MSHR hits
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system.l2c.CleanEvict_mshr_misses::total 54771 # number of CleanEvict MSHR misses
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system.l2c.overall_mshr_misses::total 875575 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
2016-08-12 15:12:59 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 21025 # number of ReadReq MSHR uncacheable
2015-05-05 09:22:39 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
2016-08-12 15:12:59 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 17575 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 81835 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 22388 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 16125 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 38513 # number of WriteReq MSHR uncacheable
2015-05-05 09:22:39 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
2016-08-12 15:12:59 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 43413 # number of overall MSHR uncacheable misses
2015-05-05 09:22:39 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
2016-08-12 15:12:59 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 33700 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 120348 # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 503126000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 519991500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 1023117500 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 19775000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 20085500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 39860500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5740155074 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4009215058 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 9749370132 # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 135154504 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 133557506 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 4277568054 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 10520997188 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 24241323314 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 139876501 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 144145000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 2898586521 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 8620097178 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 22212057363 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 73323363129 # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8575090000 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2366625500 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total 10941715500 # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 135154504 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 133557506 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 4277568054 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 16261152262 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 24241323314 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 139876501 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 144145000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 2898586521 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 12629312236 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 22212057363 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 83072733261 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 135154504 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 133557506 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 4277568054 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 16261152262 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 24241323314 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 139876501 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 144145000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 2898586521 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 12629312236 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 22212057363 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 83072733261 # number of overall MSHR miss cycles
2016-05-31 12:07:18 +02:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2719782000 # number of ReadReq MSHR uncacheable cycles
2016-08-12 15:12:59 +02:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3442200004 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7595500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2521551501 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 8691129005 # number of ReadReq MSHR uncacheable cycles
2016-05-31 12:07:18 +02:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2719782000 # number of overall MSHR uncacheable cycles
2016-08-12 15:12:59 +02:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3442200004 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7595500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2521551501 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 8691129005 # number of overall MSHR uncacheable cycles
2015-07-03 16:15:03 +02:00
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2016-08-12 15:12:59 +02:00
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.102963 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.141075 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.119419 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.015514 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.016066 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.015790 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.532786 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.516305 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.525758 # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.135632 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.213491 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.117106 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.186813 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.432496 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.151844 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.307653 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.085384 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.173628 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.418832 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.231289 # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.759299 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.497444 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total 0.681587 # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.135632 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.213491 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.117106 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.243335 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.432496 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.151844 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.307653 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.085384 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.221745 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.418832 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.251369 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.135632 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.213491 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.117106 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.243335 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.432496 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.151844 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.307653 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.085384 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.221745 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.418832 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.251369 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20538.269992 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20386.227310 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20460.713143 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24842.964824 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24346.060606 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24590.067859 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79084.015183 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 76663.895097 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 78070.533332 # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 76244.907652 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80725.208799 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76423.394880 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80065.548777 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 97673.842846 # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19906.284749 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19870.744158 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19898.586767 # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76244.907652 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 80138.148487 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76423.394880 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78953.433292 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 94877.918238 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76244.907652 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 80138.148487 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76423.394880 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78953.433292 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 94877.918238 # average overall mshr miss latency
2016-05-31 12:07:18 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average ReadReq mshr uncacheable latency
2016-08-12 15:12:59 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 163719.381879 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69050 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143473.769616 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 106203.079428 # average ReadReq mshr uncacheable latency
2016-05-31 12:07:18 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average overall mshr uncacheable latency
2016-08-12 15:12:59 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 79289.613802 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69050 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 74823.486677 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 72216.646766 # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests 3586859 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 2135577 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 3113 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-05-31 12:07:18 +02:00
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-08-12 15:12:59 +02:00
system.membus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 81835 # Transaction distribution
system.membus.trans_dist::ReadResp 841453 # Transaction distribution
system.membus.trans_dist::WriteReq 38513 # Transaction distribution
system.membus.trans_dist::WriteResp 38513 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1169257 # Transaction distribution
system.membus.trans_dist::CleanEvict 224172 # Transaction distribution
system.membus.trans_dist::UpgradeReq 330190 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 306798 # Transaction distribution
system.membus.trans_dist::UpgradeResp 21 # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution
system.membus.trans_dist::ReadExReq 142313 # Transaction distribution
system.membus.trans_dist::ReadExResp 124217 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 759618 # Transaction distribution
system.membus.trans_dist::InvalidateReq 654423 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122940 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26066 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4320804 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4469902 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238504 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 238504 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4708406 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155955 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52132 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124129580 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 124337871 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7276480 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7276480 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 131614351 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 603280 # Total snoops (count)
system.membus.snoopTraffic 185472 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 2313692 # Request fanout histogram
system.membus.snoop_fanout::mean 0.013382 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.114902 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.membus.snoop_fanout::0 2282731 98.66% 98.66% # Request fanout histogram
system.membus.snoop_fanout::1 30961 1.34% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2016-05-31 12:07:18 +02:00
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.membus.snoop_fanout::total 2313692 # Request fanout histogram
system.membus.reqLayer0.occupancy 101576998 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.reqLayer2.occupancy 21542999 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.reqLayer5.occupancy 8037178912 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.respLayer2.occupancy 4828786098 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.respLayer3.occupancy 45456460 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2016-08-12 15:12:59 +02:00
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
2014-11-12 15:05:25 +01:00
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
2016-03-16 21:03:49 +01:00
system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
2014-11-12 15:05:25 +01:00
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
2016-03-16 21:03:49 +01:00
system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
2014-11-12 15:05:25 +01:00
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2016-08-12 15:12:59 +02:00
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2016-08-12 15:12:59 +02:00
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 10929949 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 5951808 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 1800454 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 181173 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 166358 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 14815 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 81837 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 4119674 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 38513 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 38513 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 3703405 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 2363493 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 695815 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 407836 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 1103651 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 102 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 294367 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 294367 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 4038548 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 834564 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 806756 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8843715 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7139942 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 15983657 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 216752505 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 175713942 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 392466447 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 2839573 # Total snoops (count)
system.toL2Bus.snoopTraffic 122328784 # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples 7769609 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.368989 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.486467 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.toL2Bus.snoop_fanout::0 4917524 63.29% 63.29% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 2837270 36.52% 99.81% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 14815 0.19% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.toL2Bus.snoop_fanout::total 7769609 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 8597464366 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.toL2Bus.snoopLayer0.occupancy 2599172 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.toL2Bus.respLayer0.occupancy 4012155776 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.toL2Bus.respLayer1.occupancy 3555978029 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2014-10-30 05:50:15 +01:00
---------- End Simulation Statistics ----------
