sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
gem5/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt

461 lines
52 KiB
Text
Raw Normal View History

inorder-regress: add twolf ALPHA-SE
2009-05-12 21:01:16 +02:00
---------- Begin Simulation Statistics ----------
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
sim_seconds 0.042001 # Number of seconds simulated
sim_ticks 42001440000 # Number of ticks simulated
final_tick 42001440000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
inorder-regress: add twolf ALPHA-SE
2009-05-12 21:01:16 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
host_inst_rate 134131 # Simulator instruction rate (inst/s)
host_op_rate 134131 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 61300636 # Simulator tick rate (ticks/s)
host_mem_usage 216520 # Number of bytes of host memory used
host_seconds 685.17 # Real time elapsed on the host
inorder: regr-update: reduce dynamic mem. use to speedup sims previous changesets took a closer look at memory mgmt in the inorder model and sought to avoid dynamic memory mgmt (for access to pipeline resources) as much as possible. For the regressions that were run, the sims are about 2x speedup from changeset 7726 which is the last change since the recent commits in Feb. (note: these regressions now are 4-issue CPUs instead of just 1-issue)
2011-02-18 20:31:37 +01:00
sim_insts 91903056 # Number of instructions simulated
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
sim_ops 91903056 # Number of ops (including micro ops) simulated
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory
system.physmem.bytes_read::total 316032 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 178816 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 178816 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.physmem.bw_read::cpu.inst 4257378 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3266936 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 7524313 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 4257378 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 4257378 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 4257378 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3266936 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7524313 # Total bandwidth to/from this memory (bytes/s)
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dtb.read_hits 19996215 # DTB read hits
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dtb.read_misses 10 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dtb.read_accesses 19996225 # DTB read accesses
system.cpu.dtb.write_hits 6501907 # DTB write hits
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dtb.write_misses 23 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dtb.write_accesses 6501930 # DTB write accesses
system.cpu.dtb.data_hits 26498122 # DTB hits
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dtb.data_misses 33 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dtb.data_accesses 26498155 # DTB accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.itb.fetch_hits 10035828 # ITB hits
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.itb.fetch_misses 49 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.itb.fetch_accesses 10035877 # ITB accesses
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.numCycles 84002881 # number of cpu cycles simulated
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.branch_predictor.lookups 13564877 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 9782208 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 4497797 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 7992443 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 3850454 # Number of BTB hits
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target.
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.branch_predictor.RASInCorrect 122 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 48.176183 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 5999677 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 7565200 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 73745294 # Number of Reads from Int. Register File
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.regfile_manager.intRegFileAccesses 136320766 # Total Accesses (Read+Write) to the Int. Register File
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.regfile_manager.floatRegFileReads 2206799 # Number of Reads from FP Register File
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.regfile_manager.floatRegFileAccesses 8058687 # Total Accesses (Read+Write) to the FP Register File
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.regfile_manager.regForwards 38528678 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 26769096 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 3520460 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 976479 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 4496939 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 5743763 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 43.912410 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 57470351 # Number of Instructions Executed.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.mult_div_unit.multiplies 458258 # Number of Multipy Operations Executed
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.contextSwitches 1 # Number of context switches
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.threadCycles 83639631 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.timesIdled 11378 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7720370 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 76282511 # Number of cycles cpu stages are processed.
system.cpu.activity 90.809399 # Percentage of cycles cpu is active
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.comLoads 19996198 # Number of Load instructions committed
system.cpu.comStores 6501103 # Number of Store instructions committed
system.cpu.comBranches 10240685 # Number of Branches instructions committed
system.cpu.comNops 7723346 # Number of Nop instructions committed
system.cpu.comNonSpec 389 # Number of Non-Speculative instructions committed
system.cpu.comInts 43665352 # Number of Integer instructions committed
system.cpu.comFloats 3775974 # Number of Floating Point instructions committed
system.cpu.committedInsts 91903056 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total)
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.cpi 0.914038 # CPI: Cycles Per Instruction (Per-Thread)
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.cpi_total 0.914038 # CPI: Total CPI of All Threads
system.cpu.ipc 1.094046 # IPC: Instructions Per Cycle (Per-Thread)
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.ipc_total 1.094046 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 27781439 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 56221442 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 66.927993 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 34555420 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 49447461 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 58.864006 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 34024816 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 49978065 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 59.495656 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 65973303 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 18029578 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 21.463047 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 30058791 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 53944090 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 64.216952 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 8127 # number of replacements
system.cpu.icache.tagsinuse 1492.293343 # Cycle average of tags in use
system.cpu.icache.total_refs 10024070 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 10012 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1001.205553 # Average number of references to valid blocks.
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.icache.occ_blocks::cpu.inst 1492.293343 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.728659 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.728659 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 10024070 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 10024070 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 10024070 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 10024070 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 10024070 # number of overall hits
system.cpu.icache.overall_hits::total 10024070 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 11754 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 11754 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 11754 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 11754 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 11754 # number of overall misses
system.cpu.icache.overall_misses::total 11754 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 284626500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 284626500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 284626500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 284626500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 284626500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 284626500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 10035824 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 10035824 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 10035824 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 10035824 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 10035824 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 10035824 # number of overall (read+write) accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001171 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.001171 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.001171 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.001171 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001171 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001171 # miss rate for overall accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24215.288412 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 24215.288412 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 24215.288412 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 24215.288412 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24215.288412 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 24215.288412 # average overall miss latency
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.icache.blocked_cycles::no_targets 184 # number of cycles access was blocked
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets 30.666667 # average number of cycles each access was blocked
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1742 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 1742 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 1742 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 1742 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 1742 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 1742 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10012 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 10012 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 10012 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 10012 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 10012 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 10012 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 231904000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 231904000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 231904000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 231904000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 231904000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 231904000 # number of overall MSHR miss cycles
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000998 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000998 # mshr miss rate for overall accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23162.604874 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23162.604874 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23162.604874 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 23162.604874 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23162.604874 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 23162.604874 # average overall mshr miss latency
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 157 # number of replacements
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.tagsinuse 1441.465399 # Cycle average of tags in use
system.cpu.dcache.total_refs 26491189 # Total number of references to valid blocks.
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.avg_refs 11916.864148 # Average number of references to valid blocks.
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.occ_blocks::cpu.data 1441.465399 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.351920 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.351920 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 19995639 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 19995639 # number of ReadReq hits
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.WriteReq_hits::cpu.data 6495550 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 6495550 # number of WriteReq hits
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.demand_hits::cpu.data 26491189 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26491189 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26491189 # number of overall hits
system.cpu.dcache.overall_hits::total 26491189 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 559 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 559 # number of ReadReq misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.WriteReq_misses::cpu.data 5553 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5553 # number of WriteReq misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.demand_misses::cpu.data 6112 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 6112 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 6112 # number of overall misses
system.cpu.dcache.overall_misses::total 6112 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 28955000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 28955000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 305088500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 305088500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 334043500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 334043500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 334043500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 334043500 # number of overall miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000854 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000854 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000231 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000231 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000231 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000231 # miss rate for overall accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51797.853309 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 51797.853309 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54941.202953 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 54941.202953 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54653.714005 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 54653.714005 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54653.714005 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 54653.714005 # average overall miss latency
inorder-regress: add twolf ALPHA-SE
2009-05-12 21:01:16 +02:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.dcache.blocked_cycles::no_targets 82457 # number of cycles access was blocked
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.blocked::no_targets 827 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.dcache.avg_blocked_cycles::no_targets 99.706167 # average number of cycles each access was blocked
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
inorder-regress: add twolf ALPHA-SE
2009-05-12 21:01:16 +02:00
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
system.cpu.dcache.writebacks::total 107 # number of writebacks
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3805 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3805 # number of WriteReq MSHR hits
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.demand_mshr_hits::cpu.data 3889 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3889 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3889 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3889 # number of overall MSHR hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24156000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24156000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96637000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 96637000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 120793000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 120793000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 120793000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 120793000 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50854.736842 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50854.736842 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55284.324943 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55284.324943 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54337.831759 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 54337.831759 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54337.831759 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54337.831759 # average overall mshr miss latency
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.tagsinuse 2189.683531 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7285 # Total number of references to valid blocks.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks.
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.avg_refs 2.219683 # Average number of references to valid blocks.
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.occ_blocks::writebacks 17.845444 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1820.840268 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 350.997820 # Average occupied blocks per requestor
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.occ_percent::cpu.inst 0.055568 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.066824 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 7218 # number of ReadReq hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_hits::total 7271 # number of ReadReq hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_hits::cpu.inst 7218 # number of demand (read+write) hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_hits::total 7297 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 7218 # number of overall hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_hits::total 7297 # number of overall hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 2794 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 1722 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1722 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2794 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2144 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 4938 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
system.cpu.l2cache.overall_misses::total 4938 # number of overall misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 149399500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23132500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 172532000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 94615000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 94615000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 149399500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 117747500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 267147000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 149399500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 117747500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 267147000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 10012 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_accesses::total 10487 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses)
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_accesses::cpu.inst 10012 # number of demand (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_accesses::total 12235 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 10012 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_accesses::total 12235 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.279065 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_miss_rate::total 0.306665 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.279065 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_miss_rate::total 0.403596 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279065 # miss rate for overall accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_miss_rate::total 0.403596 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53471.546170 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54816.350711 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 53648.009950 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54944.831591 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54944.831591 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53471.546170 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54919.542910 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 54100.243013 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53471.546170 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54919.542910 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 54100.243013 # average overall miss latency
inorder-regress: add twolf ALPHA-SE
2009-05-12 21:01:16 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
inorder-regress: add twolf ALPHA-SE
2009-05-12 21:01:16 +02:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2794 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 3216 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1722 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1722 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2794 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 4938 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115312500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17984000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 133296500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73481500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73481500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115312500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 91465500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 206778000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115312500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 91465500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 206778000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.306665 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::total 0.403596 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for overall accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.403596 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41271.474588 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42616.113744 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41447.916667 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42672.183508 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42672.183508 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41271.474588 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42661.147388 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41874.848117 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41271.474588 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42661.147388 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41874.848117 # average overall mshr miss latency
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
inorder-regress: add twolf ALPHA-SE
2009-05-12 21:01:16 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink