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gem5/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt

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inorder: add 00.gzip and 60.bzip2 regression tests
2011-02-23 22:35:25 +01:00
---------- Begin Simulation Statistics ----------
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
sim_seconds 0.271545 # Number of seconds simulated
sim_ticks 271544682500 # Number of ticks simulated
final_tick 271544682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
inorder: add 00.gzip and 60.bzip2 regression tests
2011-02-23 22:35:25 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
host_inst_rate 142205 # Simulator instruction rate (inst/s)
host_op_rate 142205 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 64159611 # Simulator tick rate (ticks/s)
host_mem_usage 212920 # Number of bytes of host memory used
host_seconds 4232.33 # Real time elapsed on the host
inorder: add 00.gzip and 60.bzip2 regression tests
2011-02-23 22:35:25 +01:00
sim_insts 601856964 # Number of instructions simulated
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
sim_ops 601856964 # Number of ops (including micro ops) simulated
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1620224 # Number of bytes read from this memory
system.physmem.bytes_read::total 1674048 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 53824 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 53824 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 57024 # Number of bytes written to this memory
system.physmem.bytes_written::total 57024 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 841 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 25316 # Number of read requests responded to by this memory
system.physmem.num_reads::total 26157 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 891 # Number of write requests responded to by this memory
system.physmem.num_writes::total 891 # Number of write requests responded to by this memory
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.physmem.bw_read::cpu.inst 198214 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 5966694 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 6164908 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 198214 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 198214 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 209999 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 209999 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 209999 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 198214 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5966694 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6374907 # Total bandwidth to/from this memory (bytes/s)
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dtb.read_hits 114517787 # DTB read hits
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dtb.read_misses 2631 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dtb.read_accesses 114520418 # DTB read accesses
system.cpu.dtb.write_hits 39661840 # DTB write hits
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dtb.write_misses 2302 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dtb.write_accesses 39664142 # DTB write accesses
system.cpu.dtb.data_hits 154179627 # DTB hits
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dtb.data_misses 4933 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dtb.data_accesses 154184560 # DTB accesses
system.cpu.itb.fetch_hits 25070818 # ITB hits
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.itb.fetch_accesses 25070840 # ITB accesses
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.numCycles 543089366 # number of cpu cycles simulated
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.branch_predictor.lookups 86310005 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 81365597 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 36354317 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 52694904 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 34317639 # Number of BTB hits
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.branch_predictor.BTBHitPct 65.125157 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 36895090 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 49414915 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 541552617 # Number of Reads from Int. Register File
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.regfile_manager.intRegFileAccesses 1005407463 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 255071199 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 155051796 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 33757784 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 2591546 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 36349330 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 26198577 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 58.114383 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 412334991 # Number of Instructions Executed.
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.contextSwitches 1 # Number of context switches
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.threadCycles 538349706 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.timesIdled 387700 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 53984537 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 489104829 # Number of cycles cpu stages are processed.
system.cpu.activity 90.059732 # Percentage of cycles cpu is active
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.comLoads 114514042 # Number of Load instructions committed
system.cpu.comStores 39451321 # Number of Store instructions committed
system.cpu.comBranches 62547159 # Number of Branches instructions committed
system.cpu.comNops 36304520 # Number of Nop instructions committed
system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed
system.cpu.comInts 349039879 # Number of Integer instructions committed
system.cpu.comFloats 24 # Number of Floating Point instructions committed
system.cpu.committedInsts 601856964 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total)
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.cpi 0.902356 # CPI: Cycles Per Instruction (Per-Thread)
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.cpi_total 0.902356 # CPI: Total CPI of All Threads
system.cpu.ipc 1.108210 # IPC: Instructions Per Cycle (Per-Thread)
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.ipc_total 1.108210 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 204234221 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 338855145 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 62.393994 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 232262845 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 310826521 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 57.233034 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 201309957 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 341779409 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 62.932444 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 431519146 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 111570220 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.543621 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 196111910 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 346977456 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 63.889569 # Percentage of cycles stage was utilized (processing insts).
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.icache.replacements 30 # number of replacements
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.icache.tagsinuse 729.073717 # Cycle average of tags in use
system.cpu.icache.total_refs 25069794 # Total number of references to valid blocks.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks.
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.icache.avg_refs 29321.396491 # Average number of references to valid blocks.
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.icache.occ_blocks::cpu.inst 729.073717 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.355993 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.355993 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 25069794 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 25069794 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 25069794 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 25069794 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 25069794 # number of overall hits
system.cpu.icache.overall_hits::total 25069794 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1022 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1022 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1022 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1022 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1022 # number of overall misses
system.cpu.icache.overall_misses::total 1022 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 56347500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 56347500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 56347500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 56347500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 56347500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 56347500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 25070816 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 25070816 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 25070816 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 25070816 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 25070816 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 25070816 # number of overall (read+write) accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55134.540117 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55134.540117 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55134.540117 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55134.540117 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55134.540117 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55134.540117 # average overall miss latency
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.icache.blocked_cycles::no_targets 175 # number of cycles access was blocked
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets 58.333333 # average number of cycles each access was blocked
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 167 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 167 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 167 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 167 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 167 # number of overall MSHR hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46510500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 46510500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46510500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 46510500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46510500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 46510500 # number of overall MSHR miss cycles
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54398.245614 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54398.245614 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54398.245614 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 54398.245614 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54398.245614 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 54398.245614 # average overall mshr miss latency
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 451299 # number of replacements
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.tagsinuse 4094.014631 # Cycle average of tags in use
system.cpu.dcache.total_refs 152406162 # Total number of references to valid blocks.
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.avg_refs 334.668062 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 268976000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.014631 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999515 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999515 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 114120507 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 114120507 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 38285655 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 38285655 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 152406162 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 152406162 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 152406162 # number of overall hits
system.cpu.dcache.overall_hits::total 152406162 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 393535 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 393535 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1165666 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1165666 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1559201 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1559201 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1559201 # number of overall misses
system.cpu.dcache.overall_misses::total 1559201 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5490501500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5490501500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 16777875500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 16777875500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 22268377000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 22268377000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 22268377000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 22268377000 # number of overall miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029547 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.029547 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.010127 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.010127 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.010127 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.010127 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13951.748891 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13951.748891 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14393.381552 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 14393.381552 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14281.915545 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14281.915545 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14281.915545 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14281.915545 # average overall miss latency
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.dcache.blocked_cycles::no_mshrs 42145 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 4093205 # number of cycles access was blocked
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.blocked::no_mshrs 3164 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 211457 # number of cycles access was blocked
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.320164 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 19.357151 # average number of cycles each access was blocked
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks
system.cpu.dcache.writebacks::total 436902 # number of writebacks
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192303 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 192303 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911503 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 911503 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1103806 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1103806 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1103806 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1103806 # number of overall MSHR hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2395605000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2395605000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3804662000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3804662000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6200267000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6200267000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6200267000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6200267000 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11904.692097 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11904.692097 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14969.377919 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14969.377919 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13615.140702 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13615.140702 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13615.140702 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13615.140702 # average overall mshr miss latency
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.replacements 917 # number of replacements
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.tagsinuse 22852.343306 # Cycle average of tags in use
system.cpu.l2cache.total_refs 538836 # Total number of references to valid blocks.
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.sampled_refs 23142 # Sample count of references to valid blocks.
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.avg_refs 23.283899 # Average number of references to valid blocks.
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.occ_blocks::writebacks 21651.877416 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 719.990292 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 480.475597 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.660763 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.021972 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.014663 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.697398 # Average percentage of cache occupancy
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_hits::cpu.data 197087 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 197101 # number of ReadReq hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.Writeback_hits::writebacks 436902 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 436902 # number of Writeback hits
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 232992 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 232992 # number of ReadExReq hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 430079 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 430093 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 14 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 430079 # number of overall hits
system.cpu.l2cache.overall_hits::total 430093 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 841 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 4120 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 4961 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 21196 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 21196 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 841 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 25316 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 26157 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 25316 # number of overall misses
system.cpu.l2cache.overall_misses::total 26157 # number of overall misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45502000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 215882000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 261384000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1220308500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1220308500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 45502000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1436190500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1481692500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 45502000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1436190500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1481692500 # number of overall miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses)
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.Writeback_accesses::writebacks 436902 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 436902 # number of Writeback accesses(hits+misses)
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254188 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 254188 # number of ReadExReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 855 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983626 # miss rate for ReadReq accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020476 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.024552 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083387 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.083387 # miss rate for ReadExReq accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983626 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.055591 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.057330 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.055591 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.057330 # miss rate for overall accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54104.637337 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52398.543689 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52687.764564 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 57572.584450 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 57572.584450 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54104.637337 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56730.545900 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 56646.117674 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54104.637337 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56730.545900 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 56646.117674 # average overall miss latency
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 217 # number of cycles access was blocked
inorder: add 00.gzip and 60.bzip2 regression tests
2011-02-23 22:35:25 +01:00
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 27.125000 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
inorder: add 00.gzip and 60.bzip2 regression tests
2011-02-23 22:35:25 +01:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.writebacks::writebacks 891 # number of writebacks
system.cpu.l2cache.writebacks::total 891 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 841 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4120 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 4961 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21196 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 21196 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 841 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 25316 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 26157 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 25316 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 26157 # number of overall MSHR misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35251500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 165390500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200642000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 961154000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 961154000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35251500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1126544500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1161796000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35251500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1126544500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1161796000 # number of overall MSHR miss cycles
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020476 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024552 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083387 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083387 # mshr miss rate for ReadExReq accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.057330 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.057330 # mshr miss rate for overall accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41916.171225 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40143.325243 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40443.862125 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45346.008681 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45346.008681 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41916.171225 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44499.308738 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44416.255687 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41916.171225 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44499.308738 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44416.255687 # average overall mshr miss latency
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
inorder: add 00.gzip and 60.bzip2 regression tests
2011-02-23 22:35:25 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink