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gem5/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt

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Added SPARC o3 insttest regression. --HG-- extra : convert_revision : b008b4bda60ced329df9b700ff9b0a978e2d3b19
2007-04-09 09:59:56 +02:00
---------- Begin Simulation Statistics ----------
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
sim_seconds 0.000020 # Number of seconds simulated
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
sim_ticks 20274500 # Number of ticks simulated
final_tick 20274500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
Added SPARC o3 insttest regression. --HG-- extra : convert_revision : b008b4bda60ced329df9b700ff9b0a978e2d3b19
2007-04-09 09:59:56 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
host_inst_rate 55162 # Simulator instruction rate (inst/s)
host_op_rate 55159 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 77392529 # Simulator tick rate (ticks/s)
host_mem_usage 220968 # Number of bytes of host memory used
host_seconds 0.26 # Real time elapsed on the host
regress: update regressions for tty emulation fix.
2008-07-25 01:31:54 +02:00
sim_insts 14449 # Number of instructions simulated
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
sim_ops 14449 # Number of ops (including micro ops) simulated
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.physmem.bytes_read::cpu.inst 21568 # Number of bytes read from this memory
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.physmem.bytes_read::total 30912 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 21568 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 21568 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 337 # Number of read requests responded to by this memory
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.physmem.num_reads::total 483 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1063799354 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 460874498 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1524673851 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1063799354 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1063799354 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1063799354 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 460874498 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1524673851 # Total bandwidth to/from this memory (bytes/s)
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.workload.num_syscalls 18 # Number of system calls
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.numCycles 40550 # number of cpu cycles simulated
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.BPredUnit.lookups 6892 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 4586 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 1120 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 5125 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 2600 # Number of BTB hits
tests: update tests because of changes in stat names and in the stats package
2009-03-07 23:30:55 +01:00
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.BPredUnit.usedRAS 458 # Number of times the RAS was used to get a target.
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.fetch.icacheStallCycles 12259 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 32259 # Number of instructions fetch has processed
system.cpu.fetch.Branches 6892 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 3058 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 9557 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3181 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 7365 # Number of cycles fetch has spent blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.fetch.PendingTrapStallCycles 767 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 5500 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 472 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 31917 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.010715 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.185460 # Number of instructions fetched each cycle (Total)
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.fetch.rateDist::0 22360 70.06% 70.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4750 14.88% 84.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 493 1.54% 86.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 436 1.37% 87.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 686 2.15% 90.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 773 2.42% 92.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 235 0.74% 93.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 276 0.86% 94.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1908 5.98% 100.00% # Number of instructions fetched each cycle (Total)
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.fetch.rateDist::total 31917 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.169963 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.795536 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 12903 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 8133 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 8719 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 197 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1965 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 30080 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1965 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 13582 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 285 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 7298 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 8277 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 510 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 27385 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 172 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 24421 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 50913 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 50913 # Number of integer rename lookups
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.rename.CommittedMaps 13832 # Number of HB maps that are committed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.rename.UndoneMaps 10589 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 704 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 706 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 2903 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 3640 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 2472 # Number of stores inserted to the mem dependence unit.
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iq.iqInstsAdded 23148 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 669 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 21730 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 108 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 8364 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 5915 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 194 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 31917 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.680828 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.297413 # Number of insts issued each cycle
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iq.issued_per_cycle::0 22417 70.24% 70.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 3682 11.54% 81.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 2373 7.43% 89.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 1722 5.40% 94.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 904 2.83% 97.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 493 1.54% 98.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 244 0.76% 99.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 65 0.20% 99.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 17 0.05% 100.00% # Number of insts issued each cycle
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iq.issued_per_cycle::total 31917 # Number of insts issued each cycle
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iq.fu_full::IntAlu 46 26.59% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 26.59% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 24 13.87% 40.46% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 103 59.54% 100.00% # attempts to use FU when none available
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iq.FU_type_0::IntAlu 16031 73.77% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.77% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 3433 15.80% 89.57% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 2266 10.43% 100.00% # Type of FU issued
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iq.FU_type_0::total 21730 # Type of FU issued
system.cpu.iq.rate 0.535882 # Inst issue rate
system.cpu.iq.fu_busy_cnt 173 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.007961 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 75658 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 32207 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 19957 # Number of integer instruction queue wakeup accesses
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iq.int_alu_accesses 21903 # Number of integer alu accesses
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 1414 # Number of loads squashed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
O3: Update stats for new ordering fix.
2011-09-13 18:58:09 +02:00
system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iew.lsq.thread0.squashedStores 1024 # Number of stores squashed
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iew.iewSquashCycles 1965 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 99 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 24982 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 417 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 3640 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 2472 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 669 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
O3: Update stats for new ordering fix.
2011-09-13 18:58:09 +02:00
system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.iew.predictedTakenIncorrect 291 # Number of branches that were predicted taken incorrectly
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iew.predictedNotTakenIncorrect 958 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1249 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 20553 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 3273 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1177 # Number of squashed instructions skipped in execute
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iew.exec_nop 1165 # number of nop insts executed
system.cpu.iew.exec_refs 5419 # number of memory reference insts executed
system.cpu.iew.exec_branches 4294 # Number of branches executed
system.cpu.iew.exec_stores 2146 # Number of stores executed
system.cpu.iew.exec_rate 0.506856 # Inst execution rate
system.cpu.iew.wb_sent 20221 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 19957 # cumulative count of insts written-back
system.cpu.iew.wb_producers 9257 # num instructions producing a value
system.cpu.iew.wb_consumers 11359 # num instructions consuming a value
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iew.wb_rate 0.492158 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.814948 # average fanout of values written-back
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
regress: update regressions for tty emulation fix.
2008-07-25 01:31:54 +02:00
system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.commit.commitCommittedOps 15175 # The number of committed instructions
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.commit.commitSquashedInsts 9725 # The number of squashed insts skipped by commit
regress: update regressions for tty emulation fix.
2008-07-25 01:31:54 +02:00
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.commit.branchMispredicts 1120 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 29969 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.506357 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.189037 # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.commit.committed_per_cycle::0 22543 75.22% 75.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 4136 13.80% 89.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 1421 4.74% 93.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 789 2.63% 96.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 331 1.10% 97.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 259 0.86% 98.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 318 1.06% 99.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 73 0.24% 99.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 99 0.33% 100.00% # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.commit.committed_per_cycle::total 29969 # Number of insts commited each cycle
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.commit.committedInsts 15175 # Number of instructions committed
system.cpu.commit.committedOps 15175 # Number of ops (including micro ops) committed
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 3674 # Number of memory references committed
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.loads 2226 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.commit.branches 3359 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 12186 # Number of committed integer instructions.
system.cpu.commit.function_calls 187 # Number of function calls committed.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.commit.bw_lim_events 99 # number cycles where commit BW limit reached
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.rob.rob_reads 53947 # The number of ROB reads
system.cpu.rob.rob_writes 51773 # The number of ROB writes
system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 8633 # Total number of cycles that the CPU has spent unscheduled due to idling
regress: update regressions for tty emulation fix.
2008-07-25 01:31:54 +02:00
system.cpu.committedInsts 14449 # Number of Instructions Simulated
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.committedOps 14449 # Number of Ops (including micro ops) Simulated
regress: update regressions for tty emulation fix.
2008-07-25 01:31:54 +02:00
system.cpu.committedInsts_total 14449 # Number of Instructions Simulated
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.cpi 2.806423 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.806423 # CPI: Total CPI of All Threads
system.cpu.ipc 0.356326 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.356326 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 32739 # number of integer regfile reads
system.cpu.int_regfile_writes 18191 # number of integer regfile writes
system.cpu.misc_regfile_reads 7070 # number of misc regfile reads
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
system.cpu.icache.replacements 0 # number of replacements
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.icache.tagsinuse 199.218311 # Cycle average of tags in use
system.cpu.icache.total_refs 5020 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 14.808260 # Average number of references to valid blocks.
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.icache.occ_blocks::cpu.inst 199.218311 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.097275 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.097275 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 5020 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 5020 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 5020 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 5020 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 5020 # number of overall hits
system.cpu.icache.overall_hits::total 5020 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 480 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 480 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 480 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 480 # number of overall misses
system.cpu.icache.overall_misses::total 480 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16877500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 16877500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 16877500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 16877500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 16877500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 16877500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 5500 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 5500 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 5500 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 5500 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 5500 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 5500 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.087273 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.087273 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.087273 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.087273 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.087273 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.087273 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35161.458333 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 35161.458333 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 35161.458333 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 35161.458333 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 35161.458333 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 35161.458333 # average overall miss latency
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 141 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 141 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 141 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 141 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 141 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 141 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 339 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 339 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 339 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 339 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 339 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12213000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 12213000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12213000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 12213000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12213000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 12213000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.061636 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.061636 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.061636 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.061636 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.061636 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.061636 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36026.548673 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36026.548673 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36026.548673 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 36026.548673 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36026.548673 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 36026.548673 # average overall mshr miss latency
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.tagsinuse 102.764065 # Cycle average of tags in use
system.cpu.dcache.total_refs 4075 # Total number of references to valid blocks.
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.avg_refs 27.910959 # Average number of references to valid blocks.
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.occ_blocks::cpu.data 102.764065 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.025089 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.025089 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 3036 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 3036 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.demand_hits::cpu.data 4069 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 4069 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 4069 # number of overall hits
system.cpu.dcache.overall_hits::total 4069 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 121 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 121 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 530 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 530 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 530 # number of overall misses
system.cpu.dcache.overall_misses::total 530 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4649500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 4649500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 17651000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 17651000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 22300500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 22300500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 22300500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 22300500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 3157 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 3157 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.demand_accesses::cpu.data 4599 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 4599 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 4599 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 4599 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.038328 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.038328 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.115242 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.115242 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.115242 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.115242 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38425.619835 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 38425.619835 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43156.479218 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 43156.479218 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 42076.415094 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 42076.415094 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 42076.415094 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 42076.415094 # average overall miss latency
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
Added SPARC o3 insttest regression. --HG-- extra : convert_revision : b008b4bda60ced329df9b700ff9b0a978e2d3b19
2007-04-09 09:59:56 +02:00
system.cpu.dcache.cache_copies 0 # number of cache copies performed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 384 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 384 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 384 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 384 # number of overall MSHR hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 63 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2518000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2518000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3293000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3293000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5811000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 5811000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5811000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 5811000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019956 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019956 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031746 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.031746 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031746 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.031746 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39968.253968 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39968.253968 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39674.698795 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39674.698795 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 39801.369863 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 39801.369863 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 39801.369863 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 39801.369863 # average overall mshr miss latency
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.tagsinuse 234.467813 # Cycle average of tags in use
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.005000 # Average number of references to valid blocks.
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.occ_blocks::cpu.inst 198.479082 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 35.988731 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.006057 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001098 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.007155 # Average percentage of cache occupancy
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 337 # number of ReadReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.data 63 # number of ReadReq misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.ReadReq_misses::total 400 # number of ReadReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.demand_misses::cpu.inst 337 # number of demand (read+write) misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_misses::cpu.data 146 # number of demand (read+write) misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.demand_misses::total 483 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 337 # number of overall misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_misses::cpu.data 146 # number of overall misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.overall_misses::total 483 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11867000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2431500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 14298500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3194500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3194500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 11867000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 5626000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 17493000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 11867000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 5626000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 17493000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 339 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_accesses::cpu.data 63 # number of ReadReq accesses(hits+misses)
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.ReadReq_accesses::total 402 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses)
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.demand_accesses::cpu.inst 339 # number of demand (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.demand_accesses::total 485 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 339 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.overall_accesses::total 485 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994100 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.ReadReq_miss_rate::total 0.995025 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994100 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.demand_miss_rate::total 0.995876 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994100 # miss rate for overall accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.overall_miss_rate::total 0.995876 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35213.649852 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38595.238095 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 35746.250000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38487.951807 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38487.951807 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35213.649852 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38534.246575 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 36217.391304 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35213.649852 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38534.246575 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 36217.391304 # average overall miss latency
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
Added SPARC o3 insttest regression. --HG-- extra : convert_revision : b008b4bda60ced329df9b700ff9b0a978e2d3b19
2007-04-09 09:59:56 +02:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::total 400 # number of ReadReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.demand_mshr_misses::total 483 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10794500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2238500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13033000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2937500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2937500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10794500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5176000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 15970500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10794500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5176000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 15970500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994100 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994100 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994100 # mshr miss rate for overall accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32031.157270 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35531.746032 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32582.500000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35391.566265 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35391.566265 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32031.157270 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35452.054795 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33065.217391 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32031.157270 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35452.054795 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33065.217391 # average overall mshr miss latency
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
Added SPARC o3 insttest regression. --HG-- extra : convert_revision : b008b4bda60ced329df9b700ff9b0a978e2d3b19
2007-04-09 09:59:56 +02:00
---------- End Simulation Statistics ----------
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