2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
2016-05-31 12:07:18 +02:00
sim_seconds 47.384315 # Number of seconds simulated
sim_ticks 47384315163000 # Number of ticks simulated
final_tick 47384315163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-05-31 12:07:18 +02:00
host_inst_rate 172390 # Simulator instruction rate (inst/s)
host_op_rate 202727 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 9043218476 # Simulator tick rate (ticks/s)
host_mem_usage 765852 # Number of bytes of host memory used
host_seconds 5239.76 # Real time elapsed on the host
sim_insts 903281747 # Number of instructions simulated
sim_ops 1062243320 # Number of ops (including micro ops) simulated
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-05-31 12:07:18 +02:00
system.physmem.bytes_read::cpu0.dtb.walker 88320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 58304 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 4233376 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 12825352 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 13896960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 201536 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 189312 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 2647264 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 11439440 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 16431296 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 444928 # Number of bytes read from this memory
system.physmem.bytes_read::total 62456088 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 4233376 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 2647264 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 6880640 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 79489088 # Number of bytes written to this memory
2015-05-05 09:22:39 +02:00
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
2014-12-02 12:08:25 +01:00
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
2016-05-31 12:07:18 +02:00
system.physmem.bytes_written::total 79509672 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 1380 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 911 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 82099 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 200409 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 217140 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 3149 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 2958 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 41407 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 178754 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 256739 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6952 # Number of read requests responded to by this memory
system.physmem.num_reads::total 991898 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1242017 # Number of write requests responded to by this memory
2015-05-05 09:22:39 +02:00
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
2014-12-02 12:08:25 +01:00
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
2016-05-31 12:07:18 +02:00
system.physmem.num_writes::total 1244591 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 1864 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 1230 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 89341 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 270667 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 293282 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 4253 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 3995 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 55868 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 241418 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 346767 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 9390 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1318075 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 89341 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 55868 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 145209 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1677540 # Write bandwidth from this memory (bytes/s)
2016-02-24 10:16:59 +01:00
system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
2014-12-02 12:08:25 +01:00
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
2016-05-31 12:07:18 +02:00
system.physmem.bw_write::total 1677974 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1677540 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 1864 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 1230 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 89341 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 271101 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 293282 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 4253 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 3995 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 55868 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 241418 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 346767 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 9390 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2996050 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 991898 # Number of read requests accepted
system.physmem.writeReqs 1244591 # Number of write requests accepted
system.physmem.readBursts 991898 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1244591 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 63457600 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 23872 # Total number of bytes read from write queue
system.physmem.bytesWritten 79508544 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 62456088 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 79509672 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 373 # Number of DRAM read bursts serviced by the write queue
2015-07-03 16:15:03 +02:00
system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-05-31 12:07:18 +02:00
system.physmem.perBankRdBursts::0 57534 # Per bank write bursts
system.physmem.perBankRdBursts::1 67322 # Per bank write bursts
system.physmem.perBankRdBursts::2 57239 # Per bank write bursts
system.physmem.perBankRdBursts::3 59640 # Per bank write bursts
system.physmem.perBankRdBursts::4 58543 # Per bank write bursts
system.physmem.perBankRdBursts::5 68655 # Per bank write bursts
system.physmem.perBankRdBursts::6 57471 # Per bank write bursts
system.physmem.perBankRdBursts::7 60839 # Per bank write bursts
system.physmem.perBankRdBursts::8 60208 # Per bank write bursts
system.physmem.perBankRdBursts::9 81942 # Per bank write bursts
system.physmem.perBankRdBursts::10 59318 # Per bank write bursts
system.physmem.perBankRdBursts::11 61436 # Per bank write bursts
system.physmem.perBankRdBursts::12 60309 # Per bank write bursts
system.physmem.perBankRdBursts::13 62906 # Per bank write bursts
system.physmem.perBankRdBursts::14 58748 # Per bank write bursts
system.physmem.perBankRdBursts::15 59415 # Per bank write bursts
system.physmem.perBankWrBursts::0 74024 # Per bank write bursts
system.physmem.perBankWrBursts::1 81724 # Per bank write bursts
system.physmem.perBankWrBursts::2 74878 # Per bank write bursts
system.physmem.perBankWrBursts::3 76858 # Per bank write bursts
system.physmem.perBankWrBursts::4 76593 # Per bank write bursts
system.physmem.perBankWrBursts::5 82864 # Per bank write bursts
system.physmem.perBankWrBursts::6 74278 # Per bank write bursts
system.physmem.perBankWrBursts::7 78173 # Per bank write bursts
system.physmem.perBankWrBursts::8 76626 # Per bank write bursts
system.physmem.perBankWrBursts::9 80136 # Per bank write bursts
system.physmem.perBankWrBursts::10 77163 # Per bank write bursts
system.physmem.perBankWrBursts::11 80655 # Per bank write bursts
system.physmem.perBankWrBursts::12 76245 # Per bank write bursts
system.physmem.perBankWrBursts::13 79687 # Per bank write bursts
system.physmem.perBankWrBursts::14 75064 # Per bank write bursts
system.physmem.perBankWrBursts::15 77353 # Per bank write bursts
2014-10-30 05:50:15 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2016-05-31 12:07:18 +02:00
system.physmem.numWrRetry 51477 # Number of times write queue was full causing retry
system.physmem.totGap 47384313590500 # Total gap between requests
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
2015-05-05 09:22:39 +02:00
system.physmem.readPktSize::3 25 # Read request sizes (log2)
2015-03-02 11:04:20 +01:00
system.physmem.readPktSize::4 21333 # Read request sizes (log2)
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-05-31 12:07:18 +02:00
system.physmem.readPktSize::6 970540 # Read request sizes (log2)
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
2015-05-05 09:22:39 +02:00
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2016-05-31 12:07:18 +02:00
system.physmem.writePktSize::6 1242017 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 445378 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 243433 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 76996 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 56880 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 37150 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 31949 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 29173 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 27068 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 25124 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 6848 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 3836 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 2454 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1543 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1198 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 708 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 591 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 507 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 398 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 167 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 104 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see
2016-04-21 10:48:24 +02:00
system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see
2016-02-24 10:16:59 +01:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
2014-12-23 15:31:20 +01:00
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2014-10-30 05:50:15 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2016-05-31 12:07:18 +02:00
system.physmem.wrQLenPdf::15 23188 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 27066 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 36083 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 41131 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 44808 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 48159 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 53054 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 57269 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 61997 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 63720 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 68707 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 72599 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 69938 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 72538 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 82492 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 73770 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 67397 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 63055 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 4615 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 3320 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 2487 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 1667 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 1537 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 1438 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 1351 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1216 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1258 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1384 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1422 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 1370 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 1543 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 1563 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 1451 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 1716 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 1865 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 2021 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 2168 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 2359 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 2664 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 2841 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 3106 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 3376 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 3630 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 3943 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 4563 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 6136 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 24445 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 120872 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 982131 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 145.566960 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 98.657532 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 193.069606 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 654413 66.63% 66.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 194527 19.81% 86.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 50477 5.14% 91.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 21176 2.16% 93.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 16419 1.67% 95.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 9395 0.96% 96.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 6596 0.67% 97.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 5289 0.54% 97.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 23839 2.43% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 982131 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 56922 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 17.418608 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 74.895923 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511 56917 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023 2 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes
2016-02-24 10:16:59 +01:00
system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
2016-05-31 12:07:18 +02:00
system.physmem.rdPerTurnAround::total 56922 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 56922 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 21.824971 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.750218 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 638.100533 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-4095 56920 100.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::45056-49151 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::143360-147455 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 56922 # Writes before turning the bus around for reads
system.physmem.totQLat 43578574020 # Total ticks spent queuing
system.physmem.totMemAccLat 62169667770 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 4957625000 # Total ticks spent in databus transfers
system.physmem.avgQLat 43951.06 # Average queueing delay per DRAM burst
2014-10-30 05:50:15 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-05-31 12:07:18 +02:00
system.physmem.avgMemAccLat 62701.06 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.34 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.68 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.32 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.68 # Average system write bandwidth in MiByte/s
2014-10-30 05:50:15 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2016-05-31 12:07:18 +02:00
system.physmem.busUtil 0.02 # Data bus utilization in percentage
2016-02-24 10:16:59 +01:00
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
2016-04-09 18:13:40 +02:00
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
2016-05-31 12:07:18 +02:00
system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing
system.physmem.avgWrQLen 23.75 # Average write queue length when enqueuing
system.physmem.readRowHits 750886 # Number of row buffer hits during reads
system.physmem.writeRowHits 500828 # Number of row buffer hits during writes
system.physmem.readRowHitRate 75.73 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 40.31 # Row buffer hit rate for writes
system.physmem.avgGap 21186920.03 # Average gap between requests
system.physmem.pageHitRate 56.03 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 3717395640 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 2028340875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 3800456400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 4013660160 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3094913078400 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1158326321940 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 27414513105000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 31681312358415 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.603367 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 45606511009457 # Time in different power states
system.physmem_0.memoryStateTime::REF 1582266400000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-05-31 12:07:18 +02:00
system.physmem_0.memoryStateTime::ACT 195537314293 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-05-31 12:07:18 +02:00
system.physmem_1.actEnergy 3707514720 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2022949500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 3933399600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 4036579920 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3094913078400 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1156667621085 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 27415968105750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 31681249248975 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.602035 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 45608919765384 # Time in different power states
system.physmem_1.memoryStateTime::REF 1582266400000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-05-31 12:07:18 +02:00
system.physmem_1.memoryStateTime::ACT 193128558366 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory
2014-12-02 12:08:05 +01:00
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
2015-11-06 09:26:50 +01:00
system.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory
2014-12-02 12:08:05 +01:00
system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory
2015-11-06 09:26:50 +01:00
system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 23 # Number of read requests responded to by this memory
2014-12-02 12:08:05 +01:00
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
2015-11-06 09:26:50 +01:00
system.realview.nvmem.num_reads::total 38 # Number of read requests responded to by this memory
2014-12-02 12:08:05 +01:00
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
2016-05-31 12:07:18 +02:00
system.cpu0.branchPred.lookups 138091637 # Number of BP lookups
system.cpu0.branchPred.condPredicted 91311717 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 6789940 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 97223509 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 59866310 # Number of BTB hits
2014-12-02 12:08:05 +01:00
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-05-31 12:07:18 +02:00
system.cpu0.branchPred.BTBHitPct 61.575961 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 18644167 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 188685 # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups 4389066 # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits 2747803 # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses 1641263 # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted 409141 # Number of mispredicted indirect branches.
2014-10-30 05:50:15 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-12-23 15:31:20 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.walker.walks 530338 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 530338 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10426 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79784 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 241995 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 288343 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean 2099.123266 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 12230.418976 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-65535 286535 99.37% 99.37% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-131071 1269 0.44% 99.81% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-196607 337 0.12% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-262143 138 0.05% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-327679 37 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-393215 22 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 288343 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 261783 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 19021.382214 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 16878.246550 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 10891.763559 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-32767 246122 94.02% 94.02% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-65535 14409 5.50% 99.52% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-98303 656 0.25% 99.77% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-131071 427 0.16% 99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-163839 44 0.02% 99.95% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::163840-196607 15 0.01% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-229375 47 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::229376-262143 25 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-294911 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::294912-327679 22 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-360447 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::360448-393215 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-425983 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 261783 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 513336492752 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.609866 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.537961 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1 512309669252 99.80% 99.80% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3 522001000 0.10% 99.90% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5 221126000 0.04% 99.94% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7 109873500 0.02% 99.97% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9 86703000 0.02% 99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11 51185000 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13 14405500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15 21121500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17 397500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::18-19 10500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 513336492752 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 79785 88.44% 88.44% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 10426 11.56% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 90211 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 530338 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 530338 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 90211 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 90211 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 620549 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.read_hits 99690232 # DTB read hits
system.cpu0.dtb.read_misses 367422 # DTB read misses
system.cpu0.dtb.write_hits 83046551 # DTB write hits
system.cpu0.dtb.write_misses 162916 # DTB write misses
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 35541 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 482 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 6442 # Number of TLB faults due to prefetch
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.perms_faults 39704 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 100057654 # DTB read accesses
system.cpu0.dtb.write_accesses 83209467 # DTB write accesses
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.hits 182736783 # DTB hits
system.cpu0.dtb.misses 530338 # DTB misses
system.cpu0.dtb.accesses 183267121 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-05-31 12:07:18 +02:00
system.cpu0.itb.walker.walks 81834 # Table walker walks requested
system.cpu0.itb.walker.walksLong 81834 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1030 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58824 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore 9805 # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples 72029 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean 864.033931 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 6165.525550 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-32767 71606 99.41% 99.41% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-65535 296 0.41% 99.82% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-98303 49 0.07% 99.89% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-131071 70 0.10% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-163839 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::163840-196607 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-229375 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::229376-262143 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 72029 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 69659 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 23684.893553 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 21955.996989 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 12765.700584 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-32767 63811 91.60% 91.60% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-65535 5242 7.53% 99.13% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-98303 100 0.14% 99.27% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::98304-131071 402 0.58% 99.85% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-163839 39 0.06% 99.91% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::163840-196607 17 0.02% 99.93% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-229375 16 0.02% 99.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::229376-262143 8 0.01% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::360448-393215 3 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 69659 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 375894589280 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 0.860066 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev 0.347066 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 52618427692 14.00% 14.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 323259257588 86.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2 15893500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3 943500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4 54500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::5 12500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 375894589280 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 58824 98.28% 98.28% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 1030 1.72% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 59854 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 81834 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 81834 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 59854 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 59854 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 141688 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 216521473 # ITB inst hits
system.cpu0.itb.inst_misses 81834 # ITB inst misses
2014-10-30 05:50:15 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
2016-05-31 12:07:18 +02:00
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
2014-10-30 05:50:15 +01:00
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-05-31 12:07:18 +02:00
system.cpu0.itb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 25342 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-05-31 12:07:18 +02:00
system.cpu0.itb.perms_faults 198402 # Number of TLB faults due to permissions restrictions
2014-10-30 05:50:15 +01:00
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
2016-05-31 12:07:18 +02:00
system.cpu0.itb.inst_accesses 216603307 # ITB inst accesses
system.cpu0.itb.hits 216521473 # DTB hits
system.cpu0.itb.misses 81834 # DTB misses
system.cpu0.itb.accesses 216603307 # DTB accesses
system.cpu0.numCycles 746014900 # number of cpu cycles simulated
2014-10-30 05:50:15 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-05-31 12:07:18 +02:00
system.cpu0.fetch.icacheStallCycles 90433879 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 610172736 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 138091637 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 81258280 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 615398287 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 14620490 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 1715297 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 295776 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 5589619 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 711520 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 813110 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 216323861 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 1696724 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 26704 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 722267733 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.989116 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 1.222569 # Number of instructions fetched each cycle (Total)
2014-10-30 05:50:15 +01:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-05-31 12:07:18 +02:00
system.cpu0.fetch.rateDist::0 380266002 52.65% 52.65% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 133082578 18.43% 71.07% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 45433566 6.29% 77.36% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 163485587 22.64% 100.00% # Number of instructions fetched each cycle (Total)
2014-10-30 05:50:15 +01:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2016-05-31 12:07:18 +02:00
system.cpu0.fetch.rateDist::total 722267733 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.185106 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.817910 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 106050198 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 344087060 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 231125881 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 35774912 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 5229682 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 19752919 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 2120005 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 632519077 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 23747295 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 5229682 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 140879480 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 46445701 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 235545365 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 231642525 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 62524980 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 614970268 # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts 6274841 # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents 9683853 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 239254 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 254272 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 29219197 # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents 11058 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 585821211 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 944611426 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 725501320 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 860588 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 527918401 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 57902804 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 14873386 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 12932012 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 72326353 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 100125445 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 86327833 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 8833111 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 7713299 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 593239093 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 14925406 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 596650262 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 2740149 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 54305512 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 35087941 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 259840 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 722267733 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.826079 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.071801 # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-05-31 12:07:18 +02:00
system.cpu0.iq.issued_per_cycle::0 398653423 55.19% 55.19% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 132668388 18.37% 73.56% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 116695962 16.16% 89.72% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 66414173 9.20% 98.92% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 7831504 1.08% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 4283 0.00% 100.00% # Number of insts issued each cycle
2015-03-02 11:04:20 +01:00
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2015-03-02 11:04:20 +01:00
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2016-05-31 12:07:18 +02:00
system.cpu0.iq.issued_per_cycle::total 722267733 # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-05-31 12:07:18 +02:00
system.cpu0.iq.fu_full::IntAlu 62572261 45.86% 45.86% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 47637 0.03% 45.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 27538 0.02% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 12 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 35025206 25.67% 71.58% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 38780691 28.42% 100.00% # attempts to use FU when none available
2014-10-30 05:50:15 +01:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2016-05-31 12:07:18 +02:00
system.cpu0.iq.FU_type_0::No_OpClass 37 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 408003074 68.38% 68.38% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 1391206 0.23% 68.62% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 75246 0.01% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 5 0.00% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 75513 0.01% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 102801955 17.23% 85.87% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 84303178 14.13% 100.00% # Type of FU issued
2014-10-30 05:50:15 +01:00
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-05-31 12:07:18 +02:00
system.cpu0.iq.FU_type_0::total 596650262 # Type of FU issued
system.cpu0.iq.rate 0.799783 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 136453345 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.228699 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 2053360508 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 662051351 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 579495604 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 1401241 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 556367 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 521179 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 732235238 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 868332 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 2674563 # Number of loads that had data forwarded from stores
2014-10-30 05:50:15 +01:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-05-31 12:07:18 +02:00
system.cpu0.iew.lsq.thread0.squashedLoads 12322480 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 16225 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 138716 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 5498195 # Number of stores squashed
2014-10-30 05:50:15 +01:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-05-31 12:07:18 +02:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 2627025 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 4349073 # Number of times an access to memory failed due to the cache being blocked
2014-10-30 05:50:15 +01:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-05-31 12:07:18 +02:00
system.cpu0.iew.iewSquashCycles 5229682 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 6015766 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 1577054 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 608291813 # Number of instructions dispatched to IQ
2014-10-30 05:50:15 +01:00
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2016-05-31 12:07:18 +02:00
system.cpu0.iew.iewDispLoadInsts 100125445 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 86327833 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 12661031 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 57348 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 1462300 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 138716 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 1920652 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 3139987 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 5060639 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 588583301 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 99681195 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 7546532 # Number of squashed instructions skipped in execute
2014-10-30 05:50:15 +01:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
2016-05-31 12:07:18 +02:00
system.cpu0.iew.exec_nop 127314 # number of nop insts executed
system.cpu0.iew.exec_refs 182727665 # number of memory reference insts executed
system.cpu0.iew.exec_branches 110905985 # Number of branches executed
system.cpu0.iew.exec_stores 83046470 # Number of stores executed
system.cpu0.iew.exec_rate 0.788970 # Inst execution rate
system.cpu0.iew.wb_sent 580785082 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 580016783 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 281571835 # num instructions producing a value
system.cpu0.iew.wb_consumers 462036259 # num instructions consuming a value
system.cpu0.iew.wb_rate 0.777487 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.609415 # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts 47239068 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 14665566 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 4709377 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 713265593 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.776512 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.575400 # Number of insts commited each cycle
2014-10-30 05:50:15 +01:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-05-31 12:07:18 +02:00
system.cpu0.commit.committed_per_cycle::0 472345396 66.22% 66.22% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 122854697 17.22% 83.45% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 54352038 7.62% 91.07% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 18530727 2.60% 93.67% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 13156863 1.84% 95.51% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 8843989 1.24% 96.75% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 5973723 0.84% 97.59% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 3646989 0.51% 98.10% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 13561171 1.90% 100.00% # Number of insts commited each cycle
2014-10-30 05:50:15 +01:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-05-31 12:07:18 +02:00
system.cpu0.commit.committed_per_cycle::total 713265593 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 471410910 # Number of instructions committed
system.cpu0.commit.committedOps 553858980 # Number of ops (including micro ops) committed
2014-10-30 05:50:15 +01:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
2016-05-31 12:07:18 +02:00
system.cpu0.commit.refs 168632602 # Number of memory references committed
system.cpu0.commit.loads 87802964 # Number of loads committed
system.cpu0.commit.membars 3653468 # Number of memory barriers committed
system.cpu0.commit.branches 105429162 # Number of branches committed
system.cpu0.commit.fp_insts 512997 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 508174699 # Number of committed integer instructions.
system.cpu0.commit.function_calls 13889214 # Number of function calls committed.
2014-10-30 05:50:15 +01:00
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2016-05-31 12:07:18 +02:00
system.cpu0.commit.op_class_0::IntAlu 383941234 69.32% 69.32% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 1156077 0.21% 69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 59954 0.01% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 69071 0.01% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 87802964 15.85% 85.41% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 80829638 14.59% 100.00% # Class of committed instruction
2014-10-30 05:50:15 +01:00
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-05-31 12:07:18 +02:00
system.cpu0.commit.op_class_0::total 553858980 # Class of committed instruction
system.cpu0.commit.bw_lim_events 13561171 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 1296549352 # The number of ROB reads
system.cpu0.rob.rob_writes 1211163120 # The number of ROB writes
system.cpu0.timesIdled 982435 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 23747167 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 94022615466 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 471410910 # Number of Instructions Simulated
system.cpu0.committedOps 553858980 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.582515 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.582515 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.631905 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.631905 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 694459704 # number of integer regfile reads
system.cpu0.int_regfile_writes 413089219 # number of integer regfile writes
system.cpu0.fp_regfile_reads 846069 # number of floating regfile reads
system.cpu0.fp_regfile_writes 429660 # number of floating regfile writes
system.cpu0.cc_regfile_reads 127998327 # number of cc regfile reads
system.cpu0.cc_regfile_writes 128742208 # number of cc regfile writes
system.cpu0.misc_regfile_reads 1288788249 # number of misc regfile reads
system.cpu0.misc_regfile_writes 14832406 # number of misc regfile writes
system.cpu0.dcache.tags.replacements 5793916 # number of replacements
system.cpu0.dcache.tags.tagsinuse 505.305765 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 157106373 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 5794427 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 27.113358 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 1908955000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.305765 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986925 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.986925 # Average percentage of cache occupancy
2016-04-09 18:13:40 +02:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
2016-04-09 18:13:40 +02:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.tags.tag_accesses 349540400 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 349540400 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 81616032 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 81616032 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 70522769 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 70522769 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 213045 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 213045 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259663 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 259663 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1810689 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 1810689 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1836259 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 1836259 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 152398464 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 152398464 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 152611509 # number of overall hits
system.cpu0.dcache.overall_hits::total 152611509 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 6448823 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 6448823 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 7191873 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 7191873 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 676181 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 676181 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 810826 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 810826 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 247493 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 247493 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 187335 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 187335 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 14451522 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 14451522 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 15127703 # number of overall misses
system.cpu0.dcache.overall_misses::total 15127703 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 92981912000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 92981912000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 133998931168 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 133998931168 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 29936196189 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 29936196189 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3415607500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 3415607500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4687136000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 4687136000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3788500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3788500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 256917039357 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 256917039357 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 256917039357 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 256917039357 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 88064855 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 88064855 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 77714642 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 77714642 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 889226 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 889226 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1070489 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 1070489 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2058182 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 2058182 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2023594 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 2023594 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 166849986 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 166849986 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 167739212 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 167739212 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.073228 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.073228 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.092542 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.092542 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760415 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760415 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.757435 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.757435 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.120248 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.120248 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.092575 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.092575 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086614 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.086614 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.090186 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.090186 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14418.431394 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14418.431394 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18631.993525 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 18631.993525 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 36920.616987 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 36920.616987 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13800.824670 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13800.824670 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25020.076334 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25020.076334 # average StoreCondReq miss latency
2014-12-02 12:08:05 +01:00
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17777.853389 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 17777.853389 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16983.215453 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 16983.215453 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 9060649 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 19650869 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 747322 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 698056 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.124157 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 28.150849 # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 5793928 # number of writebacks
system.cpu0.dcache.writebacks::total 5793928 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3323367 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 3323367 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5758852 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 5758852 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4670 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total 4670 # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 128237 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 128237 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 9086889 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 9086889 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 9086889 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 9086889 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3125456 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 3125456 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1433021 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 1433021 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 669278 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 669278 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 806156 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 806156 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 119256 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 119256 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 187331 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 187331 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 5364633 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 5364633 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 6033911 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 6033911 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32527 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32527 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32351 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32351 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 64878 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 64878 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43142423000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43142423000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30169010620 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 30169010620 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14964455000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14964455000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 28947099689 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 28947099689 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1564593500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1564593500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4499876000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4499876000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3717500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3717500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 102258533309 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 102258533309 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 117222988309 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 117222988309 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6208668000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6208668000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6208668000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6208668000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035490 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035490 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018440 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018440 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.752652 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.752652 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.753073 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.753073 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057942 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057942 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.092573 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.092573 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032152 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.032152 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.035972 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.035972 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13803.561144 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13803.561144 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21052.734482 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21052.734482 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22359.101898 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22359.101898 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 35907.565892 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 35907.565892 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13119.620816 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13119.620816 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24020.989585 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24020.989585 # average StoreCondReq mshr miss latency
2014-12-02 12:08:05 +01:00
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19061.608373 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19061.608373 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19427.364492 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19427.364492 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190877.363421 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190877.363421 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95697.586239 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95697.586239 # average overall mshr uncacheable latency
system.cpu0.icache.tags.replacements 6136519 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.962391 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 209807209 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 6137031 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 34.187086 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 12886295000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.962391 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999927 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999927 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-05-31 12:07:18 +02:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id
2014-10-30 05:50:15 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-05-31 12:07:18 +02:00
system.cpu0.icache.tags.tag_accesses 438728804 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 438728804 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 209807209 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 209807209 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 209807209 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 209807209 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 209807209 # number of overall hits
system.cpu0.icache.overall_hits::total 209807209 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 6488653 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 6488653 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 6488653 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 6488653 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 6488653 # number of overall misses
system.cpu0.icache.overall_misses::total 6488653 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 69596700450 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 69596700450 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 69596700450 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 69596700450 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 69596700450 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 69596700450 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 216295862 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 216295862 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 216295862 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 216295862 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 216295862 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 216295862 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029999 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.029999 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029999 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.029999 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029999 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.029999 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10725.908821 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10725.908821 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10725.908821 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10725.908821 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10725.908821 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10725.908821 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 10132412 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 436 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 737599 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 9 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.737020 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 48.444444 # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks 6136519 # number of writebacks
system.cpu0.icache.writebacks::total 6136519 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 351573 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 351573 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 351573 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 351573 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 351573 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 351573 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6137080 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 6137080 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 6137080 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 6137080 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 6137080 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 6137080 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses
2016-05-31 12:07:18 +02:00
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 62984871633 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 62984871633 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 62984871633 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 62984871633 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 62984871633 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 62984871633 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1885677498 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1885677498 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1885677498 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 1885677498 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028374 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028374 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028374 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.028374 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028374 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.028374 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10263.003193 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10263.003193 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10263.003193 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88558.563753 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88558.563753 # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.num_hwpf_issued 7743703 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 7754051 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 9277 # number of redundant prefetches already in prefetch queue
2014-12-23 15:31:20 +01:00
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2016-05-31 12:07:18 +02:00
system.cpu0.l2cache.prefetcher.pfSpanPage 1008365 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements 2565485 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 15956.741738 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 17408441 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 2581334 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 6.743971 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 2212473000 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 14849.648482 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 36.124813 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 23.448036 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000032 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1047.520376 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.906351 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002205 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001431 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063936 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.973922 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1203 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 77 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14569 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 211 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 564 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 414 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 59 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1288 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4722 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4695 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3741 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.073425 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.889221 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 408243228 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 408243228 # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 539952 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 183800 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 723752 # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks 3863126 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total 3863126 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks 8065215 # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total 8065215 # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 386 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 386 # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 6 # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total 6 # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 895474 # number of ReadExReq hits
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2016-04-21 10:48:24 +02:00
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2016-05-31 12:07:18 +02:00
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2016-04-21 10:48:24 +02:00
system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses
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2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses
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2016-05-31 12:07:18 +02:00
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998520 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998520 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999968 # miss rate for SCUpgradeReq accesses
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2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
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2016-05-31 12:07:18 +02:00
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system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 8094.282138 # average UpgradeReq miss latency
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2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-05-31 12:07:18 +02:00
system.cpu0.l2cache.blocked::no_mshrs 7 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2016-05-31 12:07:18 +02:00
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 56.428571 # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-05-31 12:07:18 +02:00
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2016-04-21 10:48:24 +02:00
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2016-05-31 12:07:18 +02:00
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system.cpu0.l2cache.overall_mshr_misses::total 2608303 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable
2016-05-31 12:07:18 +02:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32527 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 53820 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 32351 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 32351 # number of WriteReq MSHR uncacheable
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses
2016-05-31 12:07:18 +02:00
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 64878 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 86171 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 304850000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 201976000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 506826000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 36226481632 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 36226481632 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 5428667497 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 5428667497 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3091853999 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3091853999 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 3183499 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3183499 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11062749000 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11062749000 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 16630399500 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 16630399500 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 28032243476 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 28032243476 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 21947187999 # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 21947187999 # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 304850000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 201976000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 16630399500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 39094992476 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 56232217976 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 304850000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 201976000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 16630399500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 39094992476 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 36226481632 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 92458699608 # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1725979000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5947854500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7673833500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1725979000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5947854500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7673833500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.019556 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.039775 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.024771 # mshr miss rate for ReadReq accesses
2016-04-21 10:48:24 +02:00
system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses
system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses
system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2016-05-31 12:07:18 +02:00
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998520 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998520 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999968 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999968 # mshr miss rate for SCUpgradeReq accesses
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2016-05-31 12:07:18 +02:00
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.231953 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.231953 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.093508 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.093508 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.247573 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.247573 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.747519 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.747519 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.019556 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.039775 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.093508 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.243943 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.153253 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.019556 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.039775 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.093508 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.243943 # mshr miss rate for overall accesses
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
2016-05-31 12:07:18 +02:00
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.217839 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28305.478180 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 26526.924087 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27568.864230 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46845.335420 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46845.335420 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20843.655320 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20843.655320 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16505.909731 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16505.909731 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 454785.571429 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 454785.571429 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40291.912662 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40291.912662 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28979.940194 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28979.940194 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28953.724719 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28953.724719 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36518.816670 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36518.816670 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28305.478180 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 26526.924087 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28979.940194 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31458.731460 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30644.561078 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28305.478180 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 26526.924087 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28979.940194 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31458.731460 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46845.335420 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35447.837007 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182858.994066 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142583.305463 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91677.525509 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89053.550498 # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests 24754475 # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12719207 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2136 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops 1997962 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1997498 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 464 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq 885324 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 11040535 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 32352 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 32351 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty 5471965 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean 8067317 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict 2568559 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 991385 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp 10 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 475065 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 341372 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 522361 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 76 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 140 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 1216718 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 1192935 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6137080 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4901216 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq 866556 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp 803970 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18453192 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18807742 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 402695 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1170958 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 38834587 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 785846352 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 704525389 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1531416 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4405792 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 1496308949 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 6903738 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 20024554 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 0.116908 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.321383 # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-05-31 12:07:18 +02:00
system.cpu0.toL2Bus.snoop_fanout::0 17683990 88.31% 88.31% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 2340100 11.69% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 464 0.00% 100.00% # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-05-31 12:07:18 +02:00
system.cpu0.toL2Bus.snoop_fanout::total 20024554 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 24612511939 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy 212521499 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.cpu0.toL2Bus.respLayer0.occupancy 9233457820 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.cpu0.toL2Bus.respLayer1.occupancy 8324768239 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.cpu0.toL2Bus.respLayer2.occupancy 211573883 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.cpu0.toL2Bus.respLayer3.occupancy 620908635 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.cpu1.branchPred.lookups 127244460 # Number of BP lookups
system.cpu1.branchPred.condPredicted 83927531 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 6411720 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 89791062 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 55539581 # Number of BTB hits
2014-10-30 05:50:15 +01:00
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-05-31 12:07:18 +02:00
system.cpu1.branchPred.BTBHitPct 61.854242 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 17406269 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 177185 # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups 4036084 # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits 2495247 # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses 1540837 # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted 386993 # Number of mispredicted indirect branches.
2014-12-23 15:31:20 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-05-31 12:07:18 +02:00
system.cpu1.dtb.walker.walks 579824 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 579824 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 12232 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93540 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 278610 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 301214 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 2385.289196 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 13264.000730 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-65535 298702 99.17% 99.17% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-131071 1877 0.62% 99.79% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-196607 425 0.14% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::196608-262143 126 0.04% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-327679 47 0.02% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::327680-393215 33 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 301214 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 311038 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 20491.173104 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 17661.433181 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 17134.136599 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535 306887 98.67% 98.67% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071 3006 0.97% 99.63% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607 404 0.13% 99.76% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143 531 0.17% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679 109 0.04% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215 60 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751 29 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 311038 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 427436234332 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.596252 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.559035 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1 426093627832 99.69% 99.69% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3 733360500 0.17% 99.86% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5 289523500 0.07% 99.93% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7 124054000 0.03% 99.95% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9 101131500 0.02% 99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11 55199000 0.01% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13 17877500 0.00% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15 20812500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17 638500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::18-19 9500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 427436234332 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 93540 88.44% 88.44% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 12232 11.56% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 105772 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 579824 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 579824 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 105772 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 105772 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 685596 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
2016-05-31 12:07:18 +02:00
system.cpu1.dtb.read_hits 94100008 # DTB read hits
system.cpu1.dtb.read_misses 416726 # DTB read misses
system.cpu1.dtb.write_hits 75732153 # DTB write hits
system.cpu1.dtb.write_misses 163098 # DTB write misses
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-05-31 12:07:18 +02:00
system.cpu1.dtb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 40949 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 397 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 6052 # Number of TLB faults due to prefetch
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-05-31 12:07:18 +02:00
system.cpu1.dtb.perms_faults 38110 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 94516734 # DTB read accesses
system.cpu1.dtb.write_accesses 75895251 # DTB write accesses
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
2016-05-31 12:07:18 +02:00
system.cpu1.dtb.hits 169832161 # DTB hits
system.cpu1.dtb.misses 579824 # DTB misses
system.cpu1.dtb.accesses 170411985 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-05-31 12:07:18 +02:00
system.cpu1.itb.walker.walks 86146 # Table walker walks requested
system.cpu1.itb.walker.walksLong 86146 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 983 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61109 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore 10267 # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples 75879 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean 1365.727013 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 9905.301438 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-32767 74992 98.83% 98.83% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-65535 442 0.58% 99.41% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-98303 265 0.35% 99.76% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::98304-131071 132 0.17% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-163839 11 0.01% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::163840-196607 13 0.02% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::229376-262143 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::294912-327679 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 75879 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 72359 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 25927.458920 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 22905.536509 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 21012.178040 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535 70191 97.00% 97.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071 1833 2.53% 99.54% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607 132 0.18% 99.72% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143 128 0.18% 99.90% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679 41 0.06% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215 21 0.03% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287 7 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 72359 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 388687033168 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean 0.860499 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev 0.346749 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 54258161808 13.96% 13.96% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1 334394621860 86.03% 99.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2 32560000 0.01% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3 1626500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4 63000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 388687033168 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 61109 98.42% 98.42% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 983 1.58% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 62092 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 86146 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 86146 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62092 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62092 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 148238 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 200179962 # ITB inst hits
system.cpu1.itb.inst_misses 86146 # ITB inst misses
2014-10-30 05:50:15 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
2016-05-31 12:07:18 +02:00
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
2014-10-30 05:50:15 +01:00
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-05-31 12:07:18 +02:00
system.cpu1.itb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 29991 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-05-31 12:07:18 +02:00
system.cpu1.itb.perms_faults 205105 # Number of TLB faults due to permissions restrictions
2014-10-30 05:50:15 +01:00
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
2016-05-31 12:07:18 +02:00
system.cpu1.itb.inst_accesses 200266108 # ITB inst accesses
system.cpu1.itb.hits 200179962 # DTB hits
system.cpu1.itb.misses 86146 # DTB misses
system.cpu1.itb.accesses 200266108 # DTB accesses
system.cpu1.numCycles 683375860 # number of cpu cycles simulated
2014-10-30 05:50:15 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-05-31 12:07:18 +02:00
system.cpu1.fetch.icacheStallCycles 83886783 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 563469851 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 127244460 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 75441097 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 564344995 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 13807906 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 2007349 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 258832 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 5872913 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 777107 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 768148 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 199953853 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 1622392 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 27919 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 664820080 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.994147 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 1.223667 # Number of instructions fetched each cycle (Total)
2014-10-30 05:50:15 +01:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-05-31 12:07:18 +02:00
system.cpu1.fetch.rateDist::0 348468390 52.42% 52.42% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 123001690 18.50% 70.92% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 42123132 6.34% 77.25% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 151226868 22.75% 100.00% # Number of instructions fetched each cycle (Total)
2014-10-30 05:50:15 +01:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2016-05-31 12:07:18 +02:00
system.cpu1.fetch.rateDist::total 664820080 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.186200 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.824539 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 100313259 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 315334519 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 208757120 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 35486026 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 4929156 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 17976704 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 2012194 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 582722672 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 22029645 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 4929156 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 133756265 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 43242401 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 214462360 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 210347945 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 58081953 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 566482483 # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts 5736321 # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents 9739688 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 342221 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 843279 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 24527700 # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents 11906 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 538415916 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 871757488 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 668460678 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 644937 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 483561743 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 54854172 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 15093428 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 13190698 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 71341154 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 94469141 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 78816060 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 9208116 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 7878049 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 544809829 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 15364466 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 549398452 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 2550658 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 51789954 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 33366441 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 282362 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 664820080 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.826387 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.065764 # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-05-31 12:07:18 +02:00
system.cpu1.iq.issued_per_cycle::0 363096071 54.62% 54.62% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 129026402 19.41% 74.02% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 104942160 15.79% 89.81% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 60539163 9.11% 98.91% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 7211179 1.08% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 5105 0.00% 100.00% # Number of insts issued each cycle
2014-12-23 15:31:20 +01:00
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2014-12-23 15:31:20 +01:00
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2016-05-31 12:07:18 +02:00
system.cpu1.iq.issued_per_cycle::total 664820080 # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-05-31 12:07:18 +02:00
system.cpu1.iq.fu_full::IntAlu 54936992 44.00% 44.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 69872 0.06% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 6570 0.01% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 17 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 34367116 27.52% 71.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 35481157 28.42% 100.00% # attempts to use FU when none available
2014-10-30 05:50:15 +01:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2016-04-21 10:48:24 +02:00
system.cpu1.iq.FU_type_0::No_OpClass 56 0.00% 0.00% # Type of FU issued
2016-05-31 12:07:18 +02:00
system.cpu1.iq.FU_type_0::IntAlu 373883416 68.05% 68.05% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 1335155 0.24% 68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 74884 0.01% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 11 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 48854 0.01% 68.32% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.32% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.32% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.32% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 97153433 17.68% 86.00% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 76902643 14.00% 100.00% # Type of FU issued
2014-10-30 05:50:15 +01:00
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-05-31 12:07:18 +02:00
system.cpu1.iq.FU_type_0::total 549398452 # Type of FU issued
system.cpu1.iq.rate 0.803948 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 124861724 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.227270 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 1889962970 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 611689245 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 533047508 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 1066396 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 424008 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 393622 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 673596915 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 663205 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 2524444 # Number of loads that had data forwarded from stores
2014-10-30 05:50:15 +01:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-05-31 12:07:18 +02:00
system.cpu1.iew.lsq.thread0.squashedLoads 12144847 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 16403 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 149896 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 5262071 # Number of stores squashed
2014-10-30 05:50:15 +01:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-05-31 12:07:18 +02:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 2572719 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 4009144 # Number of times an access to memory failed due to the cache being blocked
2014-10-30 05:50:15 +01:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-05-31 12:07:18 +02:00
system.cpu1.iew.iewSquashCycles 4929156 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 7182655 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 1646879 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 560304926 # Number of instructions dispatched to IQ
2014-10-30 05:50:15 +01:00
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2016-05-31 12:07:18 +02:00
system.cpu1.iew.iewDispLoadInsts 94469141 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 78816060 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 12974148 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 56258 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 1524659 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 149896 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 1843431 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 2924818 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 4768249 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 541845400 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 94094962 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 6980663 # Number of squashed instructions skipped in execute
2014-10-30 05:50:15 +01:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
2016-05-31 12:07:18 +02:00
system.cpu1.iew.exec_nop 130631 # number of nop insts executed
system.cpu1.iew.exec_refs 169824676 # number of memory reference insts executed
system.cpu1.iew.exec_branches 101510793 # Number of branches executed
system.cpu1.iew.exec_stores 75729714 # Number of stores executed
system.cpu1.iew.exec_rate 0.792895 # Inst execution rate
system.cpu1.iew.wb_sent 534152020 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 533441130 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 258912640 # num instructions producing a value
system.cpu1.iew.wb_consumers 423656459 # num instructions consuming a value
system.cpu1.iew.wb_rate 0.780597 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.611138 # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts 45293147 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 15082103 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 4436923 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 656213363 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.774724 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.573400 # Number of insts commited each cycle
2014-10-30 05:50:15 +01:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-05-31 12:07:18 +02:00
system.cpu1.commit.committed_per_cycle::0 432598016 65.92% 65.92% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 117091486 17.84% 83.77% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 49126445 7.49% 91.25% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 16229930 2.47% 93.73% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 11628277 1.77% 95.50% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 8033144 1.22% 96.72% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 5546832 0.85% 97.57% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 3283510 0.50% 98.07% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 12675723 1.93% 100.00% # Number of insts commited each cycle
2014-10-30 05:50:15 +01:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-05-31 12:07:18 +02:00
system.cpu1.commit.committed_per_cycle::total 656213363 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 431870837 # Number of instructions committed
system.cpu1.commit.committedOps 508384340 # Number of ops (including micro ops) committed
2014-10-30 05:50:15 +01:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
2016-05-31 12:07:18 +02:00
system.cpu1.commit.refs 155878283 # Number of memory references committed
system.cpu1.commit.loads 82324294 # Number of loads committed
system.cpu1.commit.membars 3722309 # Number of memory barriers committed
system.cpu1.commit.branches 96290107 # Number of branches committed
system.cpu1.commit.fp_insts 384716 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 467163355 # Number of committed integer instructions.
system.cpu1.commit.function_calls 12903273 # Number of function calls committed.
2014-10-30 05:50:15 +01:00
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2016-05-31 12:07:18 +02:00
system.cpu1.commit.op_class_0::IntAlu 351312000 69.10% 69.10% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 1092238 0.21% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 59391 0.01% 69.33% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.33% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.33% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.33% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.33% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.33% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.33% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 42428 0.01% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 82324294 16.19% 85.53% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 73553989 14.47% 100.00% # Class of committed instruction
2014-10-30 05:50:15 +01:00
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-05-31 12:07:18 +02:00
system.cpu1.commit.op_class_0::total 508384340 # Class of committed instruction
system.cpu1.commit.bw_lim_events 12675723 # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads 1193390155 # The number of ROB reads
system.cpu1.rob.rob_writes 1115923607 # The number of ROB writes
system.cpu1.timesIdled 934929 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 18555780 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 94085254498 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 431870837 # Number of Instructions Simulated
system.cpu1.committedOps 508384340 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 1.582362 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.582362 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.631967 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.631967 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 639570382 # number of integer regfile reads
system.cpu1.int_regfile_writes 380109427 # number of integer regfile writes
system.cpu1.fp_regfile_reads 631427 # number of floating regfile reads
system.cpu1.fp_regfile_writes 338972 # number of floating regfile writes
system.cpu1.cc_regfile_reads 115255782 # number of cc regfile reads
system.cpu1.cc_regfile_writes 115917819 # number of cc regfile writes
system.cpu1.misc_regfile_reads 1185795918 # number of misc regfile reads
system.cpu1.misc_regfile_writes 15045931 # number of misc regfile writes
system.cpu1.dcache.tags.replacements 5420466 # number of replacements
system.cpu1.dcache.tags.tagsinuse 437.277482 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 144971712 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 5420977 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 26.742728 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 8477404255000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 437.277482 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.854058 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.854058 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 323922794 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 323922794 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 76466425 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 76466425 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 64110613 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 64110613 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 170428 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 170428 # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data 51164 # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total 51164 # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1700918 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 1700918 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1741756 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 1741756 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 140628202 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 140628202 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 140798630 # number of overall hits
system.cpu1.dcache.overall_hits::total 140798630 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 6372316 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 6372316 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 7014697 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 7014697 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 658076 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 658076 # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data 445973 # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total 445973 # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 278553 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 278553 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193453 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 193453 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 13832986 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 13832986 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 14491062 # number of overall misses
system.cpu1.dcache.overall_misses::total 14491062 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 93736923500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 93736923500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 131113304741 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 131113304741 # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11858807099 # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total 11858807099 # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4107251000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 4107251000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4806521000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 4806521000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3714500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3714500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 236709035340 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 236709035340 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 236709035340 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 236709035340 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 82838741 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 82838741 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 71125310 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 71125310 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 828504 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 828504 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 497137 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total 497137 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1979471 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 1979471 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1935209 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 1935209 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 154461188 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 154461188 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 155289692 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 155289692 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.076924 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.076924 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.098624 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.098624 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.794294 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.794294 # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.897083 # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total 0.897083 # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.140721 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.140721 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099965 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099965 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.089556 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.089556 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.093316 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.093316 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14710.024346 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14710.024346 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18691.228536 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 18691.228536 # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 26590.863346 # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 26590.863346 # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14744.953384 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14744.953384 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24845.936739 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24845.936739 # average StoreCondReq miss latency
2014-12-02 12:08:05 +01:00
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2016-05-31 12:07:18 +02:00
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17111.926184 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 17111.926184 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16334.830072 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 16334.830072 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 3137293 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 21285332 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 376632 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 706469 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.329863 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 30.129180 # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks 5420571 # number of writebacks
system.cpu1.dcache.writebacks::total 5420571 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3225514 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 3225514 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5658563 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 5658563 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3397 # number of WriteLineReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::total 3397 # number of WriteLineReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 142581 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 142581 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 8887474 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 8887474 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 8887474 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 8887474 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3146802 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 3146802 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1356134 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 1356134 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 657988 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 657988 # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 442576 # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total 442576 # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 135972 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 135972 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193443 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 193443 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 4945512 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 4945512 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 5603500 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 5603500 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6118 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6118 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 6183 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 6183 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 12301 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 12301 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 43613350000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 43613350000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26794309953 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26794309953 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14059014500 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14059014500 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 11316204599 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 11316204599 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1866790500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1866790500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4613147000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4613147000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3645500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3645500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 81723864552 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 81723864552 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 95782879052 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 95782879052 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 749898500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 749898500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 749898500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 749898500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037987 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037987 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019067 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019067 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.794188 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.794188 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.890250 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.890250 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068691 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068691 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.099960 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.099960 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032018 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.032018 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.036084 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.036084 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13859.578709 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13859.578709 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19757.863126 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19757.863126 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21366.673100 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21366.673100 # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 25568.952223 # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 25568.952223 # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13729.227341 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13729.227341 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23847.577839 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23847.577839 # average StoreCondReq mshr miss latency
2014-12-02 12:08:05 +01:00
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2016-05-31 12:07:18 +02:00
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16524.854161 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16524.854161 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17093.402169 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17093.402169 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122572.491010 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 122572.491010 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 60962.401431 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 60962.401431 # average overall mshr uncacheable latency
system.cpu1.icache.tags.replacements 5742782 # number of replacements
system.cpu1.icache.tags.tagsinuse 501.536552 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 193871102 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 5743294 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 33.756082 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 8517126060000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.536552 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979564 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.979564 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-05-31 12:07:18 +02:00
system.cpu1.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 396 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id
2014-10-30 05:50:15 +01:00
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-05-31 12:07:18 +02:00
system.cpu1.icache.tags.tag_accesses 405638078 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 405638078 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 193871102 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 193871102 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 193871102 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 193871102 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 193871102 # number of overall hits
system.cpu1.icache.overall_hits::total 193871102 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 6076268 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 6076268 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 6076268 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 6076268 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 6076268 # number of overall misses
system.cpu1.icache.overall_misses::total 6076268 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 64119298557 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 64119298557 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 64119298557 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 64119298557 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 64119298557 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 64119298557 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 199947370 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 199947370 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 199947370 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 199947370 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 199947370 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 199947370 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030389 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.030389 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030389 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.030389 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030389 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.030389 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10552.414501 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10552.414501 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10552.414501 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10552.414501 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10552.414501 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10552.414501 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 9320412 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 212 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 713481 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 3 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.063294 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets 70.666667 # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks 5742782 # number of writebacks
system.cpu1.icache.writebacks::total 5742782 # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 332930 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 332930 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 332930 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 332930 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 332930 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 332930 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5743338 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 5743338 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 5743338 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 5743338 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 5743338 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 5743338 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses
2016-05-31 12:07:18 +02:00
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 58166889552 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 58166889552 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 58166889552 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 58166889552 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 58166889552 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 58166889552 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6789498 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6789498 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6789498 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 6789498 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028724 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028724 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028724 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.028724 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028724 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.028724 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10127.714850 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 10127.714850 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 10127.714850 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101335.791045 # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101335.791045 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101335.791045 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101335.791045 # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.num_hwpf_issued 7416585 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 7422175 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 5069 # number of redundant prefetches already in prefetch queue
2014-12-23 15:31:20 +01:00
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2016-05-31 12:07:18 +02:00
system.cpu1.l2cache.prefetcher.pfSpanPage 930081 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements 2216875 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 13443.573819 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 16807540 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 2232789 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 7.527599 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 9871196159000 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 12560.451650 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 62.875087 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 63.205555 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 757.041527 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.766629 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003838 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003858 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.046206 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.820531 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1320 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 67 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14527 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 25 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 72 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 117 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 681 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 425 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1030 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5623 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4561 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3143 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.080566 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004089 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.886658 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 383680582 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 383680582 # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 591753 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 193382 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 785135 # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks 3353025 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total 3353025 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks 7809020 # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total 7809020 # number of WritebackClean hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 779 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 779 # number of UpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 872441 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 872441 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5195235 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 5195235 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2967964 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 2967964 # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 177430 # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total 177430 # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 591753 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 193382 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 5195235 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 3840405 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 9820775 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 591753 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 193382 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 5195235 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 3840405 # number of overall hits
system.cpu1.l2cache.overall_hits::total 9820775 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 13125 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9784 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 22909 # number of ReadReq misses
system.cpu1.l2cache.WritebackDirty_misses::writebacks 2 # number of WritebackDirty misses
system.cpu1.l2cache.WritebackDirty_misses::total 2 # number of WritebackDirty misses
2016-02-24 10:16:59 +01:00
system.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses
system.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses
2016-05-31 12:07:18 +02:00
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 227942 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 227942 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 193439 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 193439 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 262152 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 262152 # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 548077 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total 548077 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 970504 # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total 970504 # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 263582 # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total 263582 # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 13125 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9784 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 548077 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 1232656 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 1803642 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 13125 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9784 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 548077 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 1232656 # number of overall misses
system.cpu1.l2cache.overall_misses::total 1803642 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 561719500 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 455404000 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 1017123500 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 1976830000 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 1976830000 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1436047000 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1436047000 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3542000 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3542000 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12377259499 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 12377259499 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 18066070500 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total 18066070500 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 33827571986 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total 33827571986 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 317775500 # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total 317775500 # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 561719500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 455404000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 18066070500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 46204831485 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 65288025485 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 561719500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 455404000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 18066070500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 46204831485 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 65288025485 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 604878 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 203166 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 808044 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3353027 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total 3353027 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks 7809021 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total 7809021 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 228721 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 228721 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 193439 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 193439 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1134593 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 1134593 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5743312 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total 5743312 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3938468 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total 3938468 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 441012 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total 441012 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 604878 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 203166 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 5743312 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 5073061 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 11624417 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 604878 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 203166 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 5743312 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 5073061 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 11624417 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021699 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048158 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.028351 # miss rate for ReadReq accesses
system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses
2016-02-24 10:16:59 +01:00
system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses
system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses
2016-05-31 12:07:18 +02:00
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.996594 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.996594 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2016-05-31 12:07:18 +02:00
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.231054 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.231054 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.095429 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.095429 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.246417 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.246417 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.597675 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.597675 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021699 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048158 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.095429 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.242981 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.155160 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021699 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048158 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.095429 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.242981 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.155160 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 42797.676190 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 46545.789043 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 44398.424200 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 8672.513183 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 8672.513183 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 7423.771835 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 7423.771835 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 885500 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 885500 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 47214.057108 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 47214.057108 # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 32962.650321 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 32962.650321 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 34855.674975 # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 34855.674975 # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1205.603949 # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1205.603949 # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 42797.676190 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 46545.789043 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32962.650321 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 37483.962667 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 36197.884882 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 42797.676190 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 46545.789043 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32962.650321 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 37483.962667 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 36197.884882 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 860 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-05-31 12:07:18 +02:00
system.cpu1.l2cache.blocked::no_mshrs 17 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2016-05-31 12:07:18 +02:00
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 50.588235 # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-05-31 12:07:18 +02:00
system.cpu1.l2cache.unused_prefetches 44363 # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks 1196648 # number of writebacks
system.cpu1.l2cache.writebacks::total 1196648 # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 8 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 12956 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 12956 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 4132 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 4132 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 5 # number of InvalidateReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::total 5 # number of InvalidateReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 8 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 17088 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total 17097 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 8 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 17088 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 17097 # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 13124 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9776 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total 22900 # number of ReadReq MSHR misses
system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 2 # number of WritebackDirty MSHR misses
system.cpu1.l2cache.WritebackDirty_mshr_misses::total 2 # number of WritebackDirty MSHR misses
2016-02-24 10:16:59 +01:00
system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses
system.cpu1.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses
2016-05-31 12:07:18 +02:00
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 773530 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 773530 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 227942 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 227942 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 193439 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 193439 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 4 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 249196 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total 249196 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 548077 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 548077 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 966372 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 966372 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 263577 # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total 263577 # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 13124 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9776 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 548077 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1215568 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total 1786545 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 13124 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9776 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 548077 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1215568 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 773530 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total 2560075 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
2016-05-31 12:07:18 +02:00
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 6118 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 6185 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 6183 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 6183 # number of WriteReq MSHR uncacheable
2015-05-05 09:22:39 +02:00
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
2016-05-31 12:07:18 +02:00
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 12301 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 12368 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 482957500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 396613500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 879571000 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 40678992877 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 40678992877 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4718335995 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4718335995 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3159514995 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3159514995 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3128000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3128000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8998543499 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8998543499 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14777608500 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14777608500 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 27796571986 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 27796571986 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 7398469497 # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 7398469497 # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 482957500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 396613500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14777608500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 36795115485 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 52452294985 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 482957500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 396613500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14777608500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 36795115485 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 40678992877 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 93131287862 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6286000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 700808000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 707094000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6286000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 700808000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 707094000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021697 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048118 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.028340 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses
2016-02-24 10:16:59 +01:00
system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses
system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2016-05-31 12:07:18 +02:00
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.996594 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.996594 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2016-05-31 12:07:18 +02:00
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.219635 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.219635 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.095429 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.095429 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.245367 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.245367 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.597664 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.597664 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021697 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048118 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.095429 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.239612 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153689 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021697 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048118 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.095429 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.239612 # mshr miss rate for overall accesses
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2016-05-31 12:07:18 +02:00
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.220233 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 36799.565681 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40570.120704 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 38409.213974 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 52588.772093 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 52588.772093 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20699.721837 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20699.721837 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16333.391896 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16333.391896 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 782000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 782000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36110.304736 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36110.304736 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26962.650321 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26962.650321 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28763.842481 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28763.842481 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 28069.480634 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 28069.480634 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 36799.565681 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 40570.120704 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26962.650321 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 30269.894802 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29359.627093 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 36799.565681 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 40570.120704 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26962.650321 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 30269.894802 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 52588.772093 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36378.343549 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93820.895522 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 114548.545276 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114324.009701 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93820.895522 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 56971.628323 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 57171.248383 # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests 23197310 # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11940096 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1305 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops 1942556 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1942287 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 269 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq 900600 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 10671947 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 6183 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 6183 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty 4554023 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean 7810324 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict 2589255 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 981692 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 441382 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 342905 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 485827 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 140 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 1162425 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 1140502 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5743338 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4866994 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 495411 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp 441012 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17229566 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17476902 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 425595 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1276864 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 36408927 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 735111088 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 677743701 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1625328 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4839024 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 1419319141 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 6390553 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 18731260 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 0.122712 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.328150 # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-05-31 12:07:18 +02:00
system.cpu1.toL2Bus.snoop_fanout::0 16432977 87.73% 87.73% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 2298014 12.27% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 269 0.00% 100.00% # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-05-31 12:07:18 +02:00
system.cpu1.toL2Bus.snoop_fanout::total 18731260 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 23041315974 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy 175324271 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.cpu1.toL2Bus.respLayer0.occupancy 8621166733 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.cpu1.toL2Bus.respLayer1.occupancy 8059431425 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.cpu1.toL2Bus.respLayer2.occupancy 222762323 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.cpu1.toL2Bus.respLayer3.occupancy 672656647 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.trans_dist::ReadReq 40341 # Transaction distribution
system.iobus.trans_dist::ReadResp 40341 # Transaction distribution
system.iobus.trans_dist::WriteReq 136646 # Transaction distribution
system.iobus.trans_dist::WriteResp 136646 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47790 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.iobus.pkt_count_system.bridge.master::total 122672 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231222 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231222 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.iobus.pkt_count::total 353974 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47810 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.iobus.pkt_size_system.bridge.master::total 155802 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338904 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7338904 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.iobus.pkt_size::total 7496792 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 37061004 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer2.occupancy 323500 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-04-21 10:48:24 +02:00
system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer23.occupancy 24283001 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer24.occupancy 36403501 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer25.occupancy 569028004 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.respLayer0.occupancy 92757000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.respLayer3.occupancy 147918000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-07-03 16:15:03 +02:00
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iocache.tags.replacements 115592 # number of replacements
system.iocache.tags.tagsinuse 11.302694 # Cycle average of tags in use
2015-12-05 01:11:25 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2016-05-31 12:07:18 +02:00
system.iocache.tags.sampled_refs 115608 # Sample count of references to valid blocks.
2015-12-05 01:11:25 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2016-05-31 12:07:18 +02:00
system.iocache.tags.warmup_cycle 9115775800000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.842796 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 7.459898 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.240175 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.466244 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.706418 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2016-05-31 12:07:18 +02:00
system.iocache.tags.tag_accesses 1040856 # Number of tag accesses
system.iocache.tags.data_accesses 1040856 # Number of data accesses
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2016-05-31 12:07:18 +02:00
system.iocache.ReadReq_misses::realview.ide 8883 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8920 # number of ReadReq misses
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2016-05-31 12:07:18 +02:00
system.iocache.demand_misses::realview.ide 115611 # number of demand (read+write) misses
system.iocache.demand_misses::total 115651 # number of demand (read+write) misses
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2016-05-31 12:07:18 +02:00
system.iocache.overall_misses::realview.ide 115611 # number of overall misses
system.iocache.overall_misses::total 115651 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5246000 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1667860010 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1673106010 # number of ReadReq miss cycles
2015-07-30 09:42:27 +02:00
system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
2016-05-31 12:07:18 +02:00
system.iocache.WriteLineReq_miss_latency::realview.ide 12956345994 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 12956345994 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5615000 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 14624206004 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 14629821004 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5615000 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 14624206004 # number of overall miss cycles
system.iocache.overall_miss_latency::total 14629821004 # number of overall miss cycles
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2016-05-31 12:07:18 +02:00
system.iocache.ReadReq_accesses::realview.ide 8883 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8920 # number of ReadReq accesses(hits+misses)
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2016-05-31 12:07:18 +02:00
system.iocache.demand_accesses::realview.ide 115611 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 115651 # number of demand (read+write) accesses
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2016-05-31 12:07:18 +02:00
system.iocache.overall_accesses::realview.ide 115611 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 115651 # number of overall (read+write) accesses
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2016-05-31 12:07:18 +02:00
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141783.783784 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 187758.641225 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 187567.938341 # average ReadReq miss latency
2015-07-30 09:42:27 +02:00
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
2016-05-31 12:07:18 +02:00
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121395.941028 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 121395.941028 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 140375 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 126494.935638 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 126499.736310 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 140375 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 126494.935638 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 126499.736310 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 33436 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-05-31 12:07:18 +02:00
system.iocache.blocked::no_mshrs 3541 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2016-05-31 12:07:18 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 9.442530 # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-04-21 10:48:24 +02:00
system.iocache.writebacks::writebacks 106694 # number of writebacks
system.iocache.writebacks::total 106694 # number of writebacks
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2016-05-31 12:07:18 +02:00
system.iocache.ReadReq_mshr_misses::realview.ide 8883 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8920 # number of ReadReq MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2016-05-31 12:07:18 +02:00
system.iocache.demand_mshr_misses::realview.ide 115611 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 115651 # number of demand (read+write) MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2016-05-31 12:07:18 +02:00
system.iocache.overall_mshr_misses::realview.ide 115611 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 115651 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3396000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1223710010 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1227106010 # number of ReadReq MSHR miss cycles
2015-07-30 09:42:27 +02:00
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
2016-05-31 12:07:18 +02:00
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7611309187 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 7611309187 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3615000 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 8835019197 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8838634197 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3615000 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 8835019197 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8838634197 # number of overall MSHR miss cycles
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2016-05-31 12:07:18 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 91783.783784 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137758.641225 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 137567.938341 # average ReadReq mshr miss latency
2015-07-30 09:42:27 +02:00
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
2016-05-31 12:07:18 +02:00
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71315.017493 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71315.017493 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90375 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 76420.229883 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 76425.056394 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90375 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 76420.229883 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76425.056394 # average overall mshr miss latency
system.l2c.tags.replacements 1423185 # number of replacements
system.l2c.tags.tagsinuse 63448.336905 # Cycle average of tags in use
system.l2c.tags.total_refs 6060449 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1482600 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 4.087717 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 3022937500 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 20826.975184 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.832374 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 12.742051 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 3854.622142 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 3569.542843 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 2315.690288 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 335.622211 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 552.279614 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 2996.807733 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 11095.009846 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17872.212619 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.317794 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000257 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000194 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.058817 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.054467 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.035335 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005121 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.008427 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.045728 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.169296 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.272708 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.968145 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 10702 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 222 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 48491 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::0 11 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 1377 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 482 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 8826 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 218 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2760 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 5614 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 39761 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.163300 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.003387 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.739914 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 76659871 # Number of tag accesses
system.l2c.tags.data_accesses 76659871 # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks 2799563 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 2799563 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data 175772 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 127713 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 303485 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 39800 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 41169 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 80969 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 55176 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 52470 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 107646 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6441 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4632 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 512914 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 602529 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 321191 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6205 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4222 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 506602 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 564191 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 285940 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 2814867 # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data 134470 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data 123510 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total 257980 # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker 6441 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 4632 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 512914 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 657705 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 321191 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 6205 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 4222 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 506602 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 616661 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 285940 # number of demand (read+write) hits
system.l2c.demand_hits::total 2922513 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 6441 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 4632 # number of overall hits
system.l2c.overall_hits::cpu0.inst 512914 # number of overall hits
system.l2c.overall_hits::cpu0.data 657705 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 321191 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 6205 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 4222 # number of overall hits
system.l2c.overall_hits::cpu1.inst 506602 # number of overall hits
system.l2c.overall_hits::cpu1.data 616661 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 285940 # number of overall hits
system.l2c.overall_hits::total 2922513 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 65800 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 60076 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 125876 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 12292 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 11651 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 23943 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 76423 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 57499 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 133922 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1380 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 911 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst 60940 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 127468 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 217255 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3149 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2958 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst 41472 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 123752 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 256869 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 836154 # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data 453643 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data 128024 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total 581667 # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker 1380 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 911 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 60940 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 203891 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 217255 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 3149 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 2958 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 41472 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 181251 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher 256869 # number of demand (read+write) misses
system.l2c.demand_misses::total 970076 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 1380 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 911 # number of overall misses
system.l2c.overall_misses::cpu0.inst 60940 # number of overall misses
system.l2c.overall_misses::cpu0.data 203891 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 217255 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 3149 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 2958 # number of overall misses
system.l2c.overall_misses::cpu1.inst 41472 # number of overall misses
system.l2c.overall_misses::cpu1.data 181251 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 256869 # number of overall misses
system.l2c.overall_misses::total 970076 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data 448544000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 390663000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 839207000 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 74504000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 75234500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 149738500 # number of SCUpgradeReq miss cycles
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system.l2c.blocked_cycles::no_mshrs 9550 # number of cycles access was blocked
2014-12-02 12:08:05 +01:00
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.l2c.blocked::no_targets 0 # number of cycles access was blocked
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system.l2c.avg_blocked_cycles::no_mshrs 93.627451 # average number of cycles each access was blocked
2014-12-02 12:08:05 +01:00
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 256869 # number of demand (read+write) MSHR misses
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system.l2c.overall_mshr_misses::cpu0.dtb.walker 1380 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 911 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 60829 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 203871 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 217255 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 3149 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker 2958 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 41363 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 181243 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 256869 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 969828 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable
2016-05-31 12:07:18 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32527 # number of ReadReq MSHR uncacheable
2015-05-05 09:22:39 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
2016-05-31 12:07:18 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 6116 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 60003 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 32351 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 6183 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 38534 # number of WriteReq MSHR uncacheable
2015-11-06 09:26:50 +01:00
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses
2016-05-31 12:07:18 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 64878 # number of overall MSHR uncacheable misses
2015-05-05 09:22:39 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
2016-05-31 12:07:18 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 12299 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 98537 # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1434481502 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 1290497995 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 2724979497 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 303964499 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 285788496 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 589752995 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6173210845 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4623959192 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 10797170037 # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 118145502 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 76067500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 4704505587 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 10752452984 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 28346572172 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 258517505 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 236065501 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 3231267055 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 10692827748 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 32803939514 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 91220361068 # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 11449259098 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2669880500 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total 14119139598 # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 118145502 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 76067500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 4704505587 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 16925663829 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 28346572172 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 258517505 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 236065501 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 3231267055 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 15316786940 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 32803939514 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 102017531105 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 118145502 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 76067500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 4704505587 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 16925663829 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 28346572172 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 258517505 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 236065501 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 3231267055 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 15316786940 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 32803939514 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 102017531105 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1342704500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5362205005 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5079500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 590567503 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 7300556508 # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1342704500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5362205005 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5079500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 590567503 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 7300556508 # number of overall MSHR uncacheable cycles
2015-07-03 16:15:03 +02:00
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2016-05-31 12:07:18 +02:00
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.272383 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.319912 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.293171 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.235967 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.220579 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.228220 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.580726 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.522866 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.554386 # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.176448 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.164351 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.106001 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.174587 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403485 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.336647 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.411978 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.075470 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.179875 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.473222 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.228951 # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.771353 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.508973 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total 0.692752 # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.176448 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.164351 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.106001 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.236620 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403485 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.336647 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.411978 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.075470 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.227147 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.473222 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.249147 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.176448 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.164351 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.106001 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.236620 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403485 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.336647 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.411978 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.075470 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.227147 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.473222 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.249147 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21800.630729 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21481.090535 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21648.125910 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24728.644566 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24529.095872 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24631.541369 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80776.871426 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 80418.080175 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 80622.825503 # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 85612.682609 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 83498.902305 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 77339.847556 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 84367.373235 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130476.040469 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82095.111146 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 79805.781271 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 78119.746029 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 86410.878491 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 127706.883719 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 109127.534756 # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 25238.478491 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20854.531182 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 24273.578522 # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 85612.682609 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 83498.902305 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 77339.847556 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83021.439189 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130476.040469 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82095.111146 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79805.781271 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 78119.746029 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 84509.674525 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 127706.883719 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 105191.364969 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 85612.682609 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 83498.902305 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 77339.847556 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83021.439189 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130476.040469 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82095.111146 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79805.781271 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 78119.746029 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 84509.674525 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 127706.883719 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 105191.364969 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164853.967627 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 75813.432836 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 96561.069817 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 121669.858307 # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82650.590416 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 75813.432836 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 48017.521994 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 74089.494383 # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests 3952559 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 2414080 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 2931 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.trans_dist::ReadReq 60003 # Transaction distribution
system.membus.trans_dist::ReadResp 904829 # Transaction distribution
system.membus.trans_dist::WriteReq 38534 # Transaction distribution
system.membus.trans_dist::WriteResp 38534 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1242017 # Transaction distribution
system.membus.trans_dist::CleanEvict 238236 # Transaction distribution
system.membus.trans_dist::UpgradeReq 446737 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 299659 # Transaction distribution
2016-04-21 10:48:24 +02:00
system.membus.trans_dist::UpgradeResp 23 # Transaction distribution
2016-05-31 12:07:18 +02:00
system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
system.membus.trans_dist::ReadExReq 144708 # Transaction distribution
system.membus.trans_dist::ReadExResp 128413 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 844826 # Transaction distribution
system.membus.trans_dist::InvalidateReq 684897 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122672 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26462 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4681290 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4830500 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238195 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 238195 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 5068695 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155802 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52924 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 134692416 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 134901698 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7273344 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7273344 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 142175042 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 606585 # Total snoops (count)
system.membus.snoop_fanout::samples 2519367 # Request fanout histogram
system.membus.snoop_fanout::mean 0.015113 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.122002 # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-05-31 12:07:18 +02:00
system.membus.snoop_fanout::0 2481292 98.49% 98.49% # Request fanout histogram
system.membus.snoop_fanout::1 38075 1.51% 100.00% # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2016-05-31 12:07:18 +02:00
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2016-05-31 12:07:18 +02:00
system.membus.snoop_fanout::total 2519367 # Request fanout histogram
system.membus.reqLayer0.occupancy 98170994 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.membus.reqLayer2.occupancy 22248500 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.membus.reqLayer5.occupancy 8723892621 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.membus.respLayer2.occupancy 5223815230 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.membus.respLayer3.occupancy 45514707 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2014-12-02 12:08:05 +01:00
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2016-05-31 12:07:18 +02:00
system.toL2Bus.snoop_filter.tot_requests 11842018 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 6441759 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 1913591 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 133722 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 121814 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 11908 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq 60005 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 4492996 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 38534 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 38534 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 3934886 # Transaction distribution
2016-04-21 10:48:24 +02:00
system.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution
2016-05-31 12:07:18 +02:00
system.toL2Bus.trans_dist::CleanEvict 2625367 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 741215 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 380628 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 1121842 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 140 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 140 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 295903 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 295903 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 4433512 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 874748 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 839647 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9358904 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7932274 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 17291178 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 230390413 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 198586357 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 428976770 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 2884507 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 8248846 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.358423 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.482538 # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-05-31 12:07:18 +02:00
system.toL2Bus.snoop_fanout::0 5304178 64.30% 64.30% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 2932760 35.55% 99.86% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 11908 0.14% 100.00% # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-05-31 12:07:18 +02:00
system.toL2Bus.snoop_fanout::total 8248846 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 9216694138 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.toL2Bus.snoopLayer0.occupancy 2593163 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.toL2Bus.respLayer0.occupancy 4234968582 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.toL2Bus.respLayer1.occupancy 3934186551 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2014-10-30 05:50:15 +01:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
2016-05-31 12:07:18 +02:00
system.cpu0.kern.inst.quiesce 13240 # number of quiesce instructions executed
2014-10-30 05:50:15 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
2016-05-31 12:07:18 +02:00
system.cpu1.kern.inst.quiesce 5626 # number of quiesce instructions executed
2014-10-30 05:50:15 +01:00
---------- End Simulation Statistics ----------
