2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
2016-02-10 10:08:27 +01:00
sim_seconds 47.354243 # Number of seconds simulated
sim_ticks 47354242877000 # Number of ticks simulated
final_tick 47354242877000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-02-10 10:08:27 +01:00
host_inst_rate 195342 # Simulator instruction rate (inst/s)
host_op_rate 229691 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 10034841905 # Simulator tick rate (ticks/s)
host_mem_usage 778832 # Number of bytes of host memory used
host_seconds 4718.98 # Real time elapsed on the host
sim_insts 921815819 # Number of instructions simulated
sim_ops 1083910027 # Number of ops (including micro ops) simulated
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-02-10 10:08:27 +01:00
system.physmem.bytes_read::cpu0.dtb.walker 202368 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 196224 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 4450144 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 45350984 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 22283904 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 113792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 85504 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 2862048 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 13865872 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 12452160 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 439808 # Number of bytes read from this memory
system.physmem.bytes_read::total 102302808 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 4450144 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 2862048 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 7312192 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 85371072 # Number of bytes written to this memory
2015-05-05 09:22:39 +02:00
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
2014-12-02 12:08:25 +01:00
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
2016-02-10 10:08:27 +01:00
system.physmem.bytes_written::total 85391656 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 3162 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 3066 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 85486 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 708622 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 348186 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1778 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1336 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 44763 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 216667 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 194565 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6872 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1614503 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1333923 # Number of write requests responded to by this memory
2015-05-05 09:22:39 +02:00
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
2014-12-02 12:08:25 +01:00
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
2016-02-10 10:08:27 +01:00
system.physmem.num_writes::total 1336497 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 4273 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 4144 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 93976 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 957696 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 470579 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 2403 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 1806 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 60439 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 292812 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 262958 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 9288 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2160373 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 93976 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 60439 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 154415 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1802818 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s)
2014-12-02 12:08:25 +01:00
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
2016-02-10 10:08:27 +01:00
system.physmem.bw_write::total 1803252 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1802818 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 4273 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 4144 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 93976 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 958131 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 470579 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 2403 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 1806 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 60439 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 292812 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 262958 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 9288 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3963625 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1614503 # Number of read requests accepted
system.physmem.writeReqs 1336497 # Number of write requests accepted
system.physmem.readBursts 1614503 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1336497 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 103293760 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 34432 # Total number of bytes read from write queue
system.physmem.bytesWritten 85390720 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 102302808 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 85391656 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 538 # Number of DRAM read bursts serviced by the write queue
2015-07-03 16:15:03 +02:00
system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 97103 # Per bank write bursts
system.physmem.perBankRdBursts::1 99552 # Per bank write bursts
system.physmem.perBankRdBursts::2 98906 # Per bank write bursts
system.physmem.perBankRdBursts::3 103577 # Per bank write bursts
system.physmem.perBankRdBursts::4 99773 # Per bank write bursts
system.physmem.perBankRdBursts::5 105983 # Per bank write bursts
system.physmem.perBankRdBursts::6 104785 # Per bank write bursts
system.physmem.perBankRdBursts::7 101396 # Per bank write bursts
system.physmem.perBankRdBursts::8 95400 # Per bank write bursts
system.physmem.perBankRdBursts::9 122614 # Per bank write bursts
system.physmem.perBankRdBursts::10 95999 # Per bank write bursts
system.physmem.perBankRdBursts::11 101585 # Per bank write bursts
system.physmem.perBankRdBursts::12 99838 # Per bank write bursts
system.physmem.perBankRdBursts::13 98462 # Per bank write bursts
system.physmem.perBankRdBursts::14 93633 # Per bank write bursts
system.physmem.perBankRdBursts::15 95359 # Per bank write bursts
system.physmem.perBankWrBursts::0 80772 # Per bank write bursts
system.physmem.perBankWrBursts::1 85062 # Per bank write bursts
system.physmem.perBankWrBursts::2 82679 # Per bank write bursts
system.physmem.perBankWrBursts::3 85393 # Per bank write bursts
system.physmem.perBankWrBursts::4 84018 # Per bank write bursts
system.physmem.perBankWrBursts::5 87943 # Per bank write bursts
system.physmem.perBankWrBursts::6 87092 # Per bank write bursts
system.physmem.perBankWrBursts::7 86427 # Per bank write bursts
system.physmem.perBankWrBursts::8 80096 # Per bank write bursts
system.physmem.perBankWrBursts::9 84617 # Per bank write bursts
system.physmem.perBankWrBursts::10 79653 # Per bank write bursts
system.physmem.perBankWrBursts::11 85236 # Per bank write bursts
system.physmem.perBankWrBursts::12 82895 # Per bank write bursts
system.physmem.perBankWrBursts::13 82853 # Per bank write bursts
system.physmem.perBankWrBursts::14 78695 # Per bank write bursts
system.physmem.perBankWrBursts::15 80799 # Per bank write bursts
2014-10-30 05:50:15 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2016-02-10 10:08:27 +01:00
system.physmem.numWrRetry 46 # Number of times write queue was full causing retry
system.physmem.totGap 47354241269500 # Total gap between requests
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
2015-05-05 09:22:39 +02:00
system.physmem.readPktSize::3 25 # Read request sizes (log2)
2015-03-02 11:04:20 +01:00
system.physmem.readPktSize::4 21333 # Read request sizes (log2)
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-02-10 10:08:27 +01:00
system.physmem.readPktSize::6 1593145 # Read request sizes (log2)
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
2015-05-05 09:22:39 +02:00
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2016-02-10 10:08:27 +01:00
system.physmem.writePktSize::6 1333923 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 609512 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 408742 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 165543 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 158385 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 99064 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 61330 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 32974 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 30716 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 27120 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 7850 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 4295 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 2710 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1710 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1391 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 869 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 607 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 497 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 363 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 155 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 94 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 4 # What read queue length does an incoming req see
2015-12-05 01:11:25 +01:00
system.physmem.rdQLenPdf::24 2 # What read queue length does an incoming req see
2016-02-10 10:08:27 +01:00
system.physmem.rdQLenPdf::25 1 # What read queue length does an incoming req see
2014-12-23 15:31:20 +01:00
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2014-10-30 05:50:15 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2016-02-10 10:08:27 +01:00
system.physmem.wrQLenPdf::15 21385 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 25204 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 37704 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 44061 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 53566 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 60840 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 68935 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 76299 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 82207 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 85573 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 89148 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 94653 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 94373 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 98828 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 112387 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 98640 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 87955 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 82141 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 5308 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 2603 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 1767 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 1210 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 756 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 659 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 496 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 462 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 446 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 410 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 443 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 472 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 377 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 359 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 312 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 324 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 337 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 280 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 310 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 218 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 246 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 222 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 217 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 151 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 167 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 184 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 234 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 86 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 109 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1039142 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 181.576816 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 111.689088 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 241.244363 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 644376 62.01% 62.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 193180 18.59% 80.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 61698 5.94% 86.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 33929 3.27% 89.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 24382 2.35% 92.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 13748 1.32% 93.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 13846 1.33% 94.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 7628 0.73% 95.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 46355 4.46% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1039142 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 75311 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 21.430349 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 250.668355 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095 75308 100.00% 100.00% # Reads before turning the bus around for writes
2015-09-25 13:27:03 +02:00
system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
2015-07-03 16:15:03 +02:00
system.physmem.rdPerTurnAround::8192-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
2015-09-25 13:27:03 +02:00
system.physmem.rdPerTurnAround::65536-69631 1 0.00% 100.00% # Reads before turning the bus around for writes
2016-02-10 10:08:27 +01:00
system.physmem.rdPerTurnAround::total 75311 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 75311 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.716270 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.189166 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 7.091364 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 70052 93.02% 93.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 3029 4.02% 97.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 423 0.56% 97.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 178 0.24% 97.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 138 0.18% 98.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 118 0.16% 98.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 205 0.27% 98.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 81 0.11% 98.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 292 0.39% 98.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 59 0.08% 99.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 23 0.03% 99.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 57 0.08% 99.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 240 0.32% 99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 44 0.06% 99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 27 0.04% 99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 108 0.14% 99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 169 0.22% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 3 0.00% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 2 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 3 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 3 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 1 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 2 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 14 0.02% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 2 0.00% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 4 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 13 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 5 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175 3 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 3 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195 3 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 75311 # Writes before turning the bus around for reads
system.physmem.totQLat 70116127057 # Total ticks spent queuing
system.physmem.totMemAccLat 100377970807 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 8069825000 # Total ticks spent in databus transfers
system.physmem.avgQLat 43443.40 # Average queueing delay per DRAM burst
2014-10-30 05:50:15 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-02-10 10:08:27 +01:00
system.physmem.avgMemAccLat 62193.40 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.18 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.80 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.80 # Average system write bandwidth in MiByte/s
2014-10-30 05:50:15 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2014-12-23 15:31:20 +01:00
system.physmem.busUtil 0.03 # Data bus utilization in percentage
2015-07-03 16:15:03 +02:00
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
2015-09-15 15:14:09 +02:00
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
2016-02-10 10:08:27 +01:00
system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing
system.physmem.avgWrQLen 25.55 # Average write queue length when enqueuing
system.physmem.readRowHits 1298803 # Number of row buffer hits during reads
system.physmem.writeRowHits 610248 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.47 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 45.74 # Row buffer hit rate for writes
system.physmem.avgGap 16046845.57 # Average gap between requests
system.physmem.pageHitRate 64.75 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 4027930200 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 2197779375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 6326346000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 4402421280 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3092948511120 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1180978829595 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 27376595514000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 31667477331570 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.735888 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 45543196260914 # Time in different power states
system.physmem_0.memoryStateTime::REF 1581262020000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-02-10 10:08:27 +01:00
system.physmem_0.memoryStateTime::ACT 229783905086 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-02-10 10:08:27 +01:00
system.physmem_1.actEnergy 3827983320 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2088681375 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 6262534200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 4243389120 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3092948511120 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1177720349355 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 27379453830000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 31666545278490 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.716205 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 45547950580913 # Time in different power states
system.physmem_1.memoryStateTime::REF 1581262020000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-02-10 10:08:27 +01:00
system.physmem_1.memoryStateTime::ACT 225030017087 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory
2014-12-02 12:08:05 +01:00
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
2015-11-06 09:26:50 +01:00
system.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory
2014-12-02 12:08:05 +01:00
system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory
2015-11-06 09:26:50 +01:00
system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 23 # Number of read requests responded to by this memory
2014-12-02 12:08:05 +01:00
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
2015-11-06 09:26:50 +01:00
system.realview.nvmem.num_reads::total 38 # Number of read requests responded to by this memory
2014-12-02 12:08:05 +01:00
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
2016-02-10 10:08:27 +01:00
system.cpu0.branchPred.lookups 149665852 # Number of BP lookups
system.cpu0.branchPred.condPredicted 99294558 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 7394871 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 104737280 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 69525721 # Number of BTB hits
2014-12-02 12:08:05 +01:00
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-02-10 10:08:27 +01:00
system.cpu0.branchPred.BTBHitPct 66.381064 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 20507496 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 218312 # Number of incorrect RAS predictions.
2014-10-30 05:50:15 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-12-23 15:31:20 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-02-10 10:08:27 +01:00
system.cpu0.dtb.walker.walks 634428 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 634428 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 14162 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 100318 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 297022 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 337406 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean 2383.727616 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 14932.270093 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-65535 334700 99.20% 99.20% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-131071 1380 0.41% 99.61% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-196607 1061 0.31% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-262143 114 0.03% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-327679 46 0.01% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-393215 68 0.02% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-458751 21 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::458752-524287 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::524288-589823 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 337406 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 331422 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 21257.229454 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 17843.462773 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 23121.353715 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535 326855 98.62% 98.62% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1016 0.31% 98.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607 2453 0.74% 99.67% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143 165 0.05% 99.72% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679 627 0.19% 99.91% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215 136 0.04% 99.95% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751 104 0.03% 99.98% # Table walker service (enqueue to completion) latency
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.walker.walkCompletionTime::458752-524287 36 0.01% 99.99% # Table walker service (enqueue to completion) latency
2016-02-10 10:08:27 +01:00
system.cpu0.dtb.walker.walkCompletionTime::524288-589823 24 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 331422 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 582048251060 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.606269 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.543146 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1 580572178560 99.75% 99.75% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3 833055500 0.14% 99.89% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5 305294500 0.05% 99.94% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7 135391000 0.02% 99.97% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9 101845000 0.02% 99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11 57765000 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13 18306500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15 23753000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17 653000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::18-19 9000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 582048251060 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 100318 87.63% 87.63% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 14162 12.37% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 114480 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 634428 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-02-10 10:08:27 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 634428 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 114480 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-02-10 10:08:27 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 114480 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 748908 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
2016-02-10 10:08:27 +01:00
system.cpu0.dtb.read_hits 109416332 # DTB read hits
system.cpu0.dtb.read_misses 460008 # DTB read misses
system.cpu0.dtb.write_hits 89314742 # DTB write hits
system.cpu0.dtb.write_misses 174420 # DTB write misses
2015-09-15 15:14:09 +02:00
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-02-10 10:08:27 +01:00
system.cpu0.dtb.flush_tlb_mva_asid 44586 # Number of times TLB was flushed by MVA & ASID
2015-11-06 09:26:50 +01:00
system.cpu0.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
2016-02-10 10:08:27 +01:00
system.cpu0.dtb.flush_entries 43796 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 708 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 7923 # Number of TLB faults due to prefetch
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-02-10 10:08:27 +01:00
system.cpu0.dtb.perms_faults 42753 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 109876340 # DTB read accesses
system.cpu0.dtb.write_accesses 89489162 # DTB write accesses
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
2016-02-10 10:08:27 +01:00
system.cpu0.dtb.hits 198731074 # DTB hits
system.cpu0.dtb.misses 634428 # DTB misses
system.cpu0.dtb.accesses 199365502 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-02-10 10:08:27 +01:00
system.cpu0.itb.walker.walks 91298 # Table walker walks requested
system.cpu0.itb.walker.walksLong 91298 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1125 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3 66671 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore 10542 # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples 80756 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean 1599.144336 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 12482.430449 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-65535 80336 99.48% 99.48% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-131071 92 0.11% 99.59% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-196607 294 0.36% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-262143 14 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::262144-327679 11 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::327680-393215 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency
2015-12-05 01:11:25 +01:00
system.cpu0.itb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
2016-02-10 10:08:27 +01:00
system.cpu0.itb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 80756 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 78338 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 27568.581021 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 23319.178868 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 29698.501423 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535 76052 97.08% 97.08% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071 130 0.17% 97.25% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607 1833 2.34% 99.59% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143 110 0.14% 99.73% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679 108 0.14% 99.87% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215 41 0.05% 99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751 39 0.05% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287 15 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823 3 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::589824-655359 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
2015-11-06 09:26:50 +01:00
system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
2016-02-10 10:08:27 +01:00
system.cpu0.itb.walker.walkCompletionTime::917504-983039 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 78338 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 423131286608 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 0.845297 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev 0.361834 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 65489609660 15.48% 15.48% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 357613926448 84.52% 99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2 25558000 0.01% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3 2033000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4 159500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 423131286608 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 66671 98.34% 98.34% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 1125 1.66% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 67796 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-02-10 10:08:27 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 91298 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 91298 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-02-10 10:08:27 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 67796 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 67796 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 159094 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 236080263 # ITB inst hits
system.cpu0.itb.inst_misses 91298 # ITB inst misses
2014-10-30 05:50:15 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
2015-09-15 15:14:09 +02:00
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
2014-10-30 05:50:15 +01:00
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-02-10 10:08:27 +01:00
system.cpu0.itb.flush_tlb_mva_asid 44586 # Number of times TLB was flushed by MVA & ASID
2015-11-06 09:26:50 +01:00
system.cpu0.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
2016-02-10 10:08:27 +01:00
system.cpu0.itb.flush_entries 31862 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-02-10 10:08:27 +01:00
system.cpu0.itb.perms_faults 229508 # Number of TLB faults due to permissions restrictions
2014-10-30 05:50:15 +01:00
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
2016-02-10 10:08:27 +01:00
system.cpu0.itb.inst_accesses 236171561 # ITB inst accesses
system.cpu0.itb.hits 236080263 # DTB hits
system.cpu0.itb.misses 91298 # DTB misses
system.cpu0.itb.accesses 236171561 # DTB accesses
system.cpu0.numCycles 875332831 # number of cpu cycles simulated
2014-10-30 05:50:15 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-02-10 10:08:27 +01:00
system.cpu0.fetch.icacheStallCycles 98502478 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 662547160 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 149665852 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 90033217 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 725278481 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 15926346 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 2210942 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 343253 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 6644206 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 843353 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 921483 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 235849038 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 1874950 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 30072 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 842707369 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.920891 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 1.205357 # Number of instructions fetched each cycle (Total)
2014-10-30 05:50:15 +01:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-02-10 10:08:27 +01:00
system.cpu0.fetch.rateDist::0 471086256 55.90% 55.90% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 144263495 17.12% 73.02% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 50294842 5.97% 78.99% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 177062776 21.01% 100.00% # Number of instructions fetched each cycle (Total)
2014-10-30 05:50:15 +01:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2016-02-10 10:08:27 +01:00
system.cpu0.fetch.rateDist::total 842707369 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.170982 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.756909 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 117017992 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 431286061 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 248304840 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 40439583 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 5658893 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 21552813 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 2348874 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 685973615 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 25548756 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 5658893 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 155339909 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 68898576 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 270709645 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 249775497 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 92324849 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 667175567 # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts 6553348 # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents 11928405 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 414386 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 932685 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 54388046 # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents 11955 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 637281036 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 1029527825 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 787757309 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 900744 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 574091859 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 63189171 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 16646916 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 14438257 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 81666616 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 109512073 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 93001551 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 9792967 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 8489048 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 643441375 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 16650008 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 647817648 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 2959555 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 59258512 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 38730764 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 299230 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 842707369 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.768734 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.052616 # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-02-10 10:08:27 +01:00
system.cpu0.iq.issued_per_cycle::0 489695832 58.11% 58.11% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 146908165 17.43% 75.54% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 125837037 14.93% 90.48% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 71836004 8.52% 99.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 8424258 1.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 6073 0.00% 100.00% # Number of insts issued each cycle
2015-03-02 11:04:20 +01:00
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2015-03-02 11:04:20 +01:00
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2016-02-10 10:08:27 +01:00
system.cpu0.iq.issued_per_cycle::total 842707369 # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-02-10 10:08:27 +01:00
system.cpu0.iq.fu_full::IntAlu 67261039 45.56% 45.56% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 66196 0.04% 45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 15732 0.01% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 29 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 38768633 26.26% 71.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 41521295 28.12% 100.00% # attempts to use FU when none available
2014-10-30 05:50:15 +01:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2016-02-10 10:08:27 +01:00
system.cpu0.iq.FU_type_0::No_OpClass 14 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 442579425 68.32% 68.32% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 1577066 0.24% 68.56% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 84316 0.01% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 83107 0.01% 68.59% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.59% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.59% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.59% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 112773884 17.41% 86.00% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 90719836 14.00% 100.00% # Type of FU issued
2014-10-30 05:50:15 +01:00
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-02-10 10:08:27 +01:00
system.cpu0.iq.FU_type_0::total 647817648 # Type of FU issued
system.cpu0.iq.rate 0.740082 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 147632924 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.227893 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 2287461115 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 718905040 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 629078745 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 1474027 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 598009 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 548346 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 794539840 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 910718 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 2963176 # Number of loads that had data forwarded from stores
2014-10-30 05:50:15 +01:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-02-10 10:08:27 +01:00
system.cpu0.iew.lsq.thread0.squashedLoads 13511879 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 17808 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 154801 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 6318307 # Number of stores squashed
2014-10-30 05:50:15 +01:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-02-10 10:08:27 +01:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 2892844 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 5122180 # Number of times an access to memory failed due to the cache being blocked
2014-10-30 05:50:15 +01:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-02-10 10:08:27 +01:00
system.cpu0.iew.iewSquashCycles 5658893 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 8725604 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 7188731 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 660220960 # Number of instructions dispatched to IQ
2014-10-30 05:50:15 +01:00
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2016-02-10 10:08:27 +01:00
system.cpu0.iew.iewDispLoadInsts 109512073 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 93001551 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 14147683 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 61387 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 7052032 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 154801 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 2237378 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 3184169 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 5421547 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 639276531 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 109409199 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 7914356 # Number of squashed instructions skipped in execute
2014-10-30 05:50:15 +01:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
2016-02-10 10:08:27 +01:00
system.cpu0.iew.exec_nop 129577 # number of nop insts executed
system.cpu0.iew.exec_refs 198721456 # number of memory reference insts executed
system.cpu0.iew.exec_branches 120519027 # Number of branches executed
system.cpu0.iew.exec_stores 89312257 # Number of stores executed
system.cpu0.iew.exec_rate 0.730324 # Inst execution rate
system.cpu0.iew.wb_sent 630467148 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 629627091 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 306648182 # num instructions producing a value
system.cpu0.iew.wb_consumers 503078288 # num instructions consuming a value
system.cpu0.iew.wb_rate 0.719300 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.609544 # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts 51710398 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 16350778 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 5090591 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 832883786 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.721389 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.530255 # Number of insts commited each cycle
2014-10-30 05:50:15 +01:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-02-10 10:08:27 +01:00
system.cpu0.commit.committed_per_cycle::0 570514920 68.50% 68.50% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 134700149 16.17% 84.67% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 59058098 7.09% 91.76% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 19776256 2.37% 94.14% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 14036208 1.69% 95.82% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 9662272 1.16% 96.98% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 6431324 0.77% 97.75% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 3992857 0.48% 98.23% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 14711702 1.77% 100.00% # Number of insts commited each cycle
2014-10-30 05:50:15 +01:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-02-10 10:08:27 +01:00
system.cpu0.commit.committed_per_cycle::total 832883786 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 511876907 # Number of instructions committed
system.cpu0.commit.committedOps 600832864 # Number of ops (including micro ops) committed
2014-10-30 05:50:15 +01:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
2016-02-10 10:08:27 +01:00
system.cpu0.commit.refs 182683437 # Number of memory references committed
system.cpu0.commit.loads 96000193 # Number of loads committed
system.cpu0.commit.membars 3986424 # Number of memory barriers committed
system.cpu0.commit.branches 114418082 # Number of branches committed
system.cpu0.commit.fp_insts 535391 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 551244640 # Number of committed integer instructions.
system.cpu0.commit.function_calls 15252520 # Number of function calls committed.
2014-10-30 05:50:15 +01:00
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2016-02-10 10:08:27 +01:00
system.cpu0.commit.op_class_0::IntAlu 416691372 69.35% 69.35% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 1318004 0.22% 69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 66523 0.01% 69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 73528 0.01% 69.59% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.59% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.59% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.59% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 96000193 15.98% 85.57% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 86683244 14.43% 100.00% # Class of committed instruction
2014-10-30 05:50:15 +01:00
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-02-10 10:08:27 +01:00
system.cpu0.commit.op_class_0::total 600832864 # Class of committed instruction
system.cpu0.commit.bw_lim_events 14711702 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 1466105636 # The number of ROB reads
system.cpu0.rob.rob_writes 1314872451 # The number of ROB writes
system.cpu0.timesIdled 1097159 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 32625462 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 93833152963 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 511876907 # Number of Instructions Simulated
system.cpu0.committedOps 600832864 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.710046 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.710046 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.584780 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.584780 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 754446272 # number of integer regfile reads
system.cpu0.int_regfile_writes 448604038 # number of integer regfile writes
system.cpu0.fp_regfile_reads 881646 # number of floating regfile reads
system.cpu0.fp_regfile_writes 476304 # number of floating regfile writes
system.cpu0.cc_regfile_reads 139793568 # number of cc regfile reads
system.cpu0.cc_regfile_writes 140496633 # number of cc regfile writes
system.cpu0.misc_regfile_reads 1470350924 # number of misc regfile reads
system.cpu0.misc_regfile_writes 16456285 # number of misc regfile writes
system.cpu0.dcache.tags.replacements 6559473 # number of replacements
system.cpu0.dcache.tags.tagsinuse 490.326221 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 169584910 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 6559985 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 25.851417 # Average number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.tags.warmup_cycle 2962390000 # Cycle when the warmup percentage was hit.
2016-02-10 10:08:27 +01:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 490.326221 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.957668 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.957668 # Average percentage of cache occupancy
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-02-10 10:08:27 +01:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 382 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 36 # Occupied blocks per task id
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-02-10 10:08:27 +01:00
system.cpu0.dcache.tags.tag_accesses 379087602 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 379087602 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 89088742 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 89088742 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 75269986 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 75269986 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 228422 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 228422 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 263534 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 263534 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1920078 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 1920078 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1972778 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 1972778 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 164358728 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 164358728 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 164587150 # number of overall hits
system.cpu0.dcache.overall_hits::total 164587150 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 7258058 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 7258058 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 8107301 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 8107301 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 768102 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 768102 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 855425 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 855425 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 287297 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 287297 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 193519 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 193519 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 15365359 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 15365359 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 16133461 # number of overall misses
system.cpu0.dcache.overall_misses::total 16133461 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 123043131500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 123043131500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 187154125822 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 187154125822 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 92776135134 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 92776135134 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4545100500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 4545100500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5540857500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 5540857500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 7820000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 7820000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 310197257322 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 310197257322 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 310197257322 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 310197257322 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 96346800 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 96346800 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 83377287 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 83377287 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 996524 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 996524 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1118959 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 1118959 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2207375 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 2207375 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2166297 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 2166297 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 179724087 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 179724087 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 180720611 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 180720611 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.075333 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.075333 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.097236 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.097236 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.770781 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.770781 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.764483 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.764483 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.130153 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.130153 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.089332 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.089332 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.085494 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.085494 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.089273 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.089273 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16952.624449 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 16952.624449 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23084.640107 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 23084.640107 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 108456.188601 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 108456.188601 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15820.215665 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15820.215665 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28632.111059 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28632.111059 # average StoreCondReq miss latency
2014-12-02 12:08:05 +01:00
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2016-02-10 10:08:27 +01:00
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20188.090452 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 20188.090452 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19226.950579 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 19226.950579 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 29213495 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 28830141 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 790800 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 799061 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 36.941698 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 36.080025 # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
2014-12-02 12:08:05 +01:00
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
2016-02-10 10:08:27 +01:00
system.cpu0.dcache.writebacks::writebacks 6559531 # number of writebacks
system.cpu0.dcache.writebacks::total 6559531 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3685333 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 3685333 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6510101 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 6510101 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4620 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total 4620 # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 146516 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 146516 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 10195434 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 10195434 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 10195434 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 10195434 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3572725 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 3572725 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1597200 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 1597200 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 761247 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 761247 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 850805 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 850805 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 140781 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 140781 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 193511 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 193511 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 5169925 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 5169925 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 5931172 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 5931172 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32878 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32878 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32941 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32941 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65819 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 65819 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 56556979500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 56556979500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 42701336905 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 42701336905 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18998780500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18998780500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 91672230134 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 91672230134 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 2014552000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2014552000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5347454500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5347454500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 7712000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 7712000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99258316405 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 99258316405 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 118257096905 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 118257096905 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6293183000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6293183000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 6230446500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6230446500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12523629500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12523629500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037082 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037082 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019156 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019156 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.763902 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.763902 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.760354 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.760354 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063778 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063778 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.089328 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.089328 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028766 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.028766 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032820 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.032820 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15830.207895 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15830.207895 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26735.122029 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26735.122029 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24957.445481 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24957.445481 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 107747.639158 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 107747.639158 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14309.828741 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14309.828741 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27633.852856 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27633.852856 # average StoreCondReq mshr miss latency
2014-12-02 12:08:05 +01:00
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2016-02-10 10:08:27 +01:00
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19199.179177 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19199.179177 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19938.234282 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19938.234282 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191410.152686 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191410.152686 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189139.567712 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189139.567712 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190273.773530 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190273.773530 # average overall mshr uncacheable latency
2014-12-02 12:08:05 +01:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-02-10 10:08:27 +01:00
system.cpu0.icache.tags.replacements 6707377 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.936942 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 228724396 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 6707889 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 34.097821 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 21622819000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.936942 # Average occupied blocks per requestor
2015-11-06 09:26:50 +01:00
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999877 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999877 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-02-10 10:08:27 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id
2014-10-30 05:50:15 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-02-10 10:08:27 +01:00
system.cpu0.icache.tags.tag_accesses 478348155 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 478348155 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 228724396 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 228724396 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 228724396 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 228724396 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 228724396 # number of overall hits
system.cpu0.icache.overall_hits::total 228724396 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 7095721 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 7095721 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 7095721 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 7095721 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 7095721 # number of overall misses
system.cpu0.icache.overall_misses::total 7095721 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 79714633751 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 79714633751 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 79714633751 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 79714633751 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 79714633751 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 79714633751 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 235820117 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 235820117 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 235820117 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 235820117 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 235820117 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 235820117 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.030090 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.030090 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.030090 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.030090 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.030090 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.030090 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11234.183778 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 11234.183778 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11234.183778 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 11234.183778 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11234.183778 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 11234.183778 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 12261513 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 1787 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 839174 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 14 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.611407 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 127.642857 # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
2016-02-10 10:08:27 +01:00
system.cpu0.icache.writebacks::writebacks 6707377 # number of writebacks
system.cpu0.icache.writebacks::total 6707377 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 387800 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 387800 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 387800 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 387800 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 387800 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 387800 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6707921 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 6707921 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 6707921 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 6707921 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 6707921 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 6707921 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses
2016-02-10 10:08:27 +01:00
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 71756007072 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 71756007072 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 71756007072 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 71756007072 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 71756007072 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 71756007072 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2939780998 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2939780998 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2939780998 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 2939780998 # number of overall MSHR uncacheable cycles
2016-02-10 10:08:27 +01:00
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028445 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028445 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028445 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.028445 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028445 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.028445 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10697.205151 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10697.205151 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10697.205151 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10697.205151 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10697.205151 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10697.205151 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138063.260132 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138063.260132 # average overall mshr uncacheable latency
2014-10-30 05:50:15 +01:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.prefetcher.num_hwpf_issued 8921966 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 8932201 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 9178 # number of redundant prefetches already in prefetch queue
2014-12-23 15:31:20 +01:00
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.prefetcher.pfSpanPage 1125087 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements 2909208 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16158.656650 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 19404404 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 2925253 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 6.633411 # Average number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.tags.warmup_cycle 3536776000 # Cycle when the warmup percentage was hit.
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.tags.occ_blocks::writebacks 15221.688116 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.041534 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 63.344722 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000040 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 812.582238 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.929058 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003726 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003866 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.049596 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.986246 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1170 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 75 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14800 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 10 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 38 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 178 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 606 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 338 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id
2015-12-05 01:11:25 +01:00
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1308 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5860 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4512 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3004 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.071411 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004578 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.903320 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 454144773 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 454144773 # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 651189 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 209837 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 861026 # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks 4295929 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total 4295929 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks 8968573 # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total 8968573 # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 805 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 805 # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1 # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 980855 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 980855 # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 6087853 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total 6087853 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3397389 # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total 3397389 # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 211269 # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total 211269 # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 651189 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 209837 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 6087853 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 4378244 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 11327123 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 651189 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 209837 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 6087853 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 4378244 # number of overall hits
system.cpu0.l2cache.overall_hits::total 11327123 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13609 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10441 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 24050 # number of ReadReq misses
system.cpu0.l2cache.WritebackDirty_misses::writebacks 4 # number of WritebackDirty misses
system.cpu0.l2cache.WritebackDirty_misses::total 4 # number of WritebackDirty misses
system.cpu0.l2cache.WritebackClean_misses::writebacks 2 # number of WritebackClean misses
system.cpu0.l2cache.WritebackClean_misses::total 2 # number of WritebackClean misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 266523 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 266523 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 193497 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 193497 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 13 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total 13 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 359046 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 359046 # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 620051 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total 620051 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1074980 # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total 1074980 # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 637513 # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total 637513 # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 13609 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10441 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 620051 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 1434026 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 2078127 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 13609 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10441 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 620051 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 1434026 # number of overall misses
system.cpu0.l2cache.overall_misses::total 2078127 # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 731180000 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 642927000 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total 1374107000 # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3539737000 # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total 3539737000 # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2018375000 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2018375000 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 7547996 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 7547996 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 23661492999 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total 23661492999 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 24792926998 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total 24792926998 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 48196505484 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total 48196505484 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 87950874488 # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total 87950874488 # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 731180000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 642927000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 24792926998 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data 71857998483 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total 98025032481 # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 731180000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 642927000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 24792926998 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data 71857998483 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 98025032481 # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 664798 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 220278 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 885076 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4295933 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total 4295933 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks 8968575 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total 8968575 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 267328 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 267328 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 193498 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 193498 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 13 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 13 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1339901 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 1339901 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6707904 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total 6707904 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4472369 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total 4472369 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 848782 # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total 848782 # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 664798 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 220278 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 6707904 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 5812270 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 13405250 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 664798 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 220278 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 6707904 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 5812270 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 13405250 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020471 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.047399 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.027173 # miss rate for ReadReq accesses
system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses
system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses
system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.996989 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.996989 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999995 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999995 # miss rate for SCUpgradeReq accesses
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.267965 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.267965 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.092436 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.092436 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.240360 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.240360 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.751092 # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.751092 # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020471 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.047399 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.092436 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.246724 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.155023 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020471 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.047399 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.092436 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.246724 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.155023 # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 53727.680212 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 61577.147783 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 57135.426195 # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13281.168980 # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13281.168980 # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10431.040275 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10431.040275 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 580615.076923 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 580615.076923 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 65901.007111 # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 65901.007111 # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39985.302819 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39985.302819 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 44834.792725 # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 44834.792725 # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 137959.342771 # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 137959.342771 # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 53727.680212 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 61577.147783 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39985.302819 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 50109.271717 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 47169.895045 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 53727.680212 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 61577.147783 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39985.302819 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 50109.271717 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 47169.895045 # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs 3672 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.blocked::no_mshrs 25 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 146.880000 # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.writebacks::writebacks 1813424 # number of writebacks
system.cpu0.l2cache.writebacks::total 1813424 # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 5 # number of ReadReq MSHR hits
2015-12-05 01:11:25 +01:00
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 178 # number of ReadReq MSHR hits
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.ReadReq_mshr_hits::total 183 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 69322 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total 69322 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 4 # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 7219 # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 7219 # number of ReadSharedReq MSHR hits
2015-12-05 01:11:25 +01:00
system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 5 # number of InvalidateReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::total 5 # number of InvalidateReq MSHR hits
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 5 # number of demand (read+write) MSHR hits
2015-12-05 01:11:25 +01:00
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 178 # number of demand (read+write) MSHR hits
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data 76541 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total 76728 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 5 # number of overall MSHR hits
2015-12-05 01:11:25 +01:00
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 178 # number of overall MSHR hits
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data 76541 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total 76728 # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 13604 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10263 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total 23867 # number of ReadReq MSHR misses
system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 4 # number of WritebackDirty MSHR misses
system.cpu0.l2cache.WritebackDirty_mshr_misses::total 4 # number of WritebackDirty MSHR misses
system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 2 # number of WritebackClean MSHR misses
system.cpu0.l2cache.WritebackClean_mshr_misses::total 2 # number of WritebackClean MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 927565 # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total 927565 # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 266523 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total 266523 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 193497 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 193497 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 13 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 13 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 289724 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total 289724 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 620047 # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 620047 # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1067761 # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1067761 # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 637508 # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total 637508 # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 13604 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10263 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 620047 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1357485 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total 2001399 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 13604 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10263 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 620047 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1357485 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 927565 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total 2928964 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32878 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 54171 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 32941 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 32941 # number of WriteReq MSHR uncacheable
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 65819 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 87112 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 649200000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 572348000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1221548000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 68343452519 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 68343452519 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7943943496 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7943943496 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3893295994 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3893295994 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 6899996 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 6899996 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 17756340999 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 17756340999 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 21072592498 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 21072592498 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 41283242484 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 41283242484 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 84125646988 # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 84125646988 # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 649200000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 572348000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 21072592498 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 59039583483 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 81333723981 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 649200000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 572348000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 21072592498 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 59039583483 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 68343452519 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 149677176500 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2780082500 # number of ReadReq MSHR uncacheable cycles
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6029953000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8810035500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5977560967 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5977560967 # number of WriteReq MSHR uncacheable cycles
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 2780082500 # number of overall MSHR uncacheable cycles
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 12007513967 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 14787596467 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.020463 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.046591 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.026966 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses
system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses
system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.996989 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.996989 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999995 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.216228 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.216228 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092435 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092435 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.238746 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.238746 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.751086 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.751086 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.020463 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.046591 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092435 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.233555 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.149300 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.020463 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.046591 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092435 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.233555 # mshr miss rate for overall accesses
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.218494 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 47721.258453 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 55768.098996 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 51181.463946 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 73680.499500 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 73680.499500 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29805.846010 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29805.846010 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20120.704683 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20120.704683 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 530768.923077 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 530768.923077 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 61287.090469 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 61287.090469 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33985.476098 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33985.476098 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 38663.373624 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 38663.373624 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 131960.143226 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 131960.143226 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 47721.258453 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 55768.098996 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33985.476098 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43491.886454 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40638.435405 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 47721.258453 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 55768.098996 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33985.476098 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43491.886454 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 73680.499500 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 51102.429562 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263 # average ReadReq mshr uncacheable latency
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183403.887098 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162633.798527 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181462.644334 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181462.644334 # average WriteReq mshr uncacheable latency
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263 # average overall mshr uncacheable latency
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 182432.336666 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 169753.839505 # average overall mshr uncacheable latency
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-02-10 10:08:27 +01:00
system.cpu0.toL2Bus.snoop_filter.tot_requests 27467007 # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 14098216 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2397 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops 2174971 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2174417 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 554 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq 1027741 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 12311555 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 32941 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 32941 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty 6114023 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean 8970970 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict 2853143 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 1178619 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.cpu0.toL2Bus.trans_dist::HardPFResp 8 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.cpu0.toL2Bus.trans_dist::UpgradeReq 489036 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 343853 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 531725 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 106 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 201 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 1422561 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 1350501 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6707921 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5424362 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq 856015 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp 848782 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20165788 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21120167 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 459340 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1399304 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 43144599 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 858918672 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 799305801 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1762224 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5318384 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 1665305081 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 7537626 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 22154436 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 0.115021 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.319126 # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-02-10 10:08:27 +01:00
system.cpu0.toL2Bus.snoop_fanout::0 19606761 88.50% 88.50% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 2547121 11.50% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 554 0.00% 100.00% # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-02-10 10:08:27 +01:00
system.cpu0.toL2Bus.snoop_fanout::total 22154436 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 27362140922 # Layer occupancy (ticks)
2015-11-06 09:26:50 +01:00
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.cpu0.toL2Bus.snoopLayer0.occupancy 207113536 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.cpu0.toL2Bus.respLayer0.occupancy 10089828109 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.cpu0.toL2Bus.respLayer1.occupancy 9431575123 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.cpu0.toL2Bus.respLayer2.occupancy 239573965 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.cpu0.toL2Bus.respLayer3.occupancy 735155181 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.cpu1.branchPred.lookups 119891525 # Number of BP lookups
system.cpu1.branchPred.condPredicted 80198528 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 5904198 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 84182887 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 54925615 # Number of BTB hits
2014-10-30 05:50:15 +01:00
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-02-10 10:08:27 +01:00
system.cpu1.branchPred.BTBHitPct 65.245583 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 16054982 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 157154 # Number of incorrect RAS predictions.
2014-12-23 15:31:20 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-02-10 10:08:27 +01:00
system.cpu1.dtb.walker.walks 523591 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 523591 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9887 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 82113 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 242894 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 280697 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 2503.193835 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 14937.525211 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-65535 278494 99.22% 99.22% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-131071 1255 0.45% 99.66% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-196607 659 0.23% 99.90% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::196608-262143 166 0.06% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-327679 38 0.01% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::327680-393215 57 0.02% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::393216-458751 13 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::524288-589823 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::589824-655359 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 280697 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 263545 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 19785.484452 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 17259.480271 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 16001.974136 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535 261738 99.31% 99.31% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071 658 0.25% 99.56% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607 820 0.31% 99.88% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143 79 0.03% 99.91% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679 151 0.06% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215 47 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751 31 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287 11 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
2016-02-10 10:08:27 +01:00
system.cpu1.dtb.walker.walkCompletionTime::total 263545 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 427419381904 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.550644 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.560610 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1 426298998404 99.74% 99.74% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3 579725500 0.14% 99.87% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5 235009500 0.05% 99.93% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7 123480000 0.03% 99.96% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9 88192000 0.02% 99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11 51481500 0.01% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13 16753000 0.00% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15 25205500 0.01% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17 518000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::18-19 18500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 427419381904 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 82114 89.25% 89.25% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 9887 10.75% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 92001 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 523591 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-02-10 10:08:27 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 523591 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 92001 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-02-10 10:08:27 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 92001 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 615592 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
2016-02-10 10:08:27 +01:00
system.cpu1.dtb.read_hits 88459625 # DTB read hits
system.cpu1.dtb.read_misses 355289 # DTB read misses
system.cpu1.dtb.write_hits 73058314 # DTB write hits
system.cpu1.dtb.write_misses 168302 # DTB write misses
2015-09-15 15:14:09 +02:00
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-02-10 10:08:27 +01:00
system.cpu1.dtb.flush_tlb_mva_asid 44586 # Number of times TLB was flushed by MVA & ASID
2015-11-06 09:26:50 +01:00
system.cpu1.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
2016-02-10 10:08:27 +01:00
system.cpu1.dtb.flush_entries 34429 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 243 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 5558 # Number of TLB faults due to prefetch
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-02-10 10:08:27 +01:00
system.cpu1.dtb.perms_faults 38457 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 88814914 # DTB read accesses
system.cpu1.dtb.write_accesses 73226616 # DTB write accesses
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
2016-02-10 10:08:27 +01:00
system.cpu1.dtb.hits 161517939 # DTB hits
system.cpu1.dtb.misses 523591 # DTB misses
system.cpu1.dtb.accesses 162041530 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-02-10 10:08:27 +01:00
system.cpu1.itb.walker.walks 79238 # Table walker walks requested
system.cpu1.itb.walker.walksLong 79238 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 670 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55768 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore 9704 # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples 69534 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean 1362.196911 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 10189.827482 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-32767 68875 99.05% 99.05% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-65535 429 0.62% 99.67% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-98303 22 0.03% 99.70% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::98304-131071 45 0.06% 99.77% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-163839 97 0.14% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::163840-196607 46 0.07% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::196608-229375 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::229376-262143 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-294911 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 69534 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 66142 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 24972.294457 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 22450.763423 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 20128.243900 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535 65282 98.70% 98.70% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071 106 0.16% 98.86% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607 635 0.96% 99.82% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143 41 0.06% 99.88% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679 34 0.05% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215 18 0.03% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751 18 0.03% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 66142 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 405913969924 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean 0.852777 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev 0.354498 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 59781305300 14.73% 14.73% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1 346114009624 85.27% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2 16127000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3 2369500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4 82500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::5 76000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 405913969924 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 55768 98.81% 98.81% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 670 1.19% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 56438 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-02-10 10:08:27 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 79238 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 79238 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-02-10 10:08:27 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56438 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56438 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 135676 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 188743149 # ITB inst hits
system.cpu1.itb.inst_misses 79238 # ITB inst misses
2014-10-30 05:50:15 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
2015-09-15 15:14:09 +02:00
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
2014-10-30 05:50:15 +01:00
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-02-10 10:08:27 +01:00
system.cpu1.itb.flush_tlb_mva_asid 44586 # Number of times TLB was flushed by MVA & ASID
2015-11-06 09:26:50 +01:00
system.cpu1.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
2016-02-10 10:08:27 +01:00
system.cpu1.itb.flush_entries 24595 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-02-10 10:08:27 +01:00
system.cpu1.itb.perms_faults 203696 # Number of TLB faults due to permissions restrictions
2014-10-30 05:50:15 +01:00
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
2016-02-10 10:08:27 +01:00
system.cpu1.itb.inst_accesses 188822387 # ITB inst accesses
system.cpu1.itb.hits 188743149 # DTB hits
system.cpu1.itb.misses 79238 # DTB misses
system.cpu1.itb.accesses 188822387 # DTB accesses
system.cpu1.numCycles 668763369 # number of cpu cycles simulated
2014-10-30 05:50:15 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-02-10 10:08:27 +01:00
system.cpu1.fetch.icacheStallCycles 76762482 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 531105996 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 119891525 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 70980597 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 555217707 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 12731518 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 1797928 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 295013 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 5987179 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 752221 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 763722 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 188519405 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 1489379 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 27517 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 647942011 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.963740 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 1.217002 # Number of instructions fetched each cycle (Total)
2014-10-30 05:50:15 +01:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-02-10 10:08:27 +01:00
system.cpu1.fetch.rateDist::0 349005233 53.86% 53.86% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 116425876 17.97% 71.83% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 39511198 6.10% 77.93% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 142999704 22.07% 100.00% # Number of instructions fetched each cycle (Total)
2014-10-30 05:50:15 +01:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2016-02-10 10:08:27 +01:00
system.cpu1.fetch.rateDist::total 647942011 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.179273 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.794161 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 92682171 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 320350015 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 196661442 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 33741382 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 4507001 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 16971690 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 1895430 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 551371568 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 20348682 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 4507001 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 124070698 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 47114866 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 212074227 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 198637530 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 61537689 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 536563152 # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts 5145214 # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents 9840770 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 223861 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 282097 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 29934469 # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents 10810 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 509803663 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 829081125 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 634679636 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 600803 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 459431302 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 50372361 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 14562905 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 12854163 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 68041373 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 88476596 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 76035338 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 8565835 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 7285035 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 516079501 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 14870100 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 521291240 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 2377203 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 47872437 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 30743352 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 257935 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 647942011 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.804534 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.061029 # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-02-10 10:08:27 +01:00
system.cpu1.iq.issued_per_cycle::0 361872507 55.85% 55.85% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 122353667 18.88% 74.73% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 99252241 15.32% 90.05% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 57424869 8.86% 98.91% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 7035151 1.09% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 3576 0.00% 100.00% # Number of insts issued each cycle
2014-12-23 15:31:20 +01:00
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2014-12-23 15:31:20 +01:00
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2016-02-10 10:08:27 +01:00
system.cpu1.iq.issued_per_cycle::total 647942011 # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-02-10 10:08:27 +01:00
system.cpu1.iq.fu_full::IntAlu 52040674 43.67% 43.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 50092 0.04% 43.71% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 18388 0.02% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 16 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 32200400 27.02% 70.74% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 34865580 29.26% 100.00% # attempts to use FU when none available
2014-10-30 05:50:15 +01:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2016-02-10 10:08:27 +01:00
system.cpu1.iq.FU_type_0::No_OpClass 27 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 354670500 68.04% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 1183955 0.23% 68.26% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 65513 0.01% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 42657 0.01% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 91135432 17.48% 85.77% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 74193108 14.23% 100.00% # Type of FU issued
2014-10-30 05:50:15 +01:00
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-02-10 10:08:27 +01:00
system.cpu1.iq.FU_type_0::total 521291240 # Type of FU issued
system.cpu1.iq.rate 0.779485 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 119175150 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.228615 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 1811086365 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 578565811 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 506287229 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 990479 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 395514 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 364516 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 639849832 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 616531 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 2398408 # Number of loads that had data forwarded from stores
2014-10-30 05:50:15 +01:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-02-10 10:08:27 +01:00
system.cpu1.iew.lsq.thread0.squashedLoads 11063470 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 14436 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 140383 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 5257500 # Number of stores squashed
2014-10-30 05:50:15 +01:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-02-10 10:08:27 +01:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 2402216 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 3864822 # Number of times an access to memory failed due to the cache being blocked
2014-10-30 05:50:15 +01:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-02-10 10:08:27 +01:00
system.cpu1.iew.iewSquashCycles 4507001 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 5849706 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 2188326 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 531063111 # Number of instructions dispatched to IQ
2014-10-30 05:50:15 +01:00
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2016-02-10 10:08:27 +01:00
system.cpu1.iew.iewDispLoadInsts 88476596 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 76035338 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 12650539 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 60907 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 2070757 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 140383 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 1813068 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 2483133 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 4296201 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 514538937 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 88454625 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 6240485 # Number of squashed instructions skipped in execute
2014-10-30 05:50:15 +01:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
2016-02-10 10:08:27 +01:00
system.cpu1.iew.exec_nop 113510 # number of nop insts executed
system.cpu1.iew.exec_refs 161513914 # number of memory reference insts executed
system.cpu1.iew.exec_branches 96416033 # Number of branches executed
system.cpu1.iew.exec_stores 73059289 # Number of stores executed
system.cpu1.iew.exec_rate 0.769389 # Inst execution rate
system.cpu1.iew.wb_sent 507314383 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 506651745 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 244576343 # num instructions producing a value
system.cpu1.iew.wb_consumers 400655745 # num instructions consuming a value
system.cpu1.iew.wb_rate 0.757595 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.610440 # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts 41944033 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 14612165 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 4045440 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 639995571 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.754813 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.555930 # Number of insts commited each cycle
2014-10-30 05:50:15 +01:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-02-10 10:08:27 +01:00
system.cpu1.commit.committed_per_cycle::0 426913272 66.71% 66.71% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 112061055 17.51% 84.22% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 46474767 7.26% 91.48% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 15512784 2.42% 93.90% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 11149430 1.74% 95.64% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 7505688 1.17% 96.82% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 5285555 0.83% 97.64% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 3055428 0.48% 98.12% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 12037592 1.88% 100.00% # Number of insts commited each cycle
2014-10-30 05:50:15 +01:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-02-10 10:08:27 +01:00
system.cpu1.commit.committed_per_cycle::total 639995571 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 409938912 # Number of instructions committed
system.cpu1.commit.committedOps 483077163 # Number of ops (including micro ops) committed
2014-10-30 05:50:15 +01:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
2016-02-10 10:08:27 +01:00
system.cpu1.commit.refs 148190964 # Number of memory references committed
system.cpu1.commit.loads 77413126 # Number of loads committed
system.cpu1.commit.membars 3553266 # Number of memory barriers committed
system.cpu1.commit.branches 91478423 # Number of branches committed
system.cpu1.commit.fp_insts 356192 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 443462583 # Number of committed integer instructions.
system.cpu1.commit.function_calls 11919697 # Number of function calls committed.
2014-10-30 05:50:15 +01:00
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2016-02-10 10:08:27 +01:00
system.cpu1.commit.op_class_0::IntAlu 333838399 69.11% 69.11% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 958189 0.20% 69.30% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 52064 0.01% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 37505 0.01% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.32% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 77413126 16.03% 85.35% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 70777838 14.65% 100.00% # Class of committed instruction
2014-10-30 05:50:15 +01:00
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-02-10 10:08:27 +01:00
system.cpu1.commit.op_class_0::total 483077163 # Class of committed instruction
system.cpu1.commit.bw_lim_events 12037592 # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads 1149378464 # The number of ROB reads
system.cpu1.rob.rob_writes 1057951201 # The number of ROB writes
system.cpu1.timesIdled 862725 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 20821358 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 94039702456 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 409938912 # Number of Instructions Simulated
system.cpu1.committedOps 483077163 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 1.631373 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.631373 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.612981 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.612981 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 608507800 # number of integer regfile reads
system.cpu1.int_regfile_writes 359700181 # number of integer regfile writes
system.cpu1.fp_regfile_reads 588843 # number of floating regfile reads
system.cpu1.fp_regfile_writes 298828 # number of floating regfile writes
system.cpu1.cc_regfile_reads 110183943 # number of cc regfile reads
system.cpu1.cc_regfile_writes 110950246 # number of cc regfile writes
system.cpu1.misc_regfile_reads 1143200959 # number of misc regfile reads
system.cpu1.misc_regfile_writes 14699928 # number of misc regfile writes
system.cpu1.dcache.tags.replacements 4943818 # number of replacements
system.cpu1.dcache.tags.tagsinuse 455.490717 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 138046990 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 4944322 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 27.920307 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 8486298300000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.490717 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.889630 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.889630 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 504 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 434 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.984375 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 307427480 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 307427480 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 71852716 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 71852716 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 61790747 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 61790747 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 162379 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 162379 # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data 50057 # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total 50057 # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1706960 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 1706960 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1722622 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 1722622 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 133643463 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 133643463 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 133805842 # number of overall hits
system.cpu1.dcache.overall_hits::total 133805842 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 5820950 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 5820950 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 6630483 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 6630483 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 628859 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 628859 # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data 401328 # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total 401328 # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 243245 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 243245 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 186259 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 186259 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 12451433 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 12451433 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 13080292 # number of overall misses
system.cpu1.dcache.overall_misses::total 13080292 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 96708932500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 96708932500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 144491403356 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 144491403356 # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 16631824083 # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total 16631824083 # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3760760000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 3760760000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5141971500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 5141971500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 6754500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 6754500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 241200335856 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 241200335856 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 241200335856 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 241200335856 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 77673666 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 77673666 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 68421230 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 68421230 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 791238 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 791238 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 451385 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total 451385 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1950205 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 1950205 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1908881 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 1908881 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 146094896 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 146094896 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 146886134 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 146886134 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074941 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.074941 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.096907 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.096907 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.794779 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.794779 # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.889104 # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total 0.889104 # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124728 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124728 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097575 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097575 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085228 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.085228 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.089051 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.089051 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16613.943171 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 16613.943171 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21791.987606 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 21791.987606 # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 41441.972858 # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 41441.972858 # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15460.790561 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15460.790561 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27606.566663 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27606.566663 # average StoreCondReq miss latency
2014-12-02 12:08:05 +01:00
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2016-02-10 10:08:27 +01:00
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19371.291309 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 19371.291309 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18439.980992 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 18439.980992 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 4381553 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 22968096 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 326353 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 670571 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13.425809 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 34.251550 # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
2014-12-02 12:08:05 +01:00
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
2016-02-10 10:08:27 +01:00
system.cpu1.dcache.writebacks::writebacks 4943833 # number of writebacks
system.cpu1.dcache.writebacks::total 4943833 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 2977175 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 2977175 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5355618 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 5355618 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3078 # number of WriteLineReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::total 3078 # number of WriteLineReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 125917 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 125917 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 8332793 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 8332793 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 8332793 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 8332793 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2843775 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 2843775 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1274865 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 1274865 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 628773 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 628773 # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 398250 # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total 398250 # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 117328 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 117328 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 186249 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 186249 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 4118640 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 4118640 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 4747413 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 4747413 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5429 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5429 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5284 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5284 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10713 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10713 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 43326231000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 43326231000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 30961849442 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 30961849442 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15267610500 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15267610500 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 16078596583 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 16078596583 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1709363500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1709363500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4955815500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4955815500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 6661500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 6661500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 74288080442 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 74288080442 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 89555690942 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 89555690942 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 604887500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 604887500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 670175500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 670175500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1275063000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1275063000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036612 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036612 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018633 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018633 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.794670 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.794670 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.882285 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.882285 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060162 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060162 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097570 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097570 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028192 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.028192 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032320 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.032320 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15235.463776 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15235.463776 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24286.374982 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24286.374982 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24281.593675 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24281.593675 # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 40373.123874 # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 40373.123874 # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14569.101152 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14569.101152 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26608.548234 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26608.548234 # average StoreCondReq mshr miss latency
2014-12-02 12:08:05 +01:00
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2016-02-10 10:08:27 +01:00
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18037.041461 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18037.041461 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18864.103659 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18864.103659 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 111417.848591 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 111417.848591 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 126831.093868 # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 126831.093868 # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 119020.162419 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 119020.162419 # average overall mshr uncacheable latency
2014-12-02 12:08:05 +01:00
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-02-10 10:08:27 +01:00
system.cpu1.icache.tags.replacements 5253385 # number of replacements
system.cpu1.icache.tags.tagsinuse 501.776230 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 182951519 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 5253897 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 34.822060 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 8525973531000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.776230 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980032 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.980032 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-02-10 10:08:27 +01:00
system.cpu1.icache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 104 # Occupied blocks per task id
2014-10-30 05:50:15 +01:00
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-02-10 10:08:27 +01:00
system.cpu1.icache.tags.tag_accesses 382279380 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 382279380 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 182951519 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 182951519 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 182951519 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 182951519 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 182951519 # number of overall hits
system.cpu1.icache.overall_hits::total 182951519 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 5561220 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 5561220 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 5561220 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 5561220 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 5561220 # number of overall misses
system.cpu1.icache.overall_misses::total 5561220 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 62243274721 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 62243274721 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 62243274721 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 62243274721 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 62243274721 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 62243274721 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 188512739 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 188512739 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 188512739 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 188512739 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 188512739 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 188512739 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029500 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.029500 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029500 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.029500 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029500 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.029500 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11192.377701 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 11192.377701 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11192.377701 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 11192.377701 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11192.377701 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 11192.377701 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 9679381 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 762 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 668024 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 6 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.489571 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets 127 # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
2016-02-10 10:08:27 +01:00
system.cpu1.icache.writebacks::writebacks 5253385 # number of writebacks
system.cpu1.icache.writebacks::total 5253385 # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 307318 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 307318 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 307318 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 307318 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 307318 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 307318 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5253902 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 5253902 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 5253902 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 5253902 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 5253902 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 5253902 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses
2016-02-10 10:08:27 +01:00
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 56076616223 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 56076616223 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 56076616223 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 56076616223 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 56076616223 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 56076616223 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9266998 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9266998 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9266998 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 9266998 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027870 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027870 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027870 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.027870 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027870 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.027870 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10673.327409 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10673.327409 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10673.327409 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 10673.327409 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10673.327409 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 10673.327409 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 138313.402985 # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 138313.402985 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 138313.402985 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 138313.402985 # average overall mshr uncacheable latency
2014-10-30 05:50:15 +01:00
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-02-10 10:08:27 +01:00
system.cpu1.l2cache.prefetcher.num_hwpf_issued 6897065 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 6901426 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 4002 # number of redundant prefetches already in prefetch queue
2014-12-23 15:31:20 +01:00
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2016-02-10 10:08:27 +01:00
system.cpu1.l2cache.prefetcher.pfSpanPage 806814 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements 2026565 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 13359.801047 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 15204091 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 2042184 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 7.445015 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 10003867799500 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 12523.198532 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 53.208861 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 55.513996 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 727.879658 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.764355 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003248 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003388 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.044426 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.815418 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1266 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 101 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14252 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 87 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 167 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 620 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 392 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 76 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id
2015-12-05 01:11:25 +01:00
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id
2016-02-10 10:08:27 +01:00
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 933 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4753 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4784 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3782 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.077271 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006165 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.869873 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 351102850 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 351102850 # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 535016 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 179387 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 714403 # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks 3106842 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total 3106842 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks 7089221 # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total 7089221 # number of WritebackClean hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 559 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 559 # number of UpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 768937 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 768937 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4743157 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 4743157 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2644934 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 2644934 # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 173458 # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total 173458 # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 535016 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 179387 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 4743157 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 3413871 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 8871431 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 535016 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 179387 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 4743157 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 3413871 # number of overall hits
system.cpu1.l2cache.overall_hits::total 8871431 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11427 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8460 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 19887 # number of ReadReq misses
system.cpu1.l2cache.WritebackDirty_misses::writebacks 5 # number of WritebackDirty misses
system.cpu1.l2cache.WritebackDirty_misses::total 5 # number of WritebackDirty misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 231672 # number of UpgradeReq misses
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2014-10-30 05:50:15 +01:00
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2016-02-10 10:08:27 +01:00
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2014-10-30 05:50:15 +01:00
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2016-02-10 10:08:27 +01:00
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2014-10-30 05:50:15 +01:00
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2016-02-10 10:08:27 +01:00
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2014-10-30 05:50:15 +01:00
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2016-02-10 10:08:27 +01:00
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2015-05-05 09:22:39 +02:00
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2016-02-10 10:08:27 +01:00
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2016-02-10 10:08:27 +01:00
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system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 31352302486 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 31352302486 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 12578456999 # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 12578456999 # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 436185000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 314747000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 16408482000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 42945541485 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 60104955485 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 436185000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 314747000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 16408482000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 42945541485 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 40592481689 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 100697437174 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8763500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 561342500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 570106000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 630451500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 630451500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8763500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1191794000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1200557500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020902 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.043972 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.026804 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000002 # mshr miss rate for WritebackDirty accesses
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2016-02-10 10:08:27 +01:00
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997593 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997593 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2016-02-10 10:08:27 +01:00
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.235701 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.235701 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.097211 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097211 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.261133 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.261133 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.562593 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.562593 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020902 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.043972 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.097211 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.255366 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.161372 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020902 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.043972 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.097211 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.255366 # mshr miss rate for overall accesses
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2016-02-10 10:08:27 +01:00
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.228955 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 38188.145684 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38104.963680 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 38153.236460 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 56526.199996 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 56526.199996 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 30720.803520 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30720.803520 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19094.913466 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19094.913466 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 541954.363636 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 541954.363636 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46776.544018 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46776.544018 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32126.941549 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32126.941549 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33480.096542 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33480.096542 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 56378.079768 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 56378.079768 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 38188.145684 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38104.963680 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32126.941549 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36262.720911 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35052.548527 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 38188.145684 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38104.963680 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32126.941549 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36262.720911 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 56526.199996 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 41391.104169 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 130798.507463 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 103397.034445 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 103731.077147 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 119313.304315 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 119313.304315 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 130798.507463 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 111247.456361 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 111368.970315 # average overall mshr uncacheable latency
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-02-10 10:08:27 +01:00
system.cpu1.toL2Bus.snoop_filter.tot_requests 21246355 # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10958434 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1131 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops 1866438 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1866138 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 300 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq 825754 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 9752282 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 5284 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 5284 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty 4201386 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean 7090370 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict 2466487 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 905169 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.cpu1.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.cpu1.toL2Bus.trans_dist::UpgradeReq 447608 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 337242 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 479463 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 119 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 201 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 1130462 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 1058321 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5253902 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4579290 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 402900 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp 396573 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15761317 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16025111 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 394044 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1160504 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 33340976 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 672467056 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 619232766 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1502776 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4371544 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 1297574142 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 6151657 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 17448758 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 0.126682 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.332668 # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-02-10 10:08:27 +01:00
system.cpu1.toL2Bus.snoop_fanout::0 15238612 87.33% 87.33% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 2209846 12.66% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 300 0.00% 100.00% # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-02-10 10:08:27 +01:00
system.cpu1.toL2Bus.snoop_fanout::total 17448758 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 21067285470 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.cpu1.toL2Bus.snoopLayer0.occupancy 170823638 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.cpu1.toL2Bus.respLayer0.occupancy 7886135987 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.cpu1.toL2Bus.respLayer1.occupancy 7380840948 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.cpu1.toL2Bus.respLayer2.occupancy 206620146 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.cpu1.toL2Bus.respLayer3.occupancy 614769571 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.iobus.trans_dist::ReadReq 40283 # Transaction distribution
system.iobus.trans_dist::ReadResp 40283 # Transaction distribution
system.iobus.trans_dist::WriteReq 136631 # Transaction distribution
system.iobus.trans_dist::WriteResp 136631 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47650 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2016-02-10 10:08:27 +01:00
system.iobus.pkt_count_system.bridge.master::total 122584 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231164 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2016-02-10 10:08:27 +01:00
system.iobus.pkt_count::total 353828 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47670 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2016-02-10 10:08:27 +01:00
system.iobus.pkt_size_system.bridge.master::total 155691 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338672 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7338672 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2016-02-10 10:08:27 +01:00
system.iobus.pkt_size::total 7496449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 36944000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.iobus.reqLayer2.occupancy 326000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.iobus.reqLayer23.occupancy 24787502 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.iobus.reqLayer24.occupancy 36442000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.iobus.reqLayer25.occupancy 567400129 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.iobus.respLayer0.occupancy 92684000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.iobus.respLayer3.occupancy 147860000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-07-03 16:15:03 +02:00
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.iocache.tags.replacements 115578 # number of replacements
system.iocache.tags.tagsinuse 11.298905 # Cycle average of tags in use
2015-12-05 01:11:25 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2016-02-10 10:08:27 +01:00
system.iocache.tags.sampled_refs 115594 # Sample count of references to valid blocks.
2015-12-05 01:11:25 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2016-02-10 10:08:27 +01:00
system.iocache.tags.warmup_cycle 9125697698000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 7.418105 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 3.880800 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.463632 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.242550 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.706182 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2016-02-10 10:08:27 +01:00
system.iocache.tags.tag_accesses 1040595 # Number of tag accesses
system.iocache.tags.data_accesses 1040595 # Number of data accesses
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2016-02-10 10:08:27 +01:00
system.iocache.ReadReq_misses::realview.ide 8854 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8891 # number of ReadReq misses
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2016-02-10 10:08:27 +01:00
system.iocache.demand_misses::realview.ide 8854 # number of demand (read+write) misses
system.iocache.demand_misses::total 8894 # number of demand (read+write) misses
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2016-02-10 10:08:27 +01:00
system.iocache.overall_misses::realview.ide 8854 # number of overall misses
system.iocache.overall_misses::total 8894 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5230500 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1713293012 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1718523512 # number of ReadReq miss cycles
2015-07-30 09:42:27 +02:00
system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
2016-02-10 10:08:27 +01:00
system.iocache.WriteLineReq_miss_latency::realview.ide 13529785617 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 13529785617 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5599500 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 1713293012 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 1718892512 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5599500 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 1713293012 # number of overall miss cycles
system.iocache.overall_miss_latency::total 1718892512 # number of overall miss cycles
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2016-02-10 10:08:27 +01:00
system.iocache.ReadReq_accesses::realview.ide 8854 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8891 # number of ReadReq accesses(hits+misses)
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2016-02-10 10:08:27 +01:00
system.iocache.demand_accesses::realview.ide 8854 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8894 # number of demand (read+write) accesses
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2016-02-10 10:08:27 +01:00
system.iocache.overall_accesses::realview.ide 8854 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8894 # number of overall (read+write) accesses
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2016-02-10 10:08:27 +01:00
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141364.864865 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 193504.970861 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 193287.989203 # average ReadReq miss latency
2015-07-30 09:42:27 +02:00
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
2016-02-10 10:08:27 +01:00
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126768.848072 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 126768.848072 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 139987.500000 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 193504.970861 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 193264.280639 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 139987.500000 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 193504.970861 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 193264.280639 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 34686 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-02-10 10:08:27 +01:00
system.iocache.blocked::no_mshrs 3488 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2016-02-10 10:08:27 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 9.944381 # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
2014-10-30 05:50:15 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
2015-12-05 01:11:25 +01:00
system.iocache.writebacks::writebacks 106694 # number of writebacks
system.iocache.writebacks::total 106694 # number of writebacks
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2016-02-10 10:08:27 +01:00
system.iocache.ReadReq_mshr_misses::realview.ide 8854 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8891 # number of ReadReq MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2016-02-10 10:08:27 +01:00
system.iocache.demand_mshr_misses::realview.ide 8854 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 8894 # number of demand (read+write) MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2016-02-10 10:08:27 +01:00
system.iocache.overall_mshr_misses::realview.ide 8854 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 8894 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3380500 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1270593012 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1273973512 # number of ReadReq MSHR miss cycles
2015-07-30 09:42:27 +02:00
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
2016-02-10 10:08:27 +01:00
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8187257903 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 8187257903 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3599500 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 1270593012 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 1274192512 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3599500 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 1270593012 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 1274192512 # number of overall MSHR miss cycles
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2016-02-10 10:08:27 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 91364.864865 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 143504.970861 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 143287.989203 # average ReadReq mshr miss latency
2015-07-30 09:42:27 +02:00
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
2016-02-10 10:08:27 +01:00
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76711.433766 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76711.433766 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89987.500000 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 143504.970861 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 143264.280639 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89987.500000 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 143504.970861 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 143264.280639 # average overall mshr miss latency
2014-10-30 05:50:15 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-02-10 10:08:27 +01:00
system.l2c.tags.replacements 1550465 # number of replacements
system.l2c.tags.tagsinuse 63029.233494 # Cycle average of tags in use
system.l2c.tags.total_refs 6222316 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1609843 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 3.865169 # Average number of references to valid blocks.
2015-07-03 16:15:03 +02:00
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-02-10 10:08:27 +01:00
system.l2c.tags.occ_blocks::writebacks 21079.795710 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 246.485529 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 359.766358 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4048.838393 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 9854.606144 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 15763.557433 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 96.147248 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 123.490081 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 3067.505167 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 4557.367994 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3831.673436 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.321652 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003761 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.005490 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.061780 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.150369 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.240533 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001467 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.001884 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.046806 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.069540 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.058467 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.961750 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 10787 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 260 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 48331 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 1394 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 453 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 8932 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 256 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2970 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 5917 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 39033 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.164597 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.003967 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.737473 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 79030194 # Number of tag accesses
system.l2c.tags.data_accesses 79030194 # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks 2899125 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 2899125 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
system.l2c.WritebackClean_hits::total 1 # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data 179542 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 131751 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 311293 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 44871 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 37587 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 82458 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 177447 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 158953 # number of ReadExReq hits
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system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4759 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 555678 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 657090 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 315358 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6220 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4455 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 465798 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 550752 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 288275 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 2855226 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker 6841 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 4759 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 555678 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 834537 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 315358 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 6220 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 4455 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 465798 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 709705 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 288275 # number of demand (read+write) hits
system.l2c.demand_hits::total 3191626 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 6841 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 4759 # number of overall hits
system.l2c.overall_hits::cpu0.inst 555678 # number of overall hits
system.l2c.overall_hits::cpu0.data 834537 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 315358 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 6220 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 4455 # number of overall hits
system.l2c.overall_hits::cpu1.inst 465798 # number of overall hits
system.l2c.overall_hits::cpu1.data 709705 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 288275 # number of overall hits
system.l2c.overall_hits::total 3191626 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 65170 # number of UpgradeReq misses
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system.l2c.UpgradeReq_misses::total 126069 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 13497 # number of SCUpgradeReq misses
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system.l2c.SCUpgradeReq_misses::total 24377 # number of SCUpgradeReq misses
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system.l2c.ReadExReq_misses::cpu1.data 111880 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 660253 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3162 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3066 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst 64369 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 165419 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 348485 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1778 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1336 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst 44941 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 109371 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 194769 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 936696 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker 3162 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 3066 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 64369 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 713792 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 348485 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 1778 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 1336 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 44941 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 221251 # number of demand (read+write) misses
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system.l2c.demand_misses::total 1596949 # number of demand (read+write) misses
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system.l2c.overall_misses::cpu0.data 713792 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 348485 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 1778 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 1336 # number of overall misses
system.l2c.overall_misses::cpu1.inst 44941 # number of overall misses
system.l2c.overall_misses::cpu1.data 221251 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 194769 # number of overall misses
system.l2c.overall_misses::total 1596949 # number of overall misses
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system.l2c.UpgradeReq_miss_latency::total 2194093000 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 212502500 # number of SCUpgradeReq miss cycles
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system.l2c.SCUpgradeReq_miss_latency::total 384236500 # number of SCUpgradeReq miss cycles
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system.l2c.ReadExReq_miss_latency::cpu1.data 16447344495 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 107029778994 # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 446300000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 433489000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst 8809361002 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 23863415500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 62552488059 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 257684000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 192911000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6154592500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 15830077997 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 35289320152 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 153829639210 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 446300000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 433489000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 8809361002 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 114445849999 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 62552488059 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 257684000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 192911000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 6154592500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 32277422492 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 35289320152 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 260859418204 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 446300000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 433489000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 8809361002 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 114445849999 # number of overall miss cycles
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system.l2c.overall_miss_latency::cpu1.dtb.walker 257684000 # number of overall miss cycles
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system.l2c.overall_miss_latency::cpu1.inst 6154592500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 32277422492 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 35289320152 # number of overall miss cycles
system.l2c.overall_miss_latency::total 260859418204 # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks 2899125 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 2899125 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 244712 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 192650 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 437362 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 58368 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 48467 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 106835 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 725820 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 270833 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 996653 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 10003 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7825 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst 620047 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 822509 # number of ReadSharedReq accesses(hits+misses)
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system.l2c.ReadSharedReq_accesses::cpu1.inst 510739 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 660123 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 483044 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 3791922 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 10003 # number of demand (read+write) accesses
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system.l2c.demand_accesses::cpu1.dtb.walker 7998 # number of demand (read+write) accesses
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system.l2c.demand_accesses::cpu1.inst 510739 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 930956 # number of demand (read+write) accesses
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system.l2c.demand_accesses::total 4788575 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 10003 # number of overall (read+write) accesses
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system.l2c.overall_accesses::cpu0.inst 620047 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 1548329 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 663843 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 7998 # number of overall (read+write) accesses
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system.l2c.overall_accesses::total 4788575 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.266313 # miss rate for UpgradeReq accesses
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system.l2c.SCUpgradeReq_miss_rate::total 0.228174 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.755522 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.413096 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.662470 # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.316105 # miss rate for ReadSharedReq accesses
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system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.103813 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.201115 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.524951 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.222306 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.230703 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.087992 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.165683 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.403212 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.247024 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.316105 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.391821 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.103813 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.461008 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.524951 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.222306 # miss rate for demand accesses
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system.l2c.demand_miss_rate::cpu1.inst 0.087992 # miss rate for demand accesses
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system.l2c.overall_miss_rate::cpu1.data 0.237660 # miss rate for overall accesses
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system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 136857.198372 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 144260.426553 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 179498.365953 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 144929.133858 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 144394.461078 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 136948.276629 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 144737.434942 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 181185.507714 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 164225.788527 # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 141144.845035 # average overall miss latency
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system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 144929.133858 # average overall miss latency
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system.l2c.demand_avg_miss_latency::cpu1.inst 136948.276629 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 145885.995959 # average overall miss latency
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system.l2c.demand_avg_miss_latency::total 163348.621781 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 141144.845035 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 141385.844749 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 136857.198372 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 160335.013560 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 179498.365953 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 144929.133858 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 144394.461078 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 136948.276629 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 145885.995959 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 181185.507714 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 163348.621781 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 8828 # number of cycles access was blocked
2014-12-02 12:08:05 +01:00
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-02-10 10:08:27 +01:00
system.l2c.blocked::no_mshrs 81 # number of cycles access was blocked
2014-12-02 12:08:05 +01:00
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2016-02-10 10:08:27 +01:00
system.l2c.avg_blocked_cycles::no_mshrs 108.987654 # average number of cycles each access was blocked
2014-12-02 12:08:05 +01:00
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
2016-02-10 10:08:27 +01:00
system.l2c.writebacks::writebacks 1227229 # number of writebacks
system.l2c.writebacks::total 1227229 # number of writebacks
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system.l2c.ReadSharedReq_mshr_hits::cpu0.data 160 # number of ReadSharedReq MSHR hits
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system.l2c.overall_mshr_hits::total 972 # number of overall MSHR hits
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system.l2c.overall_mshr_misses::total 1595977 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable
2016-02-10 10:08:27 +01:00
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32878 # number of ReadReq MSHR uncacheable
2015-05-05 09:22:39 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
2016-02-10 10:08:27 +01:00
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5427 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 59665 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 32941 # number of WriteReq MSHR uncacheable
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2015-11-06 09:26:50 +01:00
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2016-02-10 10:08:27 +01:00
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2015-05-05 09:22:39 +02:00
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2016-02-10 10:08:27 +01:00
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system.l2c.overall_mshr_miss_latency::total 244770482292 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2396808000 # number of ReadReq MSHR uncacheable cycles
2016-02-10 10:08:27 +01:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5437993027 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7557000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 463514024 # number of ReadReq MSHR uncacheable cycles
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system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 540285518 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 5957305583 # number of WriteReq MSHR uncacheable cycles
2015-11-06 09:26:50 +01:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2396808000 # number of overall MSHR uncacheable cycles
2016-02-10 10:08:27 +01:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10855013092 # number of overall MSHR uncacheable cycles
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system.l2c.overall_mshr_uncacheable_latency::total 14263177634 # number of overall MSHR uncacheable cycles
2015-07-03 16:15:03 +02:00
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2016-02-10 10:08:27 +01:00
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.266313 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.316112 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.288249 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.231240 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.224483 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.228174 # mshr miss rate for SCUpgradeReq accesses
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system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.413096 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.662470 # mshr miss rate for ReadExReq accesses
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system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.103589 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.200921 # mshr miss rate for ReadSharedReq accesses
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system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.230703 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.087530 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.165412 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402843 # mshr miss rate for ReadSharedReq accesses
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system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.316105 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.391821 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.103589 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.460905 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.524830 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.222306 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.230703 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.087530 # mshr miss rate for demand accesses
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system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402843 # mshr miss rate for demand accesses
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system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.391821 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.103589 # mshr miss rate for overall accesses
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system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.524830 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.222306 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.230703 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.087530 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.237468 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402843 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.333289 # mshr miss rate for overall accesses
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system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70524.458464 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70631.360557 # average UpgradeReq mshr miss latency
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system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73545.587960 # average SCUpgradeReq mshr miss latency
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system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 137005.808089 # average ReadExReq mshr miss latency
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system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 131143.898482 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131384.544031 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 126895.941725 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 134274.620202 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169504.703380 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 134925.488751 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 134392.970060 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127047.686075 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 134773.122390 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171201.923182 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 154259.180639 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 131143.898482 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131384.544031 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 126895.941725 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 150341.274493 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169504.703380 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 134925.488751 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 134392.970060 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127047.686075 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 135903.038779 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171201.923182 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 153367.174021 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 131143.898482 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131384.544031 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 126895.941725 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 150341.274493 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169504.703380 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 134925.488751 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 134392.970060 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127047.686075 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 135903.038779 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171201.923182 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 153367.174021 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781 # average ReadReq mshr uncacheable latency
2016-02-10 10:08:27 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165399.143105 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112791.044776 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 85408.885941 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 139208.448018 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164446.132935 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 102249.341030 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155848.412897 # average WriteReq mshr uncacheable latency
2015-11-06 09:26:50 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781 # average overall mshr uncacheable latency
2016-02-10 10:08:27 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164922.181923 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112791.044776 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 93716.697040 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 145706.176668 # average overall mshr uncacheable latency
2014-12-02 12:08:05 +01:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2016-02-10 10:08:27 +01:00
system.membus.trans_dist::ReadReq 59665 # Transaction distribution
system.membus.trans_dist::ReadResp 1004280 # Transaction distribution
system.membus.trans_dist::WriteReq 38225 # Transaction distribution
system.membus.trans_dist::WriteResp 38225 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1333923 # Transaction distribution
system.membus.trans_dist::CleanEvict 260984 # Transaction distribution
system.membus.trans_dist::UpgradeReq 453995 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 297100 # Transaction distribution
system.membus.trans_dist::UpgradeResp 23 # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution
system.membus.trans_dist::ReadExReq 671706 # Transaction distribution
system.membus.trans_dist::ReadExResp 651282 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 944615 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122584 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes)
2016-02-10 10:08:27 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25256 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5471994 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 5619910 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238072 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 238072 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 5857982 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155691 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes)
2016-02-10 10:08:27 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50512 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 180426240 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 180632999 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7268224 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7268224 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 187901223 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 614880 # Total snoops (count)
system.membus.snoop_fanout::samples 4166995 # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2016-02-10 10:08:27 +01:00
system.membus.snoop_fanout::1 4166995 100.00% 100.00% # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2016-02-10 10:08:27 +01:00
system.membus.snoop_fanout::total 4166995 # Request fanout histogram
system.membus.reqLayer0.occupancy 98592998 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.membus.reqLayer1.occupancy 53000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.membus.reqLayer2.occupancy 21315973 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.membus.reqLayer5.occupancy 9342770498 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.membus.respLayer2.occupancy 8446463151 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.membus.respLayer3.occupancy 45344986 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2014-12-02 12:08:05 +01:00
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2016-02-10 10:08:27 +01:00
system.toL2Bus.snoop_filter.tot_requests 12162467 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 6606326 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 1941011 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 162574 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 148386 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 14188 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq 59667 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 4643440 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 38225 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 38225 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 4233094 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 2736996 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 756317 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 379558 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 1135875 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 201 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 201 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 1140134 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 1140134 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 4591007 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10341744 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7350795 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 17692539 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 299067465 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 193620382 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 492687847 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 3308925 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 8737988 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.345814 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.479035 # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-02-10 10:08:27 +01:00
system.toL2Bus.snoop_fanout::0 5730454 65.58% 65.58% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 2993346 34.26% 99.84% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 14188 0.16% 100.00% # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-02-10 10:08:27 +01:00
system.toL2Bus.snoop_fanout::total 8737988 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 9497901955 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.toL2Bus.snoopLayer0.occupancy 2589298 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.toL2Bus.respLayer0.occupancy 5324917465 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.toL2Bus.respLayer1.occupancy 3923923162 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2014-10-30 05:50:15 +01:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
2016-02-10 10:08:27 +01:00
system.cpu0.kern.inst.quiesce 12950 # number of quiesce instructions executed
2014-10-30 05:50:15 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
2016-02-10 10:08:27 +01:00
system.cpu1.kern.inst.quiesce 5465 # number of quiesce instructions executed
2014-10-30 05:50:15 +01:00
---------- End Simulation Statistics ----------
