2007-02-07 06:16:33 +01:00
---------- Begin Simulation Statistics ----------
2016-08-12 15:12:59 +02:00
sim_seconds 0.000522 # Number of seconds simulated
sim_ticks 521659000 # Number of ticks simulated
final_tick 521659000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2012-01-25 18:19:50 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-08-12 15:12:59 +02:00
host_tick_rate 99821577 # Simulator tick rate (ticks/s)
host_mem_usage 236108 # Number of bytes of host memory used
host_seconds 5.23 # Real time elapsed on the host
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-08-12 15:12:59 +02:00
system.physmem.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0 261574 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1 259726 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2 254844 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3 256223 # Number of bytes read from this memory
system.physmem.bytes_read::cpu4 261709 # Number of bytes read from this memory
system.physmem.bytes_read::cpu5 259188 # Number of bytes read from this memory
system.physmem.bytes_read::cpu6 257071 # Number of bytes read from this memory
system.physmem.bytes_read::cpu7 253171 # Number of bytes read from this memory
system.physmem.bytes_read::total 2063506 # Number of bytes read from this memory
system.physmem.bytes_written::writebacks 1454400 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0 5412 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1 5468 # Number of bytes written to this memory
system.physmem.bytes_written::cpu2 5497 # Number of bytes written to this memory
system.physmem.bytes_written::cpu3 5381 # Number of bytes written to this memory
system.physmem.bytes_written::cpu4 5437 # Number of bytes written to this memory
system.physmem.bytes_written::cpu5 5503 # Number of bytes written to this memory
system.physmem.bytes_written::cpu6 5505 # Number of bytes written to this memory
system.physmem.bytes_written::cpu7 5688 # Number of bytes written to this memory
system.physmem.bytes_written::total 1498291 # Number of bytes written to this memory
system.physmem.num_reads::cpu0 13795 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1 13774 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2 13680 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3 13673 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu4 13678 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu5 13740 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu6 13765 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu7 13771 # Number of read requests responded to by this memory
system.physmem.num_reads::total 109876 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 22725 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0 5412 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1 5468 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2 5497 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu3 5381 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu4 5437 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu5 5503 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu6 5505 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu7 5688 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66616 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0 501427178 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1 497884633 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2 488526029 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3 491169519 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu4 501685967 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu5 496853308 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu6 492795102 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu7 485318954 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3955660690 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2788028195 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0 10374593 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1 10481943 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2 10537535 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu3 10315168 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu4 10422517 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu5 10549037 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu6 10552871 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu7 10903675 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2872165533 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2788028195 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0 511801771 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1 508366577 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2 499063565 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3 501484686 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu4 512108485 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu5 507402345 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu6 503347973 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu7 496222628 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6827826224 # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2016-08-12 15:12:59 +02:00
system.cpu0.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.cpu0.num_reads 99316 # number of read accesses completed
system.cpu0.num_writes 55523 # number of write accesses completed
system.cpu0.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.cpu0.l1c.tags.replacements 22284 # number of replacements
system.cpu0.l1c.tags.tagsinuse 390.956341 # Cycle average of tags in use
system.cpu0.l1c.tags.total_refs 13404 # Total number of references to valid blocks.
system.cpu0.l1c.tags.sampled_refs 22693 # Sample count of references to valid blocks.
system.cpu0.l1c.tags.avg_refs 0.590667 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-08-12 15:12:59 +02:00
system.cpu0.l1c.tags.occ_blocks::cpu0 390.956341 # Average occupied blocks per requestor
system.cpu0.l1c.tags.occ_percent::cpu0 0.763587 # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_percent::total 0.763587 # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
system.cpu0.l1c.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id
system.cpu0.l1c.tags.tag_accesses 337730 # Number of tag accesses
system.cpu0.l1c.tags.data_accesses 337730 # Number of data accesses
system.cpu0.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.cpu0.l1c.ReadReq_hits::cpu0 8729 # number of ReadReq hits
system.cpu0.l1c.ReadReq_hits::total 8729 # number of ReadReq hits
system.cpu0.l1c.WriteReq_hits::cpu0 1158 # number of WriteReq hits
system.cpu0.l1c.WriteReq_hits::total 1158 # number of WriteReq hits
system.cpu0.l1c.demand_hits::cpu0 9887 # number of demand (read+write) hits
system.cpu0.l1c.demand_hits::total 9887 # number of demand (read+write) hits
system.cpu0.l1c.overall_hits::cpu0 9887 # number of overall hits
system.cpu0.l1c.overall_hits::total 9887 # number of overall hits
system.cpu0.l1c.ReadReq_misses::cpu0 36226 # number of ReadReq misses
system.cpu0.l1c.ReadReq_misses::total 36226 # number of ReadReq misses
system.cpu0.l1c.WriteReq_misses::cpu0 24124 # number of WriteReq misses
system.cpu0.l1c.WriteReq_misses::total 24124 # number of WriteReq misses
system.cpu0.l1c.demand_misses::cpu0 60350 # number of demand (read+write) misses
system.cpu0.l1c.demand_misses::total 60350 # number of demand (read+write) misses
system.cpu0.l1c.overall_misses::cpu0 60350 # number of overall misses
system.cpu0.l1c.overall_misses::total 60350 # number of overall misses
system.cpu0.l1c.ReadReq_miss_latency::cpu0 712731918 # number of ReadReq miss cycles
system.cpu0.l1c.ReadReq_miss_latency::total 712731918 # number of ReadReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::cpu0 593276823 # number of WriteReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::total 593276823 # number of WriteReq miss cycles
system.cpu0.l1c.demand_miss_latency::cpu0 1306008741 # number of demand (read+write) miss cycles
system.cpu0.l1c.demand_miss_latency::total 1306008741 # number of demand (read+write) miss cycles
system.cpu0.l1c.overall_miss_latency::cpu0 1306008741 # number of overall miss cycles
system.cpu0.l1c.overall_miss_latency::total 1306008741 # number of overall miss cycles
system.cpu0.l1c.ReadReq_accesses::cpu0 44955 # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.ReadReq_accesses::total 44955 # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::cpu0 25282 # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::total 25282 # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.demand_accesses::cpu0 70237 # number of demand (read+write) accesses
system.cpu0.l1c.demand_accesses::total 70237 # number of demand (read+write) accesses
system.cpu0.l1c.overall_accesses::cpu0 70237 # number of overall (read+write) accesses
system.cpu0.l1c.overall_accesses::total 70237 # number of overall (read+write) accesses
system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805828 # miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_miss_rate::total 0.805828 # miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954197 # miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_miss_rate::total 0.954197 # miss rate for WriteReq accesses
system.cpu0.l1c.demand_miss_rate::cpu0 0.859234 # miss rate for demand accesses
system.cpu0.l1c.demand_miss_rate::total 0.859234 # miss rate for demand accesses
system.cpu0.l1c.overall_miss_rate::cpu0 0.859234 # miss rate for overall accesses
system.cpu0.l1c.overall_miss_rate::total 0.859234 # miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 19674.596091 # average ReadReq miss latency
system.cpu0.l1c.ReadReq_avg_miss_latency::total 19674.596091 # average ReadReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 24592.804800 # average WriteReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::total 24592.804800 # average WriteReq miss latency
system.cpu0.l1c.demand_avg_miss_latency::cpu0 21640.575659 # average overall miss latency
system.cpu0.l1c.demand_avg_miss_latency::total 21640.575659 # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::cpu0 21640.575659 # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::total 21640.575659 # average overall miss latency
system.cpu0.l1c.blocked_cycles::no_mshrs 872655 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu0.l1c.blocked::no_mshrs 66710 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu0.l1c.avg_blocked_cycles::no_mshrs 13.081322 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu0.l1c.writebacks::writebacks 9923 # number of writebacks
system.cpu0.l1c.writebacks::total 9923 # number of writebacks
system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36226 # number of ReadReq MSHR misses
system.cpu0.l1c.ReadReq_mshr_misses::total 36226 # number of ReadReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::cpu0 24124 # number of WriteReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::total 24124 # number of WriteReq MSHR misses
system.cpu0.l1c.demand_mshr_misses::cpu0 60350 # number of demand (read+write) MSHR misses
system.cpu0.l1c.demand_mshr_misses::total 60350 # number of demand (read+write) MSHR misses
system.cpu0.l1c.overall_mshr_misses::cpu0 60350 # number of overall MSHR misses
system.cpu0.l1c.overall_mshr_misses::total 60350 # number of overall MSHR misses
system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9863 # number of ReadReq MSHR uncacheable
system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9863 # number of ReadReq MSHR uncacheable
system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5414 # number of WriteReq MSHR uncacheable
system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5414 # number of WriteReq MSHR uncacheable
system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15277 # number of overall MSHR uncacheable misses
system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15277 # number of overall MSHR uncacheable misses
system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 676507918 # number of ReadReq MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_miss_latency::total 676507918 # number of ReadReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 569152823 # number of WriteReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::total 569152823 # number of WriteReq MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1245660741 # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::total 1245660741 # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1245660741 # number of overall MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::total 1245660741 # number of overall MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 770027425 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 770027425 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 770027425 # number of overall MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::total 770027425 # number of overall MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.805828 # mshr miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.805828 # mshr miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954197 # mshr miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954197 # mshr miss rate for WriteReq accesses
system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859234 # mshr miss rate for demand accesses
system.cpu0.l1c.demand_mshr_miss_rate::total 0.859234 # mshr miss rate for demand accesses
system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859234 # mshr miss rate for overall accesses
system.cpu0.l1c.overall_mshr_miss_rate::total 0.859234 # mshr miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 18674.651300 # average ReadReq mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 18674.651300 # average ReadReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 23592.804800 # average WriteReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 23592.804800 # average WriteReq mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20640.608799 # average overall mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20640.608799 # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20640.608799 # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20640.608799 # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 78072.333469 # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78072.333469 # average ReadReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 50404.361131 # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 50404.361131 # average overall mshr uncacheable latency
system.cpu1.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.cpu1.num_reads 99894 # number of read accesses completed
system.cpu1.num_writes 55231 # number of write accesses completed
system.cpu1.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.cpu1.l1c.tags.replacements 22436 # number of replacements
system.cpu1.l1c.tags.tagsinuse 391.315294 # Cycle average of tags in use
system.cpu1.l1c.tags.total_refs 13542 # Total number of references to valid blocks.
system.cpu1.l1c.tags.sampled_refs 22813 # Sample count of references to valid blocks.
system.cpu1.l1c.tags.avg_refs 0.593609 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-08-12 15:12:59 +02:00
system.cpu1.l1c.tags.occ_blocks::cpu1 391.315294 # Average occupied blocks per requestor
system.cpu1.l1c.tags.occ_percent::cpu1 0.764288 # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_percent::total 0.764288 # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_task_id_blocks::1024 377 # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::0 366 # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id
system.cpu1.l1c.tags.occ_task_id_percent::1024 0.736328 # Percentage of cache occupancy per task id
system.cpu1.l1c.tags.tag_accesses 338824 # Number of tag accesses
system.cpu1.l1c.tags.data_accesses 338824 # Number of data accesses
system.cpu1.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.cpu1.l1c.ReadReq_hits::cpu1 8855 # number of ReadReq hits
system.cpu1.l1c.ReadReq_hits::total 8855 # number of ReadReq hits
system.cpu1.l1c.WriteReq_hits::cpu1 1149 # number of WriteReq hits
system.cpu1.l1c.WriteReq_hits::total 1149 # number of WriteReq hits
system.cpu1.l1c.demand_hits::cpu1 10004 # number of demand (read+write) hits
system.cpu1.l1c.demand_hits::total 10004 # number of demand (read+write) hits
system.cpu1.l1c.overall_hits::cpu1 10004 # number of overall hits
system.cpu1.l1c.overall_hits::total 10004 # number of overall hits
system.cpu1.l1c.ReadReq_misses::cpu1 36651 # number of ReadReq misses
system.cpu1.l1c.ReadReq_misses::total 36651 # number of ReadReq misses
system.cpu1.l1c.WriteReq_misses::cpu1 23831 # number of WriteReq misses
system.cpu1.l1c.WriteReq_misses::total 23831 # number of WriteReq misses
system.cpu1.l1c.demand_misses::cpu1 60482 # number of demand (read+write) misses
system.cpu1.l1c.demand_misses::total 60482 # number of demand (read+write) misses
system.cpu1.l1c.overall_misses::cpu1 60482 # number of overall misses
system.cpu1.l1c.overall_misses::total 60482 # number of overall misses
system.cpu1.l1c.ReadReq_miss_latency::cpu1 724296905 # number of ReadReq miss cycles
system.cpu1.l1c.ReadReq_miss_latency::total 724296905 # number of ReadReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::cpu1 578481683 # number of WriteReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::total 578481683 # number of WriteReq miss cycles
system.cpu1.l1c.demand_miss_latency::cpu1 1302778588 # number of demand (read+write) miss cycles
system.cpu1.l1c.demand_miss_latency::total 1302778588 # number of demand (read+write) miss cycles
system.cpu1.l1c.overall_miss_latency::cpu1 1302778588 # number of overall miss cycles
system.cpu1.l1c.overall_miss_latency::total 1302778588 # number of overall miss cycles
system.cpu1.l1c.ReadReq_accesses::cpu1 45506 # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.ReadReq_accesses::total 45506 # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::cpu1 24980 # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::total 24980 # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.demand_accesses::cpu1 70486 # number of demand (read+write) accesses
system.cpu1.l1c.demand_accesses::total 70486 # number of demand (read+write) accesses
system.cpu1.l1c.overall_accesses::cpu1 70486 # number of overall (read+write) accesses
system.cpu1.l1c.overall_accesses::total 70486 # number of overall (read+write) accesses
system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805410 # miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_miss_rate::total 0.805410 # miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954003 # miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_miss_rate::total 0.954003 # miss rate for WriteReq accesses
system.cpu1.l1c.demand_miss_rate::cpu1 0.858071 # miss rate for demand accesses
system.cpu1.l1c.demand_miss_rate::total 0.858071 # miss rate for demand accesses
system.cpu1.l1c.overall_miss_rate::cpu1 0.858071 # miss rate for overall accesses
system.cpu1.l1c.overall_miss_rate::total 0.858071 # miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 19761.995716 # average ReadReq miss latency
system.cpu1.l1c.ReadReq_avg_miss_latency::total 19761.995716 # average ReadReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 24274.335236 # average WriteReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::total 24274.335236 # average WriteReq miss latency
system.cpu1.l1c.demand_avg_miss_latency::cpu1 21539.938957 # average overall miss latency
system.cpu1.l1c.demand_avg_miss_latency::total 21539.938957 # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::cpu1 21539.938957 # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::total 21539.938957 # average overall miss latency
system.cpu1.l1c.blocked_cycles::no_mshrs 869423 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu1.l1c.blocked::no_mshrs 66885 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.998774 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu1.l1c.writebacks::writebacks 9819 # number of writebacks
system.cpu1.l1c.writebacks::total 9819 # number of writebacks
system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36651 # number of ReadReq MSHR misses
system.cpu1.l1c.ReadReq_mshr_misses::total 36651 # number of ReadReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23831 # number of WriteReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::total 23831 # number of WriteReq MSHR misses
system.cpu1.l1c.demand_mshr_misses::cpu1 60482 # number of demand (read+write) MSHR misses
system.cpu1.l1c.demand_mshr_misses::total 60482 # number of demand (read+write) MSHR misses
system.cpu1.l1c.overall_mshr_misses::cpu1 60482 # number of overall MSHR misses
system.cpu1.l1c.overall_mshr_misses::total 60482 # number of overall MSHR misses
system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9872 # number of ReadReq MSHR uncacheable
system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9872 # number of ReadReq MSHR uncacheable
system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5469 # number of WriteReq MSHR uncacheable
system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5469 # number of WriteReq MSHR uncacheable
system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15341 # number of overall MSHR uncacheable misses
system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15341 # number of overall MSHR uncacheable misses
system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 687646905 # number of ReadReq MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_miss_latency::total 687646905 # number of ReadReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 554650683 # number of WriteReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::total 554650683 # number of WriteReq MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1242297588 # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::total 1242297588 # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1242297588 # number of overall MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::total 1242297588 # number of overall MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 771585814 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 771585814 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 771585814 # number of overall MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::total 771585814 # number of overall MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805410 # mshr miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805410 # mshr miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954003 # mshr miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954003 # mshr miss rate for WriteReq accesses
system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858071 # mshr miss rate for demand accesses
system.cpu1.l1c.demand_mshr_miss_rate::total 0.858071 # mshr miss rate for demand accesses
system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858071 # mshr miss rate for overall accesses
system.cpu1.l1c.overall_mshr_miss_rate::total 0.858071 # mshr miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 18762.023001 # average ReadReq mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 18762.023001 # average ReadReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 23274.335236 # average WriteReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 23274.335236 # average WriteReq mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20539.955491 # average overall mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20539.955491 # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20539.955491 # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20539.955491 # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 78159.016815 # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78159.016815 # average ReadReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 50295.666123 # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 50295.666123 # average overall mshr uncacheable latency
system.cpu2.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.cpu2.num_reads 99314 # number of read accesses completed
system.cpu2.num_writes 55477 # number of write accesses completed
system.cpu2.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.cpu2.l1c.tags.replacements 22237 # number of replacements
system.cpu2.l1c.tags.tagsinuse 390.931192 # Cycle average of tags in use
system.cpu2.l1c.tags.total_refs 13493 # Total number of references to valid blocks.
system.cpu2.l1c.tags.sampled_refs 22636 # Sample count of references to valid blocks.
system.cpu2.l1c.tags.avg_refs 0.596086 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-08-12 15:12:59 +02:00
system.cpu2.l1c.tags.occ_blocks::cpu2 390.931192 # Average occupied blocks per requestor
system.cpu2.l1c.tags.occ_percent::cpu2 0.763537 # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_percent::total 0.763537 # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::0 379 # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
system.cpu2.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id
system.cpu2.l1c.tags.tag_accesses 337492 # Number of tag accesses
system.cpu2.l1c.tags.data_accesses 337492 # Number of data accesses
system.cpu2.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.cpu2.l1c.ReadReq_hits::cpu2 8705 # number of ReadReq hits
system.cpu2.l1c.ReadReq_hits::total 8705 # number of ReadReq hits
system.cpu2.l1c.WriteReq_hits::cpu2 1188 # number of WriteReq hits
system.cpu2.l1c.WriteReq_hits::total 1188 # number of WriteReq hits
system.cpu2.l1c.demand_hits::cpu2 9893 # number of demand (read+write) hits
system.cpu2.l1c.demand_hits::total 9893 # number of demand (read+write) hits
system.cpu2.l1c.overall_hits::cpu2 9893 # number of overall hits
system.cpu2.l1c.overall_hits::total 9893 # number of overall hits
system.cpu2.l1c.ReadReq_misses::cpu2 36190 # number of ReadReq misses
system.cpu2.l1c.ReadReq_misses::total 36190 # number of ReadReq misses
2016-04-21 10:48:24 +02:00
system.cpu2.l1c.WriteReq_misses::cpu2 24129 # number of WriteReq misses
system.cpu2.l1c.WriteReq_misses::total 24129 # number of WriteReq misses
2016-08-12 15:12:59 +02:00
system.cpu2.l1c.demand_misses::cpu2 60319 # number of demand (read+write) misses
system.cpu2.l1c.demand_misses::total 60319 # number of demand (read+write) misses
system.cpu2.l1c.overall_misses::cpu2 60319 # number of overall misses
system.cpu2.l1c.overall_misses::total 60319 # number of overall misses
system.cpu2.l1c.ReadReq_miss_latency::cpu2 713868287 # number of ReadReq miss cycles
system.cpu2.l1c.ReadReq_miss_latency::total 713868287 # number of ReadReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::cpu2 591883556 # number of WriteReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::total 591883556 # number of WriteReq miss cycles
system.cpu2.l1c.demand_miss_latency::cpu2 1305751843 # number of demand (read+write) miss cycles
system.cpu2.l1c.demand_miss_latency::total 1305751843 # number of demand (read+write) miss cycles
system.cpu2.l1c.overall_miss_latency::cpu2 1305751843 # number of overall miss cycles
system.cpu2.l1c.overall_miss_latency::total 1305751843 # number of overall miss cycles
system.cpu2.l1c.ReadReq_accesses::cpu2 44895 # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.ReadReq_accesses::total 44895 # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::cpu2 25317 # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::total 25317 # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.demand_accesses::cpu2 70212 # number of demand (read+write) accesses
system.cpu2.l1c.demand_accesses::total 70212 # number of demand (read+write) accesses
system.cpu2.l1c.overall_accesses::cpu2 70212 # number of overall (read+write) accesses
system.cpu2.l1c.overall_accesses::total 70212 # number of overall (read+write) accesses
system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806103 # miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_miss_rate::total 0.806103 # miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953075 # miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_miss_rate::total 0.953075 # miss rate for WriteReq accesses
system.cpu2.l1c.demand_miss_rate::cpu2 0.859098 # miss rate for demand accesses
system.cpu2.l1c.demand_miss_rate::total 0.859098 # miss rate for demand accesses
system.cpu2.l1c.overall_miss_rate::cpu2 0.859098 # miss rate for overall accesses
system.cpu2.l1c.overall_miss_rate::total 0.859098 # miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 19725.567477 # average ReadReq miss latency
system.cpu2.l1c.ReadReq_avg_miss_latency::total 19725.567477 # average ReadReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 24529.966265 # average WriteReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::total 24529.966265 # average WriteReq miss latency
system.cpu2.l1c.demand_avg_miss_latency::cpu2 21647.438502 # average overall miss latency
system.cpu2.l1c.demand_avg_miss_latency::total 21647.438502 # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::cpu2 21647.438502 # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::total 21647.438502 # average overall miss latency
system.cpu2.l1c.blocked_cycles::no_mshrs 871392 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu2.l1c.blocked::no_mshrs 66762 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu2.l1c.avg_blocked_cycles::no_mshrs 13.052215 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu2.l1c.writebacks::writebacks 9753 # number of writebacks
system.cpu2.l1c.writebacks::total 9753 # number of writebacks
system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36190 # number of ReadReq MSHR misses
system.cpu2.l1c.ReadReq_mshr_misses::total 36190 # number of ReadReq MSHR misses
2016-04-21 10:48:24 +02:00
system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24129 # number of WriteReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::total 24129 # number of WriteReq MSHR misses
2016-08-12 15:12:59 +02:00
system.cpu2.l1c.demand_mshr_misses::cpu2 60319 # number of demand (read+write) MSHR misses
system.cpu2.l1c.demand_mshr_misses::total 60319 # number of demand (read+write) MSHR misses
system.cpu2.l1c.overall_mshr_misses::cpu2 60319 # number of overall MSHR misses
system.cpu2.l1c.overall_mshr_misses::total 60319 # number of overall MSHR misses
system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9852 # number of ReadReq MSHR uncacheable
system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9852 # number of ReadReq MSHR uncacheable
system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5498 # number of WriteReq MSHR uncacheable
system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5498 # number of WriteReq MSHR uncacheable
system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15350 # number of overall MSHR uncacheable misses
system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15350 # number of overall MSHR uncacheable misses
system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 677680287 # number of ReadReq MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_miss_latency::total 677680287 # number of ReadReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 567754556 # number of WriteReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::total 567754556 # number of WriteReq MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1245434843 # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::total 1245434843 # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1245434843 # number of overall MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::total 1245434843 # number of overall MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 769926007 # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 769926007 # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 769926007 # number of overall MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::total 769926007 # number of overall MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806103 # mshr miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806103 # mshr miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953075 # mshr miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953075 # mshr miss rate for WriteReq accesses
system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859098 # mshr miss rate for demand accesses
system.cpu2.l1c.demand_mshr_miss_rate::total 0.859098 # mshr miss rate for demand accesses
system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859098 # mshr miss rate for overall accesses
system.cpu2.l1c.overall_mshr_miss_rate::total 0.859098 # mshr miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 18725.622741 # average ReadReq mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 18725.622741 # average ReadReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 23529.966265 # average WriteReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 23529.966265 # average WriteReq mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20647.471659 # average overall mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20647.471659 # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20647.471659 # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20647.471659 # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 78149.208993 # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78149.208993 # average ReadReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 50158.046059 # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 50158.046059 # average overall mshr uncacheable latency
system.cpu3.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.cpu3.num_reads 99963 # number of read accesses completed
system.cpu3.num_writes 54829 # number of write accesses completed
system.cpu3.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.cpu3.l1c.tags.replacements 22502 # number of replacements
system.cpu3.l1c.tags.tagsinuse 392.266593 # Cycle average of tags in use
system.cpu3.l1c.tags.total_refs 13442 # Total number of references to valid blocks.
system.cpu3.l1c.tags.sampled_refs 22904 # Sample count of references to valid blocks.
system.cpu3.l1c.tags.avg_refs 0.586884 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-08-12 15:12:59 +02:00
system.cpu3.l1c.tags.occ_blocks::cpu3 392.266593 # Average occupied blocks per requestor
system.cpu3.l1c.tags.occ_percent::cpu3 0.766146 # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_percent::total 0.766146 # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::0 394 # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
system.cpu3.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
system.cpu3.l1c.tags.tag_accesses 338127 # Number of tag accesses
system.cpu3.l1c.tags.data_accesses 338127 # Number of data accesses
system.cpu3.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.cpu3.l1c.ReadReq_hits::cpu3 8758 # number of ReadReq hits
system.cpu3.l1c.ReadReq_hits::total 8758 # number of ReadReq hits
system.cpu3.l1c.WriteReq_hits::cpu3 1160 # number of WriteReq hits
system.cpu3.l1c.WriteReq_hits::total 1160 # number of WriteReq hits
system.cpu3.l1c.demand_hits::cpu3 9918 # number of demand (read+write) hits
system.cpu3.l1c.demand_hits::total 9918 # number of demand (read+write) hits
system.cpu3.l1c.overall_hits::cpu3 9918 # number of overall hits
system.cpu3.l1c.overall_hits::total 9918 # number of overall hits
system.cpu3.l1c.ReadReq_misses::cpu3 36654 # number of ReadReq misses
system.cpu3.l1c.ReadReq_misses::total 36654 # number of ReadReq misses
system.cpu3.l1c.WriteReq_misses::cpu3 23751 # number of WriteReq misses
system.cpu3.l1c.WriteReq_misses::total 23751 # number of WriteReq misses
system.cpu3.l1c.demand_misses::cpu3 60405 # number of demand (read+write) misses
system.cpu3.l1c.demand_misses::total 60405 # number of demand (read+write) misses
system.cpu3.l1c.overall_misses::cpu3 60405 # number of overall misses
system.cpu3.l1c.overall_misses::total 60405 # number of overall misses
system.cpu3.l1c.ReadReq_miss_latency::cpu3 726630781 # number of ReadReq miss cycles
system.cpu3.l1c.ReadReq_miss_latency::total 726630781 # number of ReadReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::cpu3 580088175 # number of WriteReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::total 580088175 # number of WriteReq miss cycles
system.cpu3.l1c.demand_miss_latency::cpu3 1306718956 # number of demand (read+write) miss cycles
system.cpu3.l1c.demand_miss_latency::total 1306718956 # number of demand (read+write) miss cycles
system.cpu3.l1c.overall_miss_latency::cpu3 1306718956 # number of overall miss cycles
system.cpu3.l1c.overall_miss_latency::total 1306718956 # number of overall miss cycles
system.cpu3.l1c.ReadReq_accesses::cpu3 45412 # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.ReadReq_accesses::total 45412 # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::cpu3 24911 # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::total 24911 # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.demand_accesses::cpu3 70323 # number of demand (read+write) accesses
system.cpu3.l1c.demand_accesses::total 70323 # number of demand (read+write) accesses
system.cpu3.l1c.overall_accesses::cpu3 70323 # number of overall (read+write) accesses
system.cpu3.l1c.overall_accesses::total 70323 # number of overall (read+write) accesses
system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807143 # miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_miss_rate::total 0.807143 # miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953434 # miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_miss_rate::total 0.953434 # miss rate for WriteReq accesses
system.cpu3.l1c.demand_miss_rate::cpu3 0.858965 # miss rate for demand accesses
system.cpu3.l1c.demand_miss_rate::total 0.858965 # miss rate for demand accesses
system.cpu3.l1c.overall_miss_rate::cpu3 0.858965 # miss rate for overall accesses
system.cpu3.l1c.overall_miss_rate::total 0.858965 # miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 19824.051427 # average ReadReq miss latency
system.cpu3.l1c.ReadReq_avg_miss_latency::total 19824.051427 # average ReadReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 24423.736895 # average WriteReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::total 24423.736895 # average WriteReq miss latency
system.cpu3.l1c.demand_avg_miss_latency::cpu3 21632.629021 # average overall miss latency
system.cpu3.l1c.demand_avg_miss_latency::total 21632.629021 # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::cpu3 21632.629021 # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::total 21632.629021 # average overall miss latency
system.cpu3.l1c.blocked_cycles::no_mshrs 870625 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu3.l1c.blocked::no_mshrs 66788 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu3.l1c.avg_blocked_cycles::no_mshrs 13.035650 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu3.l1c.writebacks::writebacks 9808 # number of writebacks
system.cpu3.l1c.writebacks::total 9808 # number of writebacks
system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36654 # number of ReadReq MSHR misses
system.cpu3.l1c.ReadReq_mshr_misses::total 36654 # number of ReadReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23751 # number of WriteReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::total 23751 # number of WriteReq MSHR misses
system.cpu3.l1c.demand_mshr_misses::cpu3 60405 # number of demand (read+write) MSHR misses
system.cpu3.l1c.demand_mshr_misses::total 60405 # number of demand (read+write) MSHR misses
system.cpu3.l1c.overall_mshr_misses::cpu3 60405 # number of overall MSHR misses
system.cpu3.l1c.overall_mshr_misses::total 60405 # number of overall MSHR misses
system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9824 # number of ReadReq MSHR uncacheable
system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9824 # number of ReadReq MSHR uncacheable
system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5382 # number of WriteReq MSHR uncacheable
system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5382 # number of WriteReq MSHR uncacheable
system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15206 # number of overall MSHR uncacheable misses
system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15206 # number of overall MSHR uncacheable misses
system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 689977781 # number of ReadReq MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_miss_latency::total 689977781 # number of ReadReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 556338175 # number of WriteReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::total 556338175 # number of WriteReq MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1246315956 # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::total 1246315956 # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1246315956 # number of overall MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::total 1246315956 # number of overall MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 768661965 # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 768661965 # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 768661965 # number of overall MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::total 768661965 # number of overall MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807143 # mshr miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807143 # mshr miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953434 # mshr miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953434 # mshr miss rate for WriteReq accesses
system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858965 # mshr miss rate for demand accesses
system.cpu3.l1c.demand_mshr_miss_rate::total 0.858965 # mshr miss rate for demand accesses
system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858965 # mshr miss rate for overall accesses
system.cpu3.l1c.overall_mshr_miss_rate::total 0.858965 # mshr miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 18824.078709 # average ReadReq mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 18824.078709 # average ReadReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 23423.778999 # average WriteReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 23423.778999 # average WriteReq mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20632.662131 # average overall mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20632.662131 # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20632.662131 # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20632.662131 # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 78243.278196 # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78243.278196 # average ReadReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 50549.912206 # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 50549.912206 # average overall mshr uncacheable latency
system.cpu4.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.cpu4.num_reads 98794 # number of read accesses completed
system.cpu4.num_writes 54937 # number of write accesses completed
system.cpu4.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.cpu4.l1c.tags.replacements 22508 # number of replacements
system.cpu4.l1c.tags.tagsinuse 392.668091 # Cycle average of tags in use
system.cpu4.l1c.tags.total_refs 13409 # Total number of references to valid blocks.
system.cpu4.l1c.tags.sampled_refs 22922 # Sample count of references to valid blocks.
system.cpu4.l1c.tags.avg_refs 0.584984 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-08-12 15:12:59 +02:00
system.cpu4.l1c.tags.occ_blocks::cpu4 392.668091 # Average occupied blocks per requestor
system.cpu4.l1c.tags.occ_percent::cpu4 0.766930 # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_percent::total 0.766930 # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_task_id_blocks::1024 414 # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::0 402 # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id
system.cpu4.l1c.tags.occ_task_id_percent::1024 0.808594 # Percentage of cache occupancy per task id
system.cpu4.l1c.tags.tag_accesses 337369 # Number of tag accesses
system.cpu4.l1c.tags.data_accesses 337369 # Number of data accesses
system.cpu4.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.cpu4.l1c.ReadReq_hits::cpu4 8739 # number of ReadReq hits
system.cpu4.l1c.ReadReq_hits::total 8739 # number of ReadReq hits
system.cpu4.l1c.WriteReq_hits::cpu4 1134 # number of WriteReq hits
system.cpu4.l1c.WriteReq_hits::total 1134 # number of WriteReq hits
system.cpu4.l1c.demand_hits::cpu4 9873 # number of demand (read+write) hits
system.cpu4.l1c.demand_hits::total 9873 # number of demand (read+write) hits
system.cpu4.l1c.overall_hits::cpu4 9873 # number of overall hits
system.cpu4.l1c.overall_hits::total 9873 # number of overall hits
system.cpu4.l1c.ReadReq_misses::cpu4 36311 # number of ReadReq misses
system.cpu4.l1c.ReadReq_misses::total 36311 # number of ReadReq misses
system.cpu4.l1c.WriteReq_misses::cpu4 23983 # number of WriteReq misses
system.cpu4.l1c.WriteReq_misses::total 23983 # number of WriteReq misses
system.cpu4.l1c.demand_misses::cpu4 60294 # number of demand (read+write) misses
system.cpu4.l1c.demand_misses::total 60294 # number of demand (read+write) misses
system.cpu4.l1c.overall_misses::cpu4 60294 # number of overall misses
system.cpu4.l1c.overall_misses::total 60294 # number of overall misses
system.cpu4.l1c.ReadReq_miss_latency::cpu4 724331862 # number of ReadReq miss cycles
system.cpu4.l1c.ReadReq_miss_latency::total 724331862 # number of ReadReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::cpu4 586488864 # number of WriteReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::total 586488864 # number of WriteReq miss cycles
system.cpu4.l1c.demand_miss_latency::cpu4 1310820726 # number of demand (read+write) miss cycles
system.cpu4.l1c.demand_miss_latency::total 1310820726 # number of demand (read+write) miss cycles
system.cpu4.l1c.overall_miss_latency::cpu4 1310820726 # number of overall miss cycles
system.cpu4.l1c.overall_miss_latency::total 1310820726 # number of overall miss cycles
system.cpu4.l1c.ReadReq_accesses::cpu4 45050 # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.ReadReq_accesses::total 45050 # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::cpu4 25117 # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::total 25117 # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.demand_accesses::cpu4 70167 # number of demand (read+write) accesses
system.cpu4.l1c.demand_accesses::total 70167 # number of demand (read+write) accesses
system.cpu4.l1c.overall_accesses::cpu4 70167 # number of overall (read+write) accesses
system.cpu4.l1c.overall_accesses::total 70167 # number of overall (read+write) accesses
system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.806016 # miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_miss_rate::total 0.806016 # miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954851 # miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_miss_rate::total 0.954851 # miss rate for WriteReq accesses
system.cpu4.l1c.demand_miss_rate::cpu4 0.859293 # miss rate for demand accesses
system.cpu4.l1c.demand_miss_rate::total 0.859293 # miss rate for demand accesses
system.cpu4.l1c.overall_miss_rate::cpu4 0.859293 # miss rate for overall accesses
system.cpu4.l1c.overall_miss_rate::total 0.859293 # miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 19948.000936 # average ReadReq miss latency
system.cpu4.l1c.ReadReq_avg_miss_latency::total 19948.000936 # average ReadReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 24454.357837 # average WriteReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::total 24454.357837 # average WriteReq miss latency
system.cpu4.l1c.demand_avg_miss_latency::cpu4 21740.483730 # average overall miss latency
system.cpu4.l1c.demand_avg_miss_latency::total 21740.483730 # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::cpu4 21740.483730 # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::total 21740.483730 # average overall miss latency
system.cpu4.l1c.blocked_cycles::no_mshrs 869421 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu4.l1c.blocked::no_mshrs 66532 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu4.l1c.avg_blocked_cycles::no_mshrs 13.067712 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu4.l1c.writebacks::writebacks 9883 # number of writebacks
system.cpu4.l1c.writebacks::total 9883 # number of writebacks
system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36311 # number of ReadReq MSHR misses
system.cpu4.l1c.ReadReq_mshr_misses::total 36311 # number of ReadReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23983 # number of WriteReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::total 23983 # number of WriteReq MSHR misses
system.cpu4.l1c.demand_mshr_misses::cpu4 60294 # number of demand (read+write) MSHR misses
system.cpu4.l1c.demand_mshr_misses::total 60294 # number of demand (read+write) MSHR misses
system.cpu4.l1c.overall_mshr_misses::cpu4 60294 # number of overall MSHR misses
system.cpu4.l1c.overall_mshr_misses::total 60294 # number of overall MSHR misses
system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9741 # number of ReadReq MSHR uncacheable
system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9741 # number of ReadReq MSHR uncacheable
system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5439 # number of WriteReq MSHR uncacheable
system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5439 # number of WriteReq MSHR uncacheable
system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15180 # number of overall MSHR uncacheable misses
system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15180 # number of overall MSHR uncacheable misses
system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 688022862 # number of ReadReq MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_miss_latency::total 688022862 # number of ReadReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 562507864 # number of WriteReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::total 562507864 # number of WriteReq MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1250530726 # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::total 1250530726 # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1250530726 # number of overall MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::total 1250530726 # number of overall MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 763019844 # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 763019844 # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 763019844 # number of overall MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::total 763019844 # number of overall MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.806016 # mshr miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.806016 # mshr miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954851 # mshr miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954851 # mshr miss rate for WriteReq accesses
system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859293 # mshr miss rate for demand accesses
system.cpu4.l1c.demand_mshr_miss_rate::total 0.859293 # mshr miss rate for demand accesses
system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859293 # mshr miss rate for overall accesses
system.cpu4.l1c.overall_mshr_miss_rate::total 0.859293 # mshr miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 18948.056016 # average ReadReq mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 18948.056016 # average ReadReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 23454.441229 # average WriteReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 23454.441229 # average WriteReq mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20740.550071 # average overall mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20740.550071 # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20740.550071 # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20740.550071 # average overall mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 78330.750847 # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78330.750847 # average ReadReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 50264.811858 # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 50264.811858 # average overall mshr uncacheable latency
system.cpu5.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.cpu5.num_reads 99762 # number of read accesses completed
system.cpu5.num_writes 55488 # number of write accesses completed
system.cpu5.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.cpu5.l1c.tags.replacements 22372 # number of replacements
system.cpu5.l1c.tags.tagsinuse 391.676077 # Cycle average of tags in use
system.cpu5.l1c.tags.total_refs 13488 # Total number of references to valid blocks.
system.cpu5.l1c.tags.sampled_refs 22774 # Sample count of references to valid blocks.
system.cpu5.l1c.tags.avg_refs 0.592254 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-08-12 15:12:59 +02:00
system.cpu5.l1c.tags.occ_blocks::cpu5 391.676077 # Average occupied blocks per requestor
system.cpu5.l1c.tags.occ_percent::cpu5 0.764992 # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_percent::total 0.764992 # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::0 387 # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
system.cpu5.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
system.cpu5.l1c.tags.tag_accesses 338416 # Number of tag accesses
system.cpu5.l1c.tags.data_accesses 338416 # Number of data accesses
system.cpu5.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.cpu5.l1c.ReadReq_hits::cpu5 8728 # number of ReadReq hits
system.cpu5.l1c.ReadReq_hits::total 8728 # number of ReadReq hits
system.cpu5.l1c.WriteReq_hits::cpu5 1164 # number of WriteReq hits
system.cpu5.l1c.WriteReq_hits::total 1164 # number of WriteReq hits
system.cpu5.l1c.demand_hits::cpu5 9892 # number of demand (read+write) hits
system.cpu5.l1c.demand_hits::total 9892 # number of demand (read+write) hits
system.cpu5.l1c.overall_hits::cpu5 9892 # number of overall hits
system.cpu5.l1c.overall_hits::total 9892 # number of overall hits
system.cpu5.l1c.ReadReq_misses::cpu5 36506 # number of ReadReq misses
system.cpu5.l1c.ReadReq_misses::total 36506 # number of ReadReq misses
system.cpu5.l1c.WriteReq_misses::cpu5 23995 # number of WriteReq misses
system.cpu5.l1c.WriteReq_misses::total 23995 # number of WriteReq misses
system.cpu5.l1c.demand_misses::cpu5 60501 # number of demand (read+write) misses
system.cpu5.l1c.demand_misses::total 60501 # number of demand (read+write) misses
system.cpu5.l1c.overall_misses::cpu5 60501 # number of overall misses
system.cpu5.l1c.overall_misses::total 60501 # number of overall misses
system.cpu5.l1c.ReadReq_miss_latency::cpu5 721706442 # number of ReadReq miss cycles
system.cpu5.l1c.ReadReq_miss_latency::total 721706442 # number of ReadReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::cpu5 584665158 # number of WriteReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::total 584665158 # number of WriteReq miss cycles
system.cpu5.l1c.demand_miss_latency::cpu5 1306371600 # number of demand (read+write) miss cycles
system.cpu5.l1c.demand_miss_latency::total 1306371600 # number of demand (read+write) miss cycles
system.cpu5.l1c.overall_miss_latency::cpu5 1306371600 # number of overall miss cycles
system.cpu5.l1c.overall_miss_latency::total 1306371600 # number of overall miss cycles
system.cpu5.l1c.ReadReq_accesses::cpu5 45234 # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.ReadReq_accesses::total 45234 # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::cpu5 25159 # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::total 25159 # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.demand_accesses::cpu5 70393 # number of demand (read+write) accesses
system.cpu5.l1c.demand_accesses::total 70393 # number of demand (read+write) accesses
system.cpu5.l1c.overall_accesses::cpu5 70393 # number of overall (read+write) accesses
system.cpu5.l1c.overall_accesses::total 70393 # number of overall (read+write) accesses
system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.807048 # miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_miss_rate::total 0.807048 # miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953734 # miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_miss_rate::total 0.953734 # miss rate for WriteReq accesses
system.cpu5.l1c.demand_miss_rate::cpu5 0.859475 # miss rate for demand accesses
system.cpu5.l1c.demand_miss_rate::total 0.859475 # miss rate for demand accesses
system.cpu5.l1c.overall_miss_rate::cpu5 0.859475 # miss rate for overall accesses
system.cpu5.l1c.overall_miss_rate::total 0.859475 # miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 19769.529447 # average ReadReq miss latency
system.cpu5.l1c.ReadReq_avg_miss_latency::total 19769.529447 # average ReadReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 24366.124526 # average WriteReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::total 24366.124526 # average WriteReq miss latency
system.cpu5.l1c.demand_avg_miss_latency::cpu5 21592.562106 # average overall miss latency
system.cpu5.l1c.demand_avg_miss_latency::total 21592.562106 # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::cpu5 21592.562106 # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::total 21592.562106 # average overall miss latency
system.cpu5.l1c.blocked_cycles::no_mshrs 870792 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu5.l1c.blocked::no_mshrs 66903 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu5.l1c.avg_blocked_cycles::no_mshrs 13.015739 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu5.l1c.writebacks::writebacks 9839 # number of writebacks
system.cpu5.l1c.writebacks::total 9839 # number of writebacks
system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36506 # number of ReadReq MSHR misses
system.cpu5.l1c.ReadReq_mshr_misses::total 36506 # number of ReadReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23995 # number of WriteReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::total 23995 # number of WriteReq MSHR misses
system.cpu5.l1c.demand_mshr_misses::cpu5 60501 # number of demand (read+write) MSHR misses
system.cpu5.l1c.demand_mshr_misses::total 60501 # number of demand (read+write) MSHR misses
system.cpu5.l1c.overall_mshr_misses::cpu5 60501 # number of overall MSHR misses
system.cpu5.l1c.overall_mshr_misses::total 60501 # number of overall MSHR misses
system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9845 # number of ReadReq MSHR uncacheable
system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9845 # number of ReadReq MSHR uncacheable
system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5507 # number of WriteReq MSHR uncacheable
system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5507 # number of WriteReq MSHR uncacheable
system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15352 # number of overall MSHR uncacheable misses
system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15352 # number of overall MSHR uncacheable misses
system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 685200442 # number of ReadReq MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_miss_latency::total 685200442 # number of ReadReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 560672158 # number of WriteReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::total 560672158 # number of WriteReq MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1245872600 # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::total 1245872600 # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1245872600 # number of overall MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::total 1245872600 # number of overall MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 769357074 # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 769357074 # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 769357074 # number of overall MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::total 769357074 # number of overall MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.807048 # mshr miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.807048 # mshr miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953734 # mshr miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.953734 # mshr miss rate for WriteReq accesses
system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859475 # mshr miss rate for demand accesses
system.cpu5.l1c.demand_mshr_miss_rate::total 0.859475 # mshr miss rate for demand accesses
system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859475 # mshr miss rate for overall accesses
system.cpu5.l1c.overall_mshr_miss_rate::total 0.859475 # mshr miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 18769.529447 # average ReadReq mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 18769.529447 # average ReadReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 23366.207877 # average WriteReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 23366.207877 # average WriteReq mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20592.595164 # average overall mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20592.595164 # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20592.595164 # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20592.595164 # average overall mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 78146.985678 # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78146.985678 # average ReadReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 50114.452449 # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 50114.452449 # average overall mshr uncacheable latency
system.cpu6.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.cpu6.num_reads 100000 # number of read accesses completed
system.cpu6.num_writes 55102 # number of write accesses completed
system.cpu6.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.cpu6.l1c.tags.replacements 22254 # number of replacements
system.cpu6.l1c.tags.tagsinuse 391.922561 # Cycle average of tags in use
system.cpu6.l1c.tags.total_refs 13477 # Total number of references to valid blocks.
system.cpu6.l1c.tags.sampled_refs 22655 # Sample count of references to valid blocks.
system.cpu6.l1c.tags.avg_refs 0.594880 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-08-12 15:12:59 +02:00
system.cpu6.l1c.tags.occ_blocks::cpu6 391.922561 # Average occupied blocks per requestor
system.cpu6.l1c.tags.occ_percent::cpu6 0.765474 # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_percent::total 0.765474 # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::0 393 # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
system.cpu6.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id
system.cpu6.l1c.tags.tag_accesses 337953 # Number of tag accesses
system.cpu6.l1c.tags.data_accesses 337953 # Number of data accesses
system.cpu6.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.cpu6.l1c.ReadReq_hits::cpu6 8677 # number of ReadReq hits
system.cpu6.l1c.ReadReq_hits::total 8677 # number of ReadReq hits
system.cpu6.l1c.WriteReq_hits::cpu6 1226 # number of WriteReq hits
system.cpu6.l1c.WriteReq_hits::total 1226 # number of WriteReq hits
system.cpu6.l1c.demand_hits::cpu6 9903 # number of demand (read+write) hits
system.cpu6.l1c.demand_hits::total 9903 # number of demand (read+write) hits
system.cpu6.l1c.overall_hits::cpu6 9903 # number of overall hits
system.cpu6.l1c.overall_hits::total 9903 # number of overall hits
system.cpu6.l1c.ReadReq_misses::cpu6 36565 # number of ReadReq misses
system.cpu6.l1c.ReadReq_misses::total 36565 # number of ReadReq misses
system.cpu6.l1c.WriteReq_misses::cpu6 23825 # number of WriteReq misses
system.cpu6.l1c.WriteReq_misses::total 23825 # number of WriteReq misses
system.cpu6.l1c.demand_misses::cpu6 60390 # number of demand (read+write) misses
system.cpu6.l1c.demand_misses::total 60390 # number of demand (read+write) misses
system.cpu6.l1c.overall_misses::cpu6 60390 # number of overall misses
system.cpu6.l1c.overall_misses::total 60390 # number of overall misses
system.cpu6.l1c.ReadReq_miss_latency::cpu6 723690383 # number of ReadReq miss cycles
system.cpu6.l1c.ReadReq_miss_latency::total 723690383 # number of ReadReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::cpu6 577264297 # number of WriteReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::total 577264297 # number of WriteReq miss cycles
system.cpu6.l1c.demand_miss_latency::cpu6 1300954680 # number of demand (read+write) miss cycles
system.cpu6.l1c.demand_miss_latency::total 1300954680 # number of demand (read+write) miss cycles
system.cpu6.l1c.overall_miss_latency::cpu6 1300954680 # number of overall miss cycles
system.cpu6.l1c.overall_miss_latency::total 1300954680 # number of overall miss cycles
system.cpu6.l1c.ReadReq_accesses::cpu6 45242 # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.ReadReq_accesses::total 45242 # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::cpu6 25051 # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::total 25051 # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.demand_accesses::cpu6 70293 # number of demand (read+write) accesses
system.cpu6.l1c.demand_accesses::total 70293 # number of demand (read+write) accesses
system.cpu6.l1c.overall_accesses::cpu6 70293 # number of overall (read+write) accesses
system.cpu6.l1c.overall_accesses::total 70293 # number of overall (read+write) accesses
system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808209 # miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_miss_rate::total 0.808209 # miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.951060 # miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_miss_rate::total 0.951060 # miss rate for WriteReq accesses
system.cpu6.l1c.demand_miss_rate::cpu6 0.859118 # miss rate for demand accesses
system.cpu6.l1c.demand_miss_rate::total 0.859118 # miss rate for demand accesses
system.cpu6.l1c.overall_miss_rate::cpu6 0.859118 # miss rate for overall accesses
system.cpu6.l1c.overall_miss_rate::total 0.859118 # miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 19791.887953 # average ReadReq miss latency
system.cpu6.l1c.ReadReq_avg_miss_latency::total 19791.887953 # average ReadReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 24229.351396 # average WriteReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::total 24229.351396 # average WriteReq miss latency
system.cpu6.l1c.demand_avg_miss_latency::cpu6 21542.551416 # average overall miss latency
system.cpu6.l1c.demand_avg_miss_latency::total 21542.551416 # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::cpu6 21542.551416 # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::total 21542.551416 # average overall miss latency
system.cpu6.l1c.blocked_cycles::no_mshrs 870051 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu6.l1c.blocked::no_mshrs 66789 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu6.l1c.avg_blocked_cycles::no_mshrs 13.026861 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu6.l1c.writebacks::writebacks 9787 # number of writebacks
system.cpu6.l1c.writebacks::total 9787 # number of writebacks
system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36565 # number of ReadReq MSHR misses
system.cpu6.l1c.ReadReq_mshr_misses::total 36565 # number of ReadReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23825 # number of WriteReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::total 23825 # number of WriteReq MSHR misses
system.cpu6.l1c.demand_mshr_misses::cpu6 60390 # number of demand (read+write) MSHR misses
system.cpu6.l1c.demand_mshr_misses::total 60390 # number of demand (read+write) MSHR misses
system.cpu6.l1c.overall_mshr_misses::cpu6 60390 # number of overall MSHR misses
system.cpu6.l1c.overall_mshr_misses::total 60390 # number of overall MSHR misses
system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9904 # number of ReadReq MSHR uncacheable
system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9904 # number of ReadReq MSHR uncacheable
system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5506 # number of WriteReq MSHR uncacheable
system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5506 # number of WriteReq MSHR uncacheable
system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15410 # number of overall MSHR uncacheable misses
system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15410 # number of overall MSHR uncacheable misses
system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 687127383 # number of ReadReq MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_miss_latency::total 687127383 # number of ReadReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 553439297 # number of WriteReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::total 553439297 # number of WriteReq MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1240566680 # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::total 1240566680 # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1240566680 # number of overall MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::total 1240566680 # number of overall MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 773835448 # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 773835448 # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 773835448 # number of overall MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::total 773835448 # number of overall MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808209 # mshr miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808209 # mshr miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.951060 # mshr miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.951060 # mshr miss rate for WriteReq accesses
system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859118 # mshr miss rate for demand accesses
system.cpu6.l1c.demand_mshr_miss_rate::total 0.859118 # mshr miss rate for demand accesses
system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859118 # mshr miss rate for overall accesses
system.cpu6.l1c.overall_mshr_miss_rate::total 0.859118 # mshr miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 18791.942650 # average ReadReq mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 18791.942650 # average ReadReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 23229.351396 # average WriteReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 23229.351396 # average WriteReq mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20542.584534 # average overall mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20542.584534 # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20542.584534 # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20542.584534 # average overall mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 78133.627625 # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78133.627625 # average ReadReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 50216.446982 # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 50216.446982 # average overall mshr uncacheable latency
system.cpu7.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.cpu7.num_reads 99606 # number of read accesses completed
system.cpu7.num_writes 54773 # number of write accesses completed
system.cpu7.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.cpu7.l1c.tags.replacements 21949 # number of replacements
system.cpu7.l1c.tags.tagsinuse 391.189669 # Cycle average of tags in use
system.cpu7.l1c.tags.total_refs 13361 # Total number of references to valid blocks.
system.cpu7.l1c.tags.sampled_refs 22347 # Sample count of references to valid blocks.
system.cpu7.l1c.tags.avg_refs 0.597888 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-08-12 15:12:59 +02:00
system.cpu7.l1c.tags.occ_blocks::cpu7 391.189669 # Average occupied blocks per requestor
system.cpu7.l1c.tags.occ_percent::cpu7 0.764042 # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_percent::total 0.764042 # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
system.cpu7.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id
system.cpu7.l1c.tags.tag_accesses 335877 # Number of tag accesses
system.cpu7.l1c.tags.data_accesses 335877 # Number of data accesses
system.cpu7.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.cpu7.l1c.ReadReq_hits::cpu7 8692 # number of ReadReq hits
system.cpu7.l1c.ReadReq_hits::total 8692 # number of ReadReq hits
2016-04-21 10:48:24 +02:00
system.cpu7.l1c.WriteReq_hits::cpu7 1148 # number of WriteReq hits
system.cpu7.l1c.WriteReq_hits::total 1148 # number of WriteReq hits
2016-08-12 15:12:59 +02:00
system.cpu7.l1c.demand_hits::cpu7 9840 # number of demand (read+write) hits
system.cpu7.l1c.demand_hits::total 9840 # number of demand (read+write) hits
system.cpu7.l1c.overall_hits::cpu7 9840 # number of overall hits
system.cpu7.l1c.overall_hits::total 9840 # number of overall hits
system.cpu7.l1c.ReadReq_misses::cpu7 36424 # number of ReadReq misses
system.cpu7.l1c.ReadReq_misses::total 36424 # number of ReadReq misses
system.cpu7.l1c.WriteReq_misses::cpu7 23598 # number of WriteReq misses
system.cpu7.l1c.WriteReq_misses::total 23598 # number of WriteReq misses
system.cpu7.l1c.demand_misses::cpu7 60022 # number of demand (read+write) misses
system.cpu7.l1c.demand_misses::total 60022 # number of demand (read+write) misses
system.cpu7.l1c.overall_misses::cpu7 60022 # number of overall misses
system.cpu7.l1c.overall_misses::total 60022 # number of overall misses
system.cpu7.l1c.ReadReq_miss_latency::cpu7 721113865 # number of ReadReq miss cycles
system.cpu7.l1c.ReadReq_miss_latency::total 721113865 # number of ReadReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::cpu7 575330708 # number of WriteReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::total 575330708 # number of WriteReq miss cycles
system.cpu7.l1c.demand_miss_latency::cpu7 1296444573 # number of demand (read+write) miss cycles
system.cpu7.l1c.demand_miss_latency::total 1296444573 # number of demand (read+write) miss cycles
system.cpu7.l1c.overall_miss_latency::cpu7 1296444573 # number of overall miss cycles
system.cpu7.l1c.overall_miss_latency::total 1296444573 # number of overall miss cycles
system.cpu7.l1c.ReadReq_accesses::cpu7 45116 # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.ReadReq_accesses::total 45116 # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::cpu7 24746 # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::total 24746 # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.demand_accesses::cpu7 69862 # number of demand (read+write) accesses
system.cpu7.l1c.demand_accesses::total 69862 # number of demand (read+write) accesses
system.cpu7.l1c.overall_accesses::cpu7 69862 # number of overall (read+write) accesses
system.cpu7.l1c.overall_accesses::total 69862 # number of overall (read+write) accesses
system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807341 # miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_miss_rate::total 0.807341 # miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953609 # miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_miss_rate::total 0.953609 # miss rate for WriteReq accesses
system.cpu7.l1c.demand_miss_rate::cpu7 0.859151 # miss rate for demand accesses
system.cpu7.l1c.demand_miss_rate::total 0.859151 # miss rate for demand accesses
system.cpu7.l1c.overall_miss_rate::cpu7 0.859151 # miss rate for overall accesses
system.cpu7.l1c.overall_miss_rate::total 0.859151 # miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 19797.766994 # average ReadReq miss latency
system.cpu7.l1c.ReadReq_avg_miss_latency::total 19797.766994 # average ReadReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 24380.485973 # average WriteReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::total 24380.485973 # average WriteReq miss latency
system.cpu7.l1c.demand_avg_miss_latency::cpu7 21599.489737 # average overall miss latency
system.cpu7.l1c.demand_avg_miss_latency::total 21599.489737 # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::cpu7 21599.489737 # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::total 21599.489737 # average overall miss latency
system.cpu7.l1c.blocked_cycles::no_mshrs 871786 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu7.l1c.blocked::no_mshrs 66469 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu7.l1c.avg_blocked_cycles::no_mshrs 13.115678 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu7.l1c.writebacks::writebacks 9508 # number of writebacks
system.cpu7.l1c.writebacks::total 9508 # number of writebacks
system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36424 # number of ReadReq MSHR misses
system.cpu7.l1c.ReadReq_mshr_misses::total 36424 # number of ReadReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23598 # number of WriteReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::total 23598 # number of WriteReq MSHR misses
system.cpu7.l1c.demand_mshr_misses::cpu7 60022 # number of demand (read+write) MSHR misses
system.cpu7.l1c.demand_mshr_misses::total 60022 # number of demand (read+write) MSHR misses
system.cpu7.l1c.overall_mshr_misses::cpu7 60022 # number of overall MSHR misses
system.cpu7.l1c.overall_mshr_misses::total 60022 # number of overall MSHR misses
system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9972 # number of ReadReq MSHR uncacheable
system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9972 # number of ReadReq MSHR uncacheable
system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5689 # number of WriteReq MSHR uncacheable
system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5689 # number of WriteReq MSHR uncacheable
system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15661 # number of overall MSHR uncacheable misses
system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15661 # number of overall MSHR uncacheable misses
system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 684690865 # number of ReadReq MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_miss_latency::total 684690865 # number of ReadReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 551733708 # number of WriteReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::total 551733708 # number of WriteReq MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1236424573 # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::total 1236424573 # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1236424573 # number of overall MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::total 1236424573 # number of overall MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 778989868 # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 778989868 # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 778989868 # number of overall MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::total 778989868 # number of overall MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807341 # mshr miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807341 # mshr miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953609 # mshr miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953609 # mshr miss rate for WriteReq accesses
system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859151 # mshr miss rate for demand accesses
system.cpu7.l1c.demand_mshr_miss_rate::total 0.859151 # mshr miss rate for demand accesses
system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859151 # mshr miss rate for overall accesses
system.cpu7.l1c.overall_mshr_miss_rate::total 0.859151 # mshr miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 18797.794449 # average ReadReq mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 18797.794449 # average ReadReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 23380.528350 # average WriteReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 23380.528350 # average WriteReq mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20599.523058 # average overall mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20599.523058 # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20599.523058 # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20599.523058 # average overall mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 78117.716406 # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78117.716406 # average ReadReq mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 49740.748867 # average overall mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 49740.748867 # average overall mshr uncacheable latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 91944 # number of replacements
system.l2c.tags.tagsinuse 1018.135199 # Cycle average of tags in use
system.l2c.tags.total_refs 150035 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 92968 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 1.613835 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 8704000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 700.601873 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0 40.249147 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1 40.174988 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2 39.327766 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3 40.057426 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu4 39.781379 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu5 39.374996 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu6 39.797467 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu7 38.770159 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.684182 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0 0.039306 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1 0.039233 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2 0.038406 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3 0.039119 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu4 0.038849 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu5 0.038452 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu6 0.038865 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu7 0.037861 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.994273 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 1024 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 947 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 2139200 # Number of tag accesses
system.l2c.tags.data_accesses 2139200 # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 77024 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 77024 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0 414 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1 433 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2 398 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3 417 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu4 426 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu5 450 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu6 421 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu7 435 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 3394 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0 1862 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1 1934 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2 1949 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3 1865 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu4 1828 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu5 1873 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu6 1869 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu7 1854 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 15034 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0 9356 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1 9333 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2 9371 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3 9291 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu4 9201 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu5 9292 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu6 9177 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu7 9226 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 74247 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0 11218 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1 11267 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2 11320 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3 11156 # number of demand (read+write) hits
system.l2c.demand_hits::cpu4 11029 # number of demand (read+write) hits
system.l2c.demand_hits::cpu5 11165 # number of demand (read+write) hits
system.l2c.demand_hits::cpu6 11046 # number of demand (read+write) hits
system.l2c.demand_hits::cpu7 11080 # number of demand (read+write) hits
system.l2c.demand_hits::total 89281 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0 11218 # number of overall hits
system.l2c.overall_hits::cpu1 11267 # number of overall hits
system.l2c.overall_hits::cpu2 11320 # number of overall hits
system.l2c.overall_hits::cpu3 11156 # number of overall hits
system.l2c.overall_hits::cpu4 11029 # number of overall hits
system.l2c.overall_hits::cpu5 11165 # number of overall hits
system.l2c.overall_hits::cpu6 11046 # number of overall hits
system.l2c.overall_hits::cpu7 11080 # number of overall hits
system.l2c.overall_hits::total 89281 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0 1872 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1 1844 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2 1947 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3 1836 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu4 1852 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu5 1900 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu6 1862 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu7 1851 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 14964 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0 4900 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1 4669 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2 4784 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3 4718 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu4 4791 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu5 4701 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu6 4630 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu7 4626 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 37819 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0 2463 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1 2553 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2 2469 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3 2512 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu4 2543 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu5 2510 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu6 2544 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu7 2476 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 20070 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0 7363 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1 7222 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2 7253 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3 7230 # number of demand (read+write) misses
system.l2c.demand_misses::cpu4 7334 # number of demand (read+write) misses
system.l2c.demand_misses::cpu5 7211 # number of demand (read+write) misses
system.l2c.demand_misses::cpu6 7174 # number of demand (read+write) misses
system.l2c.demand_misses::cpu7 7102 # number of demand (read+write) misses
system.l2c.demand_misses::total 57889 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0 7363 # number of overall misses
system.l2c.overall_misses::cpu1 7222 # number of overall misses
system.l2c.overall_misses::cpu2 7253 # number of overall misses
system.l2c.overall_misses::cpu3 7230 # number of overall misses
system.l2c.overall_misses::cpu4 7334 # number of overall misses
system.l2c.overall_misses::cpu5 7211 # number of overall misses
system.l2c.overall_misses::cpu6 7174 # number of overall misses
system.l2c.overall_misses::cpu7 7102 # number of overall misses
system.l2c.overall_misses::total 57889 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0 31234104 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1 31358138 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2 32572788 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3 30120451 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu4 30799263 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu5 31792446 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu6 30352791 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu7 30383968 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 248613949 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0 215803873 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1 203805632 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2 208081416 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3 204329473 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu4 209030536 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu5 205216215 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu6 201405883 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu7 201887028 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 1649560056 # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0 169116609 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1 174843463 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2 170153096 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3 173149203 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu4 175448063 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu5 172961782 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu6 175284714 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu7 170387602 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 1381344532 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0 384920482 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1 378649095 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2 378234512 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3 377478676 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu4 384478599 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu5 378177997 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu6 376690597 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu7 372274630 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 3030904588 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0 384920482 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1 378649095 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2 378234512 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3 377478676 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu4 384478599 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu5 378177997 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu6 376690597 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu7 372274630 # number of overall miss cycles
system.l2c.overall_miss_latency::total 3030904588 # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks 77024 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 77024 # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0 2286 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1 2277 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2 2345 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3 2253 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu4 2278 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu5 2350 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu6 2283 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu7 2286 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 18358 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0 6762 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1 6603 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2 6733 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3 6583 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu4 6619 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu5 6574 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu6 6499 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu7 6480 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 52853 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0 11819 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1 11886 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2 11840 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3 11803 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu4 11744 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu5 11802 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu6 11721 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu7 11702 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 94317 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0 18581 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1 18489 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2 18573 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3 18386 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu4 18363 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu5 18376 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu6 18220 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu7 18182 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 147170 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0 18581 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1 18489 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2 18573 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3 18386 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu4 18363 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu5 18376 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu6 18220 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu7 18182 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 147170 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0 0.818898 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1 0.809838 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2 0.830277 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3 0.814913 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu4 0.812994 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu5 0.808511 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu6 0.815594 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu7 0.809711 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.815121 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0 0.724638 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1 0.707103 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2 0.710530 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3 0.716695 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu4 0.723825 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu5 0.715090 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu6 0.712417 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu7 0.713889 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.715551 # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0 0.208393 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1 0.214791 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2 0.208530 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3 0.212827 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu4 0.216536 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu5 0.212676 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu6 0.217046 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu7 0.211588 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.212793 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0 0.396265 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1 0.390611 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2 0.390513 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3 0.393234 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu4 0.399390 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu5 0.392414 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu6 0.393743 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu7 0.390606 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.393348 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0 0.396265 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1 0.390611 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2 0.390513 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3 0.393234 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu4 0.399390 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu5 0.392414 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu6 0.393743 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu7 0.390606 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.393348 # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0 16684.884615 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1 17005.497831 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2 16729.731895 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3 16405.474401 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu4 16630.271598 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu5 16732.866316 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu6 16301.176692 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu7 16414.893571 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 16614.137196 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0 44041.606735 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1 43650.810024 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2 43495.279264 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3 43308.493641 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu4 43629.834273 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu5 43653.736439 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu6 43500.190713 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu7 43641.813230 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 43617.230916 # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0 68662.853837 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1 68485.492754 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2 68915.794249 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3 68928.822850 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu4 68992.553284 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu5 68909.076494 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu6 68901.224057 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu7 68815.671244 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 68826.334429 # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0 52277.669700 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1 52429.949460 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2 52148.698745 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3 52210.052006 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu4 52424.134033 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu5 52444.598114 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu6 52507.749791 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu7 52418.280766 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52357.176458 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0 52277.669700 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1 52429.949460 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2 52148.698745 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3 52210.052006 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu4 52424.134033 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu5 52444.598114 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu6 52507.749791 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu7 52418.280766 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52357.176458 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 46726 # number of cycles access was blocked
2015-02-11 16:23:31 +01:00
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.l2c.blocked::no_mshrs 7668 # number of cycles access was blocked
2015-02-11 16:23:31 +01:00
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.l2c.avg_blocked_cycles::no_mshrs 6.093636 # average number of cycles each access was blocked
2015-02-11 16:23:31 +01:00
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.l2c.writebacks::writebacks 22726 # number of writebacks
system.l2c.writebacks::total 22726 # number of writebacks
system.l2c.UpgradeReq_mshr_hits::cpu0 3 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu1 4 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu2 2 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu3 3 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu4 5 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits
2016-04-21 10:48:24 +02:00
system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits
2016-08-12 15:12:59 +02:00
system.l2c.UpgradeReq_mshr_hits::cpu7 5 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::total 25 # number of UpgradeReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu0 20 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu1 17 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu2 18 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu3 21 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu4 18 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu5 25 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu6 26 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu7 21 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::total 166 # number of ReadExReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0 33 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1 30 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu2 30 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu3 27 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu4 34 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu5 37 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu6 35 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu7 41 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total 267 # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0 53 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1 47 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2 48 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3 48 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu4 52 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu5 62 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu6 61 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu7 62 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 433 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0 53 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1 47 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2 48 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3 48 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu4 52 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu5 62 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu6 61 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu7 62 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 433 # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks 4900 # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total 4900 # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0 1869 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1 1840 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2 1945 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3 1833 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu4 1847 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu5 1898 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu6 1861 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu7 1846 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 14939 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0 4880 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1 4652 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2 4766 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3 4697 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu4 4773 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu5 4676 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu6 4604 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu7 4605 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 37653 # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0 2430 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1 2523 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2 2439 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3 2485 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu4 2509 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu5 2473 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu6 2509 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu7 2435 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 19803 # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0 7310 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1 7175 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2 7205 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3 7182 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu4 7282 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu5 7149 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu6 7113 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu7 7040 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 57456 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0 7310 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1 7175 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2 7205 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3 7182 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu4 7282 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu5 7149 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu6 7113 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu7 7040 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 57456 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0 9863 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1 9872 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2 9852 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu3 9823 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu4 9741 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu5 9844 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu6 9904 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu7 9971 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 78870 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0 5413 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1 5469 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2 5498 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu3 5381 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu4 5438 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu5 5504 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu6 5505 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu7 5689 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 43897 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0 15276 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1 15341 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2 15350 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu3 15204 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu4 15179 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu5 15348 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu6 15409 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu7 15660 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 122767 # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0 42798637 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1 41900379 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2 44540803 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3 41317767 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu4 42296498 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu5 43188221 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu6 42540949 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu7 41448863 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 340032117 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0 166179988 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1 156537743 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2 159697945 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3 156613177 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu4 160372266 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu5 157473921 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu6 154279145 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu7 154804178 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 1265958363 # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 143336439 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 148034574 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 144250348 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 146721083 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 148442317 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 146274036 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 148395292 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 144143903 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 1169597992 # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0 309516427 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1 304572317 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2 303948293 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3 303334260 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu4 308814583 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu5 303747957 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu6 302674437 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu7 298948081 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 2435556355 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0 309516427 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1 304572317 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2 303948293 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3 303334260 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu4 308814583 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu5 303747957 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu6 302674437 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu7 298948081 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 2435556355 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 558924481 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 559228006 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 558782791 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 556927201 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 552042138 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 557542912 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 561245949 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 564245669 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 4468939147 # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0 558924481 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1 559228006 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2 558782791 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3 556927201 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu4 552042138 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu5 557542912 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu6 561245949 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu7 564245669 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 4468939147 # number of overall MSHR uncacheable cycles
2015-07-03 16:15:03 +02:00
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2016-08-12 15:12:59 +02:00
system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.817585 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.808081 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.829424 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.813582 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.810799 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.807660 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.815155 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.807524 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.813760 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.721680 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.704528 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.707857 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.713504 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.721106 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.711287 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.708417 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.710648 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.712410 # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.205601 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.212267 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.205997 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.210540 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.213641 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.209541 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.214060 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.208084 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.209962 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0 0.393413 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1 0.388069 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2 0.387929 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3 0.390623 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu4 0.396558 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu5 0.389040 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu6 0.390395 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu7 0.387196 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.390406 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0 0.393413 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1 0.388069 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2 0.387929 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3 0.390623 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu4 0.396558 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu5 0.389040 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu6 0.390395 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu7 0.387196 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.390406 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 22899.217228 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 22771.945109 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 22900.155784 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 22541.062193 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 22900.107201 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 22754.594837 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 22859.188071 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 22453.338570 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22761.370708 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 34053.276230 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 33649.557825 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 33507.751783 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 33343.235469 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 33599.888121 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 33677.057528 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 33509.805604 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 33616.542454 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 33621.713091 # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 58986.188889 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 58674.028537 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59143.234112 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 59042.689336 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 59163.936628 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 59148.417307 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 59145.194101 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 59196.674743 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 59061.656921 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0 42341.508482 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1 42449.103415 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2 42185.745038 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3 42235.346700 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu4 42407.935045 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu5 42488.174150 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu6 42552.289751 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu7 42464.216051 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 42389.939345 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0 42341.508482 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1 42449.103415 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2 42185.745038 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3 42235.346700 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu4 42407.935045 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu5 42488.174150 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu6 42552.289751 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu7 42464.216051 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 42389.939345 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 56668.810808 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 56647.893639 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 56717.701076 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 56696.243612 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 56672.019095 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 56637.841528 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 56668.613590 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 56588.674055 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 56662.091378 # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 36588.405407 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 36453.165113 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 36402.787687 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 36630.307880 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 36368.808090 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 36326.746938 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 36423.255825 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 36031.013346 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 36401.794839 # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests 165129 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 149421 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 78866 # Transaction distribution
system.membus.trans_dist::ReadResp 98603 # Transaction distribution
system.membus.trans_dist::WriteReq 43891 # Transaction distribution
system.membus.trans_dist::WriteResp 43890 # Transaction distribution
system.membus.trans_dist::WritebackDirty 22725 # Transaction distribution
system.membus.trans_dist::CleanEvict 5096 # Transaction distribution
system.membus.trans_dist::UpgradeReq 51962 # Transaction distribution
system.membus.trans_dist::ReadExReq 56321 # Transaction distribution
system.membus.trans_dist::ReadExResp 11265 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 19745 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 432364 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 432364 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 3561537 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 3561537 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 55548 # Total snoops (count)
2016-07-21 18:19:18 +02:00
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
2016-08-12 15:12:59 +02:00
system.membus.snoop_fanout::samples 277065 # Request fanout histogram
2015-02-11 16:23:31 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.membus.snoop_fanout::0 277065 100.00% 100.00% # Request fanout histogram
2015-02-11 16:23:31 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.membus.snoop_fanout::total 277065 # Request fanout histogram
system.membus.reqLayer0.occupancy 406206026 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 77.9 # Layer utilization (%)
system.membus.respLayer0.occupancy 356644000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 68.4 # Layer utilization (%)
system.toL2Bus.snoop_filter.tot_requests 666785 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 283960 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 335937 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 86136 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 43107 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 43029 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 78870 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 370375 # Transaction distribution
system.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 43897 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 43890 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 99750 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 167866 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 28850 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 28850 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 162383 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 162380 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 291522 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133688 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 134001 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 133796 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133576 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 133426 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133904 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133634 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 133439 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 1069464 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1829226 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1815722 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1817716 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1809443 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1812235 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1808884 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1798064 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1779371 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 14470661 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 409171 # Total snoops (count)
system.toL2Bus.snoopTraffic 21085504 # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples 706797 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.196447 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.990756 # Request fanout histogram
2015-02-11 16:23:31 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.toL2Bus.snoop_fanout::0 181481 25.68% 25.68% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 294628 41.68% 67.36% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 158602 22.44% 89.80% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 56776 8.03% 97.83% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 13243 1.87% 99.71% # Request fanout histogram
system.toL2Bus.snoop_fanout::5 1898 0.27% 99.98% # Request fanout histogram
system.toL2Bus.snoop_fanout::6 160 0.02% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::7 9 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
2015-02-11 16:23:31 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.toL2Bus.snoop_fanout::total 706797 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 500161714 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 95.9 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 102256739 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 19.6 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 102545160 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 19.7 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 102125332 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 19.6 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 102285646 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 19.6 # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy 102013056 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 19.6 # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy 102427641 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 19.6 # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy 102433420 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 19.6 # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy 101994041 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 19.6 # Layer utilization (%)
2007-02-07 06:16:33 +01:00
---------- End Simulation Statistics ----------
