sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
gem5/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt

633 lines
72 KiB
Text
Raw Normal View History

X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
---------- Begin Simulation Statistics ----------
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
sim_seconds 0.609798 # Number of seconds simulated
sim_ticks 609797568500 # Number of ticks simulated
final_tick 609797568500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
host_inst_rate 67150 # Simulator instruction rate (inst/s)
host_op_rate 123728 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 46530668 # Simulator tick rate (ticks/s)
host_mem_usage 230840 # Number of bytes of host memory used
host_seconds 13105.28 # Real time elapsed on the host
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
sim_insts 880025277 # Number of instructions simulated
sim_ops 1621493925 # Number of ops (including micro ops) simulated
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.physmem.bytes_read::cpu.inst 58112 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1694784 # Number of bytes read from this memory
system.physmem.bytes_read::total 1752896 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 58112 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 58112 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 162816 # Number of bytes written to this memory
system.physmem.bytes_written::total 162816 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 908 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 26481 # Number of read requests responded to by this memory
system.physmem.num_reads::total 27389 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 2544 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2544 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 95297 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2779257 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2874554 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 95297 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 95297 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 267000 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 267000 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 267000 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 95297 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2779257 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3141554 # Total bandwidth to/from this memory (bytes/s)
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.workload.num_syscalls 48 # Number of system calls
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.numCycles 1219595138 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.BPredUnit.lookups 153419281 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 153419281 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 26709105 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 75190754 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 74807048 # Number of BTB hits
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.fetch.icacheStallCycles 180231048 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1488409356 # Number of instructions fetch has processed
system.cpu.fetch.Branches 153419281 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 74807048 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 400557825 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 92407802 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 573234633 # Number of cycles fetch has spent blocked
x86 Regressions: Update stats due to register predication
2012-09-11 16:34:40 +02:00
system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 185924931 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 9228337 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1219569114 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.084484 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.278873 # Number of instructions fetched each cycle (Total)
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.fetch.rateDist::0 826230375 67.75% 67.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 23815932 1.95% 69.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 15671088 1.28% 70.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 17469051 1.43% 72.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 26718016 2.19% 74.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 18180169 1.49% 76.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 27807273 2.28% 78.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 39426907 3.23% 81.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 224250303 18.39% 100.00% # Number of instructions fetched each cycle (Total)
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.fetch.rateDist::total 1219569114 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.125795 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.220413 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 289356881 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 496684656 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 275171365 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 92810894 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 65545318 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 2357736314 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 65545318 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 337721602 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 122595128 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 1576 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 305744833 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 387960657 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2261287899 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 242284686 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 120945759 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2627574208 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 5773835618 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 5773831438 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4180 # Number of floating rename lookups
x86 Regressions: Update stats due to register predication
2012-09-11 16:34:40 +02:00
system.cpu.rename.CommittedMaps 1886895257 # Number of HB maps that are committed
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.rename.UndoneMaps 740678951 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 84 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 84 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 730447231 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 543232760 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 220439884 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 349480208 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 144920713 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2014741693 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 481 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1784164311 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 260366 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 392823529 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 821144040 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 431 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1219569114 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.462946 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.418593 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.iq.issued_per_cycle::0 363999611 29.85% 29.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 365670586 29.98% 59.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 234855592 19.26% 79.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 140866108 11.55% 90.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 60913141 4.99% 95.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 40023537 3.28% 98.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 10789680 0.88% 99.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 1930984 0.16% 99.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 519875 0.04% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.iq.issued_per_cycle::total 1219569114 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.iq.fu_full::IntAlu 467350 16.09% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.09% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2184649 75.23% 91.33% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 251796 8.67% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.iq.FU_type_0::No_OpClass 46816435 2.62% 2.62% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1065676196 59.73% 62.35% # Type of FU issued
x86 Regressions: Update stats due to register predication
2012-09-11 16:34:40 +02:00
system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.35% # Type of FU issued
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.iq.FU_type_0::MemRead 478957046 26.84% 89.20% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 192714634 10.80% 100.00% # Type of FU issued
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.iq.FU_type_0::total 1784164311 # Type of FU issued
system.cpu.iq.rate 1.462915 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2903795 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.001628 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4791061390 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2407739950 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1725073479 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 507 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 1436 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 104 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1740251451 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 220 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 209520869 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 124190639 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 36910 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 180735 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 32253827 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 2057 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.iew.iewSquashCycles 65545318 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 120938 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 15130 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2014742174 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 63913352 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 543232760 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 220439884 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 78 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 7621 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 7 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 180735 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 2120344 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 24738064 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 26858408 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1766248435 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 474148133 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 17915876 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.iew.exec_refs 665987460 # number of memory reference insts executed
system.cpu.iew.exec_branches 110190116 # Number of branches executed
system.cpu.iew.exec_stores 191839327 # Number of stores executed
system.cpu.iew.exec_rate 1.448225 # Inst execution rate
system.cpu.iew.wb_sent 1726426595 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1725073583 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1267591282 # num instructions producing a value
system.cpu.iew.wb_consumers 1828482722 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.iew.wb_rate 1.414464 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.693248 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.commit.commitSquashedInsts 393250539 # The number of squashed insts skipped by commit
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.commit.branchMispredicts 26709142 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1154023796 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.405078 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.832959 # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.commit.committed_per_cycle::0 421087806 36.49% 36.49% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 412894237 35.78% 72.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 87424698 7.58% 79.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 122293813 10.60% 90.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 24525346 2.13% 92.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 22502511 1.95% 94.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 19027826 1.65% 96.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 12052514 1.04% 97.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 32215045 2.79% 100.00% # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.commit.committed_per_cycle::total 1154023796 # Number of insts commited each cycle
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.committedInsts 880025277 # Number of instructions committed
system.cpu.commit.committedOps 1621493925 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.refs 607228178 # Number of memory references committed
system.cpu.commit.loads 419042121 # Number of loads committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.membars 0 # Number of memory barriers committed
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.branches 107161574 # Number of branches committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.int_insts 1621354435 # Number of committed integer instructions.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.function_calls 0 # Number of function calls committed.
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.commit.bw_lim_events 32215045 # number cycles where commit BW limit reached
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.rob.rob_reads 3136553215 # The number of ROB reads
system.cpu.rob.rob_writes 4095072141 # The number of ROB writes
system.cpu.timesIdled 539 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 26024 # Total number of cycles that the CPU has spent unscheduled due to idling
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts 880025277 # Number of Instructions Simulated
system.cpu.committedOps 1621493925 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.cpi 1.385864 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.385864 # CPI: Total CPI of All Threads
system.cpu.ipc 0.721572 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.721572 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3541346034 # number of integer regfile reads
system.cpu.int_regfile_writes 1975100349 # number of integer regfile writes
system.cpu.fp_regfile_reads 104 # number of floating regfile reads
system.cpu.misc_regfile_reads 910400266 # number of misc regfile reads
system.cpu.icache.replacements 21 # number of replacements
system.cpu.icache.tagsinuse 820.177123 # Cycle average of tags in use
system.cpu.icache.total_refs 185923597 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 919 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 202310.769314 # Average number of references to valid blocks.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.icache.occ_blocks::cpu.inst 820.177123 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.400477 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.400477 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 185923597 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 185923597 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 185923597 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 185923597 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 185923597 # number of overall hits
system.cpu.icache.overall_hits::total 185923597 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1334 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1334 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1334 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1334 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1334 # number of overall misses
system.cpu.icache.overall_misses::total 1334 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 44859000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 44859000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 44859000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 44859000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 44859000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 44859000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 185924931 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 185924931 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 185924931 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 185924931 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 185924931 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 185924931 # number of overall (read+write) accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33627.436282 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 33627.436282 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 33627.436282 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 33627.436282 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 33627.436282 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 33627.436282 # average overall miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 415 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 415 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 415 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 415 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 415 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 415 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 919 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 919 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 919 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 919 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 919 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 919 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33142500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 33142500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33142500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 33142500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33142500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 33142500 # number of overall MSHR miss cycles
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36063.656148 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36063.656148 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36063.656148 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 36063.656148 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36063.656148 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 36063.656148 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.replacements 445640 # number of replacements
system.cpu.dcache.tagsinuse 4093.409130 # Cycle average of tags in use
system.cpu.dcache.total_refs 452355828 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 449736 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 1005.825257 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 723009000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4093.409130 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999367 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999367 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 264416053 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 264416053 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 187939775 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 187939775 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 452355828 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 452355828 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 452355828 # number of overall hits
system.cpu.dcache.overall_hits::total 452355828 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 208185 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 208185 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 246282 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 246282 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 454467 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 454467 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 454467 # number of overall misses
system.cpu.dcache.overall_misses::total 454467 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 988643000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 988643000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1714858500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1714858500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 2703501500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 2703501500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 2703501500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 2703501500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 264624238 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 264624238 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses)
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.demand_accesses::cpu.data 452810295 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 452810295 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 452810295 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 452810295 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000787 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000787 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001309 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001309 # miss rate for WriteReq accesses
x86 Regressions: Update stats due to register predication
2012-09-11 16:34:40 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.001004 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.001004 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.001004 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.001004 # miss rate for overall accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 4748.867594 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 4748.867594 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 6962.987551 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 6962.987551 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 5948.730051 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 5948.730051 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 5948.730051 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 5948.730051 # average overall miss latency
X86 Regressions: Update stats due to introduction of TSO
2012-01-29 02:09:17 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.writebacks::writebacks 428671 # number of writebacks
system.cpu.dcache.writebacks::total 428671 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4720 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 4720 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 9 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 4729 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 4729 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 4729 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 4729 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203465 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 203465 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246273 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 246273 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 449738 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 449738 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 449738 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 449738 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 561387500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 561387500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1222169500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1222169500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1783557000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 1783557000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1783557000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 1783557000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000769 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000769 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001309 # mshr miss rate for WriteReq accesses
x86 Regressions: Update stats due to register predication
2012-09-11 16:34:40 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000993 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000993 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000993 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000993 # mshr miss rate for overall accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2759.135478 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2759.135478 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 4962.661355 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 4962.661355 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3965.768959 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 3965.768959 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3965.768959 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 3965.768959 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.replacements 2661 # number of replacements
system.cpu.l2cache.tagsinuse 22190.588854 # Cycle average of tags in use
system.cpu.l2cache.total_refs 517940 # Total number of references to valid blocks.
x86 Regressions: Update stats due to register predication
2012-09-11 16:34:40 +02:00
system.cpu.l2cache.sampled_refs 24220 # Sample count of references to valid blocks.
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.avg_refs 21.384806 # Average number of references to valid blocks.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.occ_blocks::writebacks 20788.599128 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 725.869471 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 676.120254 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.634418 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.022152 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.020634 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.677203 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 11 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 198908 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 198919 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 428671 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 428671 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 224349 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 224349 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 11 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 423257 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 423268 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 11 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 423257 # number of overall hits
system.cpu.l2cache.overall_hits::total 423268 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 908 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 4552 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 5460 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 21929 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 21929 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 908 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 26481 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 27389 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 908 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 26481 # number of overall misses
system.cpu.l2cache.overall_misses::total 27389 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32192500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 157441500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 189634000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 751374000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 751374000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 32192500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 908815500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 941008000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 32192500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 908815500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 941008000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 919 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 203460 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 204379 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 428671 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 428671 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 246278 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 246278 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 919 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 449738 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 450657 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 919 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 449738 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 450657 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.988030 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022373 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.026715 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089042 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.089042 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.988030 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.058881 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.060776 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.988030 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.058881 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.060776 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35454.295154 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34587.324253 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34731.501832 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34263.942724 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34263.942724 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35454.295154 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34319.530984 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34357.150681 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35454.295154 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34319.530984 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34357.150681 # average overall miss latency
X86 Regressions: Update stats due to introduction of TSO
2012-01-29 02:09:17 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
X86 Regressions: Update stats due to introduction of TSO
2012-01-29 02:09:17 +01:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.writebacks::writebacks 2544 # number of writebacks
system.cpu.l2cache.writebacks::total 2544 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 908 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4552 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 5460 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21929 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 21929 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 908 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 26481 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 27389 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 908 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 26481 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 27389 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29285500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 141665500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 170951000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 682609000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 682609000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29285500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 824274500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 853560000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29285500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 824274500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 853560000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.988030 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022373 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026715 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089042 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089042 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.988030 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058881 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.060776 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.988030 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058881 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.060776 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32252.753304 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31121.594903 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31309.706960 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31128.140818 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31128.140818 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32252.753304 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31127.015596 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31164.336047 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32252.753304 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31127.015596 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31164.336047 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink