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gem5/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt

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X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
---------- Begin Simulation Statistics ----------
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
sim_seconds 0.636964 # Number of seconds simulated
sim_ticks 636963896500 # Number of ticks simulated
final_tick 636963896500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
host_inst_rate 94339 # Simulator instruction rate (inst/s)
host_op_rate 173825 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 68282764 # Simulator tick rate (ticks/s)
host_mem_usage 230548 # Number of bytes of host memory used
host_seconds 9328.33 # Real time elapsed on the host
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
sim_insts 880025312 # Number of instructions simulated
sim_ops 1621493982 # Number of ops (including micro ops) simulated
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.physmem.bytes_read::cpu.inst 59072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1694720 # Number of bytes read from this memory
system.physmem.bytes_read::total 1753792 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 59072 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 59072 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 162752 # Number of bytes written to this memory
system.physmem.bytes_written::total 162752 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 923 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 26480 # Number of read requests responded to by this memory
system.physmem.num_reads::total 27403 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 2543 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2543 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 92740 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2660622 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2753362 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 92740 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 92740 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 255512 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 255512 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 255512 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 92740 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2660622 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3008874 # Total bandwidth to/from this memory (bytes/s)
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.workload.num_syscalls 48 # Number of system calls
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.numCycles 1273927794 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.BPredUnit.lookups 155476696 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 155476696 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 26665974 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 76215157 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 75849392 # Number of BTB hits
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.fetch.icacheStallCycles 180766435 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1491872316 # Number of instructions fetch has processed
system.cpu.fetch.Branches 155476696 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 75849392 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 402325403 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 93614087 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 624018674 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1031 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 185889439 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 8548075 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1273900868 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.002953 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.238276 # Number of instructions fetched each cycle (Total)
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.fetch.rateDist::0 878792706 68.98% 68.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 24409433 1.92% 70.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 14960209 1.17% 72.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 18025508 1.41% 73.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 26731742 2.10% 75.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 18277101 1.43% 77.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 28493019 2.24% 79.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 39802935 3.12% 82.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 224408215 17.62% 100.00% # Number of instructions fetched each cycle (Total)
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.fetch.rateDist::total 1273900868 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.122045 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.171081 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 300130332 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 537055352 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 281851498 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 88074501 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 66789185 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 2370363864 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 66789185 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 352614235 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 124117956 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 1807 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 302560946 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 427816739 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2274265358 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 293377579 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 103041568 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 112 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 3464406080 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 7122244281 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 7122237233 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 7048 # Number of floating rename lookups
X86 Regression: update stats due to cc register split
2012-05-22 18:38:04 +02:00
system.cpu.rename.CommittedMaps 2493860970 # Number of HB maps that are committed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.rename.UndoneMaps 970545110 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 88 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 88 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 745535849 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 545979333 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 222242756 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 352158228 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 146951837 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2027253751 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 556 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1785885865 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 143298 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 405620982 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1049961378 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 506 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1273900868 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.401903 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.311945 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iq.issued_per_cycle::0 346798223 27.22% 27.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 447596849 35.14% 62.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 243149127 19.09% 81.45% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 151409869 11.89% 93.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 40759247 3.20% 96.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 32504128 2.55% 99.08% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 9931846 0.78% 99.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 1400181 0.11% 99.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 351398 0.03% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iq.issued_per_cycle::total 1273900868 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iq.fu_full::IntAlu 262837 10.20% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.20% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2136217 82.89% 93.09% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 178017 6.91% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iq.FU_type_0::No_OpClass 46812745 2.62% 2.62% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1067077874 59.75% 62.37% # Type of FU issued
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iq.FU_type_0::MemRead 479524386 26.85% 89.22% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 192470860 10.78% 100.00% # Type of FU issued
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iq.FU_type_0::total 1785885865 # Type of FU issued
system.cpu.iq.rate 1.401874 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2577071 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.001443 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4848392282 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2433055974 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1727031567 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 685 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2066 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 68 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1741649976 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 215 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 208887212 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 126937208 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 36775 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 189921 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 34056699 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 2072 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 462 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iew.iewSquashCycles 66789185 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 397482 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 85620 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2027254307 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 63893728 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 545979333 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 222242756 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 83 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 48032 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 669 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 189921 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 2137684 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 24653436 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 26791120 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1767797184 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 473889834 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 18088681 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iew.exec_refs 665730625 # number of memory reference insts executed
system.cpu.iew.exec_branches 109718993 # Number of branches executed
system.cpu.iew.exec_stores 191840791 # Number of stores executed
system.cpu.iew.exec_rate 1.387675 # Inst execution rate
system.cpu.iew.wb_sent 1728379028 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1727031635 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1262282896 # num instructions producing a value
system.cpu.iew.wb_consumers 2985352291 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iew.wb_rate 1.355675 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.422825 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.commit.commitCommittedInsts 880025312 # The number of committed instructions
system.cpu.commit.commitCommittedOps 1621493982 # The number of committed instructions
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.commit.commitSquashedInsts 405765098 # The number of squashed insts skipped by commit
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.commit.branchMispredicts 26666115 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1207111683 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.343284 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.660206 # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.commit.committed_per_cycle::0 437166011 36.22% 36.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 432802967 35.85% 72.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 93484629 7.74% 79.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 134841213 11.17% 90.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 35727207 2.96% 93.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 23483214 1.95% 95.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 25551681 2.12% 98.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 8874954 0.74% 98.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 15179807 1.26% 100.00% # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.commit.committed_per_cycle::total 1207111683 # Number of insts commited each cycle
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.commit.committedInsts 880025312 # Number of instructions committed
system.cpu.commit.committedOps 1621493982 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 607228182 # Number of memory references committed
system.cpu.commit.loads 419042125 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 107161579 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.commit.bw_lim_events 15179807 # number cycles where commit BW limit reached
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.rob.rob_reads 3219190956 # The number of ROB reads
system.cpu.rob.rob_writes 4121324121 # The number of ROB writes
system.cpu.timesIdled 604 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 26926 # Total number of cycles that the CPU has spent unscheduled due to idling
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.committedInsts 880025312 # Number of Instructions Simulated
system.cpu.committedOps 1621493982 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 880025312 # Number of Instructions Simulated
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.cpi 1.447604 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.447604 # CPI: Total CPI of All Threads
system.cpu.ipc 0.690797 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.690797 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 4473882728 # number of integer regfile reads
system.cpu.int_regfile_writes 2589957068 # number of integer regfile writes
system.cpu.fp_regfile_reads 68 # number of floating regfile reads
system.cpu.misc_regfile_reads 911502074 # number of misc regfile reads
system.cpu.icache.replacements 17 # number of replacements
system.cpu.icache.tagsinuse 828.056964 # Cycle average of tags in use
system.cpu.icache.total_refs 185888078 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 930 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 199879.653763 # Average number of references to valid blocks.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.icache.occ_blocks::cpu.inst 828.056964 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.404325 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.404325 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 185888078 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 185888078 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 185888078 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 185888078 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 185888078 # number of overall hits
system.cpu.icache.overall_hits::total 185888078 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1361 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1361 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1361 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1361 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1361 # number of overall misses
system.cpu.icache.overall_misses::total 1361 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 47861000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 47861000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 47861000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 47861000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 47861000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 47861000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 185889439 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 185889439 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 185889439 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 185889439 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 185889439 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 185889439 # number of overall (read+write) accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35166.054372 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 35166.054372 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 35166.054372 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 35166.054372 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 35166.054372 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 35166.054372 # average overall miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 431 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 431 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 431 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 431 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 431 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 431 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 930 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 930 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 930 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 930 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 930 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 930 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34220000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 34220000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34220000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 34220000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34220000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 34220000 # number of overall MSHR miss cycles
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36795.698925 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36795.698925 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36795.698925 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 36795.698925 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36795.698925 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 36795.698925 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.replacements 445433 # number of replacements
system.cpu.dcache.tagsinuse 4093.428364 # Cycle average of tags in use
system.cpu.dcache.total_refs 452731874 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 449529 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 1007.124955 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 738592000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4093.428364 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999372 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999372 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 264792027 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 264792027 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 187939847 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 187939847 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 452731874 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 452731874 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 452731874 # number of overall hits
system.cpu.dcache.overall_hits::total 452731874 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 206669 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 206669 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 246210 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 246210 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 452879 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 452879 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 452879 # number of overall misses
system.cpu.dcache.overall_misses::total 452879 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1300622500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 1300622500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2040839000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2040839000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 3341461500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 3341461500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 3341461500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 3341461500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 264998696 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 264998696 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses)
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.demand_accesses::cpu.data 453184753 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 453184753 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 453184753 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 453184753 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000780 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000780 # miss rate for ReadReq accesses
X86 Regression: update stats due to cc register split
2012-05-22 18:38:04 +02:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001308 # miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.WriteReq_miss_rate::total 0.001308 # miss rate for WriteReq accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.000999 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000999 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000999 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000999 # miss rate for overall accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6293.263624 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 6293.263624 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8289.017505 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 8289.017505 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 7378.265497 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 7378.265497 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 7378.265497 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 7378.265497 # average overall miss latency
X86 Regressions: Update stats due to introduction of TSO
2012-01-29 02:09:17 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.writebacks::writebacks 428496 # number of writebacks
system.cpu.dcache.writebacks::total 428496 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3328 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 3328 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 20 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 20 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3348 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3348 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3348 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3348 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203341 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 203341 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246190 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 246190 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 449531 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 449531 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 449531 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 449531 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 607771500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 607771500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1249776500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1249776500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1857548000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 1857548000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1857548000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 1857548000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000767 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000767 # mshr miss rate for ReadReq accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001308 # mshr miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001308 # mshr miss rate for WriteReq accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.demand_mshr_miss_rate::total 0.000992 # mshr miss rate for demand accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.overall_mshr_miss_rate::total 0.000992 # mshr miss rate for overall accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2988.927467 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2988.927467 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 5076.471425 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 5076.471425 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 4132.191106 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 4132.191106 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 4132.191106 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 4132.191106 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.replacements 2658 # number of replacements
system.cpu.l2cache.tagsinuse 22224.770293 # Cycle average of tags in use
system.cpu.l2cache.total_refs 517694 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 24236 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 21.360538 # Average number of references to valid blocks.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.occ_blocks::writebacks 20809.314009 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 737.283312 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 678.172973 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.635050 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.022500 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.020696 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.678246 # Average percentage of cache occupancy
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_hits::cpu.inst 7 # number of ReadReq hits
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.ReadReq_hits::cpu.data 198771 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 198778 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 428496 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 428496 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 224280 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 224280 # number of ReadExReq hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_hits::cpu.inst 7 # number of demand (read+write) hits
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.demand_hits::cpu.data 423051 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 423058 # number of demand (read+write) hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.overall_hits::cpu.inst 7 # number of overall hits
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.overall_hits::cpu.data 423051 # number of overall hits
system.cpu.l2cache.overall_hits::total 423058 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 923 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 4558 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 5481 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 21922 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 21922 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 923 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 26480 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 27403 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 923 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 26480 # number of overall misses
system.cpu.l2cache.overall_misses::total 27403 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32677500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 156724000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 189401500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 752017500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 752017500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 32677500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 908741500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 941419000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 32677500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 908741500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 941419000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 930 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 203329 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 204259 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 428496 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 428496 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 246202 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 246202 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 930 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 449531 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 450461 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 930 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 449531 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 450461 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992473 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022417 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.026834 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089041 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.089041 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992473 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.058906 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.060833 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992473 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.058906 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.060833 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35403.575298 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34384.379114 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34556.011677 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34304.237752 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34304.237752 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35403.575298 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34318.032477 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34354.596212 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35403.575298 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34318.032477 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34354.596212 # average overall miss latency
X86 Regressions: Update stats due to introduction of TSO
2012-01-29 02:09:17 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
X86 Regressions: Update stats due to introduction of TSO
2012-01-29 02:09:17 +01:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.writebacks::writebacks 2543 # number of writebacks
system.cpu.l2cache.writebacks::total 2543 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 923 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4558 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 5481 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21922 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 21922 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 923 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 26480 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 27403 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 923 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 26480 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 27403 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29745000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 141788500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 171533500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 679883500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 679883500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29745000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 821672000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 851417000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29745000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 821672000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 851417000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992473 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022417 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026834 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089041 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089041 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992473 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058906 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.060833 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992473 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058906 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.060833 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32226.435536 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31107.612988 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31296.022624 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31013.753307 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31013.753307 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32226.435536 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31029.909366 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31070.211291 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32226.435536 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31029.909366 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31070.211291 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink