gem5/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.201717                       # Number of seconds simulated
sim_ticks                                201717314000                       # Number of ticks simulated
final_tick                               201717314000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1265309                       # Simulator instruction rate (inst/s)
host_op_rate                                  1519144                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              934796791                       # Simulator tick rate (ticks/s)
host_mem_usage                                 311752                       # Number of bytes of host memory used
host_seconds                                   215.79                       # Real time elapsed on the host
sim_insts                                   273037595                       # Number of instructions simulated
sim_ops                                     327811950                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst        1394641096                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data         480709216                       # Number of bytes read from this memory
system.physmem.bytes_read::total           1875350312                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst   1394641096                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total      1394641096                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data      400047763                       # Number of bytes written to this memory
system.physmem.bytes_written::total         400047763                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst          348660274                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data           86300511                       # Number of read requests responded to by this memory
system.physmem.num_reads::total             434960785                       # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data          82063567                       # Number of write requests responded to by this memory
system.physmem.num_writes::total             82063567                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst           6913839315                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data           2383083566                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              9296922881                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst      6913839315                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total         6913839315                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data          1983209845                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total             1983209845                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst          6913839315                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data          4366293411                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total            11280132726                       # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  191                       # Number of system calls
system.cpu.numCycles                        403434629                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   273037595                       # Number of instructions committed
system.cpu.committedOps                     327811950                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             258331481                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses              114216705                       # Number of float alu accesses
system.cpu.num_func_calls                    12448615                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts     15799338                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    258331481                       # number of integer instructions
system.cpu.num_fp_insts                     114216705                       # number of float instructions
system.cpu.num_int_register_reads          1174407516                       # number of times the integer registers were read
system.cpu.num_int_register_writes          162499657                       # number of times the integer registers were written
system.cpu.num_fp_register_reads            180262959                       # number of times the floating registers were read
system.cpu.num_fp_register_writes           126152315                       # number of times the floating registers were written
system.cpu.num_cc_register_reads            985884626                       # number of times the CC registers were read
system.cpu.num_cc_register_writes            76361749                       # number of times the CC registers were written
system.cpu.num_mem_refs                     168107829                       # number of memory refs
system.cpu.num_load_insts                    85732235                       # Number of load instructions
system.cpu.num_store_insts                   82375594                       # Number of store instructions
system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
system.cpu.num_busy_cycles               403434628.998000                       # Number of busy cycles
system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
system.cpu.Branches                          30563491                       # Number of branches fetched
system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
system.cpu.op_class::IntAlu                 104312493     31.82%     31.82% # Class of executed instruction
system.cpu.op_class::IntMult                  2145905      0.65%     32.48% # Class of executed instruction
system.cpu.op_class::IntDiv                         0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::FloatAdd                       0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd             6594343      2.01%     34.49% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     34.49% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp             7943502      2.42%     36.91% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt             3118180      0.95%     37.86% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv             1563217      0.48%     38.34% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc           19652356      6.00%     44.33% # Class of executed instruction
system.cpu.op_class::SimdFloatMult            7136937      2.18%     46.51% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc         7062098      2.15%     48.66% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt             175285      0.05%     48.72% # Class of executed instruction
system.cpu.op_class::MemRead                 85732235     26.15%     74.87% # Class of executed instruction
system.cpu.op_class::MemWrite                82375594     25.13%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                  327812145                       # Class of executed instruction
system.membus.trans_dist::ReadReq           434895828                       # Transaction distribution
system.membus.trans_dist::ReadResp          434906723                       # Transaction distribution
system.membus.trans_dist::WriteReq           82052672                       # Transaction distribution
system.membus.trans_dist::WriteResp          82052672                       # Transaction distribution
system.membus.trans_dist::SoftPFReq             54062                       # Transaction distribution
system.membus.trans_dist::SoftPFResp            54062                       # Transaction distribution
system.membus.trans_dist::LoadLockedReq         10895                       # Transaction distribution
system.membus.trans_dist::StoreCondReq          10895                       # Transaction distribution
system.membus.trans_dist::StoreCondResp         10895                       # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    697320548                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port    336728156                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total             1034048704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port   1394641096                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    880756979                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total              2275398075                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples         517024352                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.674359                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.468614                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0               168364078     32.56%     32.56% # Request fanout histogram
system.membus.snoop_fanout::1               348660274     67.44%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total           517024352                       # Request fanout histogram

---------- End Simulation Statistics   ----------