2006-10-12 21:04:14 +02:00
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|
---------- Begin Simulation Statistics ----------
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2013-03-01 19:20:30 +01:00
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|
sim_seconds 0.133774 # Number of seconds simulated
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|
sim_ticks 133773851500 # Number of ticks simulated
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|
final_tick 133773851500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
2011-06-21 00:57:14 +02:00
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|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
2013-03-01 19:20:30 +01:00
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|
host_inst_rate 262576 # Simulator instruction rate (inst/s)
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host_op_rate 262576 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 62108832 # Simulator tick rate (ticks/s)
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host_mem_usage 226536 # Number of bytes of host memory used
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|
host_seconds 2153.86 # Real time elapsed on the host
|
2011-06-21 00:57:14 +02:00
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sim_insts 565552443 # Number of instructions simulated
|
2012-02-12 23:07:43 +01:00
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|
sim_ops 565552443 # Number of ops (including micro ops) simulated
|
2013-03-01 19:20:30 +01:00
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|
system.physmem.bytes_read::cpu.inst 60992 # Number of bytes read from this memory
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|
system.physmem.bytes_read::cpu.data 1636544 # Number of bytes read from this memory
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system.physmem.bytes_read::total 1697536 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 60992 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 60992 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 67072 # Number of bytes written to this memory
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|
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system.physmem.bytes_written::total 67072 # Number of bytes written to this memory
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|
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|
system.physmem.num_reads::cpu.inst 953 # Number of read requests responded to by this memory
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|
system.physmem.num_reads::cpu.data 25571 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 26524 # Number of read requests responded to by this memory
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|
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|
system.physmem.num_writes::writebacks 1048 # Number of write requests responded to by this memory
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|
system.physmem.num_writes::total 1048 # Number of write requests responded to by this memory
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|
system.physmem.bw_read::cpu.inst 455934 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 12233661 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 12689595 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 455934 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 455934 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 501383 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 501383 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 501383 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 455934 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 12233661 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 13190979 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 26524 # Total number of read requests seen
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system.physmem.writeReqs 1048 # Total number of write requests seen
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system.physmem.cpureqs 27572 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 1697536 # Total number of bytes read from memory
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|
system.physmem.bytesWritten 67072 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 1697536 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 67072 # bytesWritten derated as per pkt->getSize()
|
2012-10-30 14:35:32 +01:00
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|
system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q
|
2012-10-25 19:14:42 +02:00
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|
|
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
2013-03-01 19:20:30 +01:00
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|
|
system.physmem.perBankRdReqs::0 1631 # Track reads on a per bank basis
|
2013-01-31 13:49:16 +01:00
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|
|
system.physmem.perBankRdReqs::1 1662 # Track reads on a per bank basis
|
2013-03-01 19:20:30 +01:00
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|
|
system.physmem.perBankRdReqs::2 1680 # Track reads on a per bank basis
|
2013-01-31 13:49:16 +01:00
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|
system.physmem.perBankRdReqs::3 1686 # Track reads on a per bank basis
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|
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|
system.physmem.perBankRdReqs::4 1626 # Track reads on a per bank basis
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|
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|
system.physmem.perBankRdReqs::5 1603 # Track reads on a per bank basis
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|
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|
system.physmem.perBankRdReqs::6 1584 # Track reads on a per bank basis
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|
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|
system.physmem.perBankRdReqs::7 1608 # Track reads on a per bank basis
|
2013-03-01 19:20:30 +01:00
|
|
|
system.physmem.perBankRdReqs::8 1666 # Track reads on a per bank basis
|
2013-01-31 13:49:16 +01:00
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|
|
system.physmem.perBankRdReqs::9 1722 # Track reads on a per bank basis
|
2013-03-01 19:20:30 +01:00
|
|
|
system.physmem.perBankRdReqs::10 1648 # Track reads on a per bank basis
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|
|
|
|
system.physmem.perBankRdReqs::11 1647 # Track reads on a per bank basis
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|
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|
|
system.physmem.perBankRdReqs::12 1724 # Track reads on a per bank basis
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|
|
|
|
system.physmem.perBankRdReqs::13 1665 # Track reads on a per bank basis
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|
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|
system.physmem.perBankRdReqs::14 1675 # Track reads on a per bank basis
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|
system.physmem.perBankRdReqs::15 1682 # Track reads on a per bank basis
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|
system.physmem.perBankWrReqs::0 60 # Track writes on a per bank basis
|
2013-01-31 13:49:16 +01:00
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|
system.physmem.perBankWrReqs::1 60 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 68 # Track writes on a per bank basis
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|
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|
system.physmem.perBankWrReqs::3 65 # Track writes on a per bank basis
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|
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|
system.physmem.perBankWrReqs::4 56 # Track writes on a per bank basis
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|
system.physmem.perBankWrReqs::5 58 # Track writes on a per bank basis
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|
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|
system.physmem.perBankWrReqs::6 53 # Track writes on a per bank basis
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|
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|
|
system.physmem.perBankWrReqs::7 56 # Track writes on a per bank basis
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|
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|
|
system.physmem.perBankWrReqs::8 64 # Track writes on a per bank basis
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|
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|
|
system.physmem.perBankWrReqs::9 75 # Track writes on a per bank basis
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|
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|
|
system.physmem.perBankWrReqs::10 63 # Track writes on a per bank basis
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|
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|
|
system.physmem.perBankWrReqs::11 61 # Track writes on a per bank basis
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|
system.physmem.perBankWrReqs::12 83 # Track writes on a per bank basis
|
2013-03-01 19:20:30 +01:00
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|
|
system.physmem.perBankWrReqs::13 73 # Track writes on a per bank basis
|
2013-01-31 13:49:16 +01:00
|
|
|
system.physmem.perBankWrReqs::14 72 # Track writes on a per bank basis
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|
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|
|
system.physmem.perBankWrReqs::15 81 # Track writes on a per bank basis
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
|
|
|
|
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
2013-03-01 19:20:30 +01:00
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|
|
system.physmem.totGap 133773818000 # Total gap between requests
|
2012-10-25 19:14:42 +02:00
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|
|
system.physmem.readPktSize::0 0 # Categorize read packet sizes
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|
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|
system.physmem.readPktSize::1 0 # Categorize read packet sizes
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|
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|
|
system.physmem.readPktSize::2 0 # Categorize read packet sizes
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|
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|
|
system.physmem.readPktSize::3 0 # Categorize read packet sizes
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|
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|
|
system.physmem.readPktSize::4 0 # Categorize read packet sizes
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|
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
2013-03-01 19:20:30 +01:00
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system.physmem.readPktSize::6 26524 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 1048 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 8806 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 11451 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 5143 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 1096 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see
|
2012-11-02 17:50:06 +01:00
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|
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
2012-10-30 14:35:32 +01:00
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|
|
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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|
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
2012-10-25 19:14:42 +02:00
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|
|
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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|
|
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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|
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|
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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|
|
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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|
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|
|
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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|
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|
|
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
|
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|
|
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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|
|
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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|
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|
|
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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|
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|
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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|
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|
|
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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|
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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|
|
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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|
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
2013-03-01 19:20:30 +01:00
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system.physmem.wrQLenPdf::0 41 # What write queue length does an incoming req see
|
2013-01-31 13:49:16 +01:00
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system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see
|
2012-10-30 14:35:32 +01:00
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system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 46 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 46 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 46 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 46 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 46 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 46 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 46 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 46 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 46 # What write queue length does an incoming req see
|
2013-01-31 13:49:16 +01:00
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|
|
system.physmem.wrQLenPdf::12 46 # What write queue length does an incoming req see
|
2013-03-01 19:20:30 +01:00
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|
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system.physmem.wrQLenPdf::13 45 # What write queue length does an incoming req see
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|
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system.physmem.wrQLenPdf::14 45 # What write queue length does an incoming req see
|
2012-10-30 14:35:32 +01:00
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|
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system.physmem.wrQLenPdf::15 45 # What write queue length does an incoming req see
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|
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system.physmem.wrQLenPdf::16 45 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 45 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 45 # What write queue length does an incoming req see
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|
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system.physmem.wrQLenPdf::19 45 # What write queue length does an incoming req see
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|
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system.physmem.wrQLenPdf::20 45 # What write queue length does an incoming req see
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|
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system.physmem.wrQLenPdf::21 45 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 45 # What write queue length does an incoming req see
|
2013-03-01 19:20:30 +01:00
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|
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system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see
|
2013-01-31 13:49:16 +01:00
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|
|
system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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|
|
|
|
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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|
|
|
|
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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|
|
|
|
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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|
|
|
|
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
2013-03-01 19:20:30 +01:00
|
|
|
system.physmem.totQLat 654284750 # Total cycles spent in queuing delays
|
|
|
|
|
system.physmem.totMemAccLat 1345973500 # Sum of mem lat for all requests
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|
|
|
|
system.physmem.totBusLat 132545000 # Total cycles spent in databus access
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|
|
|
|
system.physmem.totBankLat 559143750 # Total cycles spent in bank access
|
|
|
|
|
system.physmem.avgQLat 24681.61 # Average queueing delay per request
|
|
|
|
|
system.physmem.avgBankLat 21092.60 # Average bank access latency per request
|
2013-01-31 13:49:16 +01:00
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|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
2013-03-01 19:20:30 +01:00
|
|
|
system.physmem.avgMemAccLat 50774.21 # Average memory access latency
|
2012-11-02 17:50:06 +01:00
|
|
|
system.physmem.avgRdBW 12.69 # Average achieved read bandwidth in MB/s
|
|
|
|
|
system.physmem.avgWrBW 0.50 # Average achieved write bandwidth in MB/s
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|
|
|
|
system.physmem.avgConsumedRdBW 12.69 # Average consumed read bandwidth in MB/s
|
|
|
|
|
system.physmem.avgConsumedWrBW 0.50 # Average consumed write bandwidth in MB/s
|
2013-01-31 13:49:16 +01:00
|
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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|
|
|
|
system.physmem.busUtil 0.10 # Data bus utilization in percentage
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.avgRdQLen 0.01 # Average read queue length over time
|
2013-03-01 19:20:30 +01:00
|
|
|
system.physmem.avgWrQLen 9.24 # Average write queue length over time
|
|
|
|
|
system.physmem.readRowHits 16966 # Number of row buffer hits during reads
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|
|
|
|
system.physmem.writeRowHits 271 # Number of row buffer hits during writes
|
|
|
|
|
system.physmem.readRowHitRate 64.00 # Row buffer hit rate for reads
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|
|
|
|
system.physmem.writeRowHitRate 25.86 # Row buffer hit rate for writes
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|
|
|
|
system.physmem.avgGap 4851799.58 # Average gap between requests
|
|
|
|
|
system.cpu.branchPred.lookups 76502410 # Number of BP lookups
|
|
|
|
|
system.cpu.branchPred.condPredicted 70922676 # Number of conditional branches predicted
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|
|
|
|
system.cpu.branchPred.condIncorrect 2717282 # Number of conditional branches incorrect
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|
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|
|
system.cpu.branchPred.BTBLookups 43095322 # Number of BTB lookups
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|
|
|
system.cpu.branchPred.BTBHits 41949760 # Number of BTB hits
|
2013-01-24 19:29:00 +01:00
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|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.branchPred.BTBHitPct 97.341795 # BTB Hit Percentage
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|
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|
|
system.cpu.branchPred.usedRAS 1606512 # Number of times the RAS was used to get a target.
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|
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|
system.cpu.branchPred.RASInCorrect 241 # Number of incorrect RAS predictions.
|
2009-04-09 07:21:30 +02:00
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|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
|
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.dtb.read_hits 122629608 # DTB read hits
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|
|
|
|
system.cpu.dtb.read_misses 28810 # DTB read misses
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.dtb.read_accesses 122658418 # DTB read accesses
|
|
|
|
|
system.cpu.dtb.write_hits 40760367 # DTB write hits
|
|
|
|
|
system.cpu.dtb.write_misses 25602 # DTB write misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.dtb.write_accesses 40785969 # DTB write accesses
|
|
|
|
|
system.cpu.dtb.data_hits 163389975 # DTB hits
|
|
|
|
|
system.cpu.dtb.data_misses 54412 # DTB misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.dtb.data_accesses 163444387 # DTB accesses
|
|
|
|
|
system.cpu.itb.fetch_hits 65529846 # ITB hits
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.itb.fetch_misses 41 # ITB misses
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.itb.fetch_accesses 65529887 # ITB accesses
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
|
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.workload.num_syscalls 17 # Number of system calls
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.numCycles 267547704 # number of cpu cycles simulated
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.fetch.icacheStallCycles 67181660 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.Insts 699454641 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.Branches 76502410 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.predictedBranches 43556272 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.Cycles 117851527 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.SquashCycles 11664601 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.BlockedCycles 73301689 # Number of cycles fetch has spent blocked
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.fetch.PendingTrapStallCycles 1199 # Number of stall cycles due to pending traps
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 21 # Number of stall cycles due to full MSHR
|
|
|
|
|
system.cpu.fetch.CacheLines 65529846 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 933458 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.rateDist::samples 267250540 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::mean 2.617224 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::stdev 3.444995 # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.fetch.rateDist::0 149399013 55.90% 55.90% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::1 10348526 3.87% 59.77% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::2 11849388 4.43% 64.21% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::3 10578020 3.96% 68.17% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::4 7012807 2.62% 70.79% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::5 2871984 1.07% 71.87% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::6 3578789 1.34% 73.20% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::7 3106707 1.16% 74.37% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::8 68505306 25.63% 100.00% # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.fetch.rateDist::total 267250540 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.branchRate 0.285939 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.rate 2.614317 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu.decode.IdleCycles 84320129 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.BlockedCycles 57595253 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.RunCycles 102753479 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.UnblockCycles 13668133 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.decode.SquashCycles 8913546 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.BranchResolved 3876280 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu.decode.BranchMispred 932 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu.decode.DecodedInsts 691464517 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.SquashedInsts 3449 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu.rename.SquashCycles 8913546 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.IdleCycles 92299678 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.BlockCycles 12776720 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.serializeStallCycles 1189 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RunCycles 103108433 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.UnblockCycles 50150974 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RenamedInsts 681302234 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.ROBFullEvents 431 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu.rename.IQFullEvents 38477727 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.LSQFullEvents 5455282 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RenamedOperands 520934901 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RenameLookups 897390123 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.int_rename_lookups 897387366 # Number of integer rename lookups
|
|
|
|
|
system.cpu.rename.fp_rename_lookups 2757 # Number of floating rename lookups
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.rename.UndoneMaps 57080012 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.serializingInsts 63 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.tempSerializingInsts 67 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.rename.skidInsts 112027328 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.memDep0.insertedLoads 127008438 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 42384710 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.conflictingLoads 14844783 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 10088023 # Number of conflicting stores.
|
|
|
|
|
system.cpu.iq.iqInstsAdded 621271293 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqInstsIssued 604725807 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 299798 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 55080788 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 30005964 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 38 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.issued_per_cycle::samples 267250540 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::mean 2.262767 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::stdev 1.823653 # Number of insts issued each cycle
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::0 52429829 19.62% 19.62% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::1 55852855 20.90% 40.52% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::2 53444845 20.00% 60.52% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::3 36460113 13.64% 74.16% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::4 31255141 11.70% 85.85% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::5 23773948 8.90% 94.75% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::6 10075913 3.77% 98.52% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::7 3406027 1.27% 99.79% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::8 551869 0.21% 100.00% # Number of insts issued each cycle
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::total 267250540 # Number of insts issued each cycle
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.iq.fu_full::IntAlu 2756472 71.14% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntMult 40 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemRead 728591 18.80% 89.94% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemWrite 389871 10.06% 100.00% # attempts to use FU when none available
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.iq.FU_type_0::IntAlu 439176954 72.62% 72.62% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntMult 7066 0.00% 72.63% # Type of FU issued
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.63% # Type of FU issued
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.iq.FU_type_0::MemRead 124356224 20.56% 93.19% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 41185515 6.81% 100.00% # Type of FU issued
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.iq.FU_type_0::total 604725807 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 2.260254 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 3874974 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.006408 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 1480873086 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 676355161 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 596602519 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 3840 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 2402 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 1730 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 608598846 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 1935 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 12280408 # Number of loads that had data forwarded from stores
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 12494396 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 35705 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 5495 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 2933389 # Number of stores squashed
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 6442 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 54892 # Number of times an access to memory failed due to the cache being blocked
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.iew.iewSquashCycles 8913546 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 1440408 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 191911 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 664145675 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 1694595 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 127008438 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 42384710 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 55 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 143753 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 7490 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 5495 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 1342563 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 1811283 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 3153846 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 599598114 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 122658565 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 5127693 # Number of squashed instructions skipped in execute
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.iew.exec_nop 42874327 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 163462793 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 66641793 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 40804228 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 2.241089 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 597543507 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 596604249 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 415969736 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 530347418 # num instructions consuming a value
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.iew.wb_rate 2.229899 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.784334 # average fanout of values written-back
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.commit.commitSquashedInsts 62164646 # The number of squashed insts skipped by commit
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.commit.branchMispredicts 2716416 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 258336994 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 2.329736 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.693311 # Number of insts commited each cycle
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::0 79521079 30.78% 30.78% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 72557315 28.09% 58.87% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 25650829 9.93% 68.80% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 9136101 3.54% 72.33% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 10241480 3.96% 76.30% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 20967757 8.12% 84.41% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 6801640 2.63% 87.05% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 3711202 1.44% 88.48% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 29749591 11.52% 100.00% # Number of insts commited each cycle
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::total 258336994 # Number of insts commited each cycle
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.commit.committedInsts 601856963 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.refs 153965363 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 114514042 # Number of loads committed
|
|
|
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
|
|
|
system.cpu.commit.branches 62547159 # Number of branches committed
|
|
|
|
|
system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu.commit.int_insts 563954763 # Number of committed integer instructions.
|
|
|
|
|
system.cpu.commit.function_calls 1197610 # Number of function calls committed.
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.commit.bw_lim_events 29749591 # number cycles where commit BW limit reached
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.rob.rob_reads 892544623 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 1336970755 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 34274 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 297164 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.committedInsts 565552443 # Number of Instructions Simulated
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.cpi 0.473073 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.473073 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 2.113838 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 2.113838 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 845171662 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 490625638 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 396 # number of floating regfile reads
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.fp_regfile_writes 54 # number of floating regfile writes
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.icache.replacements 39 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 824.684718 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 65528462 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 971 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 67485.542739 # Average number of references to valid blocks.
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.icache.occ_blocks::cpu.inst 824.684718 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.occ_percent::cpu.inst 0.402678 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_percent::total 0.402678 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 65528462 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 65528462 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 65528462 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 65528462 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 65528462 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 65528462 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1383 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 1383 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 1383 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 1383 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 1383 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 1383 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 72600500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 72600500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 72600500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::total 72600500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 72600500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::total 72600500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 65529845 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 65529845 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 65529845 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 65529845 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 65529845 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 65529845 # number of overall (read+write) accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52494.938539 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 52494.938539 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52494.938539 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total 52494.938539 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52494.938539 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total 52494.938539 # average overall miss latency
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 25.400000 # average number of cycles each access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 412 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits::total 412 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 412 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::total 412 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 412 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::total 412 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 971 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 971 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 971 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 971 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 971 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 971 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54205000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 54205000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54205000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 54205000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54205000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 54205000 # number of overall MSHR miss cycles
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55823.892894 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55823.892894 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55823.892894 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 55823.892894 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55823.892894 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 55823.892894 # average overall mshr miss latency
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.l2cache.replacements 1081 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 22920.644164 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 547028 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 23516 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 23.261949 # Average number of references to valid blocks.
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.l2cache.occ_blocks::writebacks 21474.762913 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 815.139111 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.data 630.742140 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_percent::writebacks 0.655358 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.024876 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.019249 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::total 0.699483 # Average percentage of cache occupancy
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 18 # number of ReadReq hits
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 206066 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 206084 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 444903 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 444903 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 233285 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 233285 # number of ReadExReq hits
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 439351 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 439369 # number of demand (read+write) hits
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 439351 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 439369 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 953 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 4305 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 5258 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 21266 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 21266 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 953 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 25571 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 26524 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 953 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 25571 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 26524 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 53037500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 418895500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 471933000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1507958500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 1507958500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 53037500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 1926854000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 1979891500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 53037500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 1926854000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 1979891500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 971 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 210371 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 211342 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 444903 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 444903 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254551 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 254551 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 971 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 464922 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 465893 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 971 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 464922 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 465893 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.981462 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020464 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.024879 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083543 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.083543 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.981462 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.055001 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::total 0.056932 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.981462 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.055001 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::total 0.056932 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55653.200420 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 97304.413473 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 89755.230126 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70909.362362 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70909.362362 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55653.200420 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75353.095303 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 74645.283517 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55653.200420 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75353.095303 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 74645.283517 # average overall miss latency
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.l2cache.writebacks::writebacks 1049 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.writebacks::total 1049 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 953 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4305 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 5258 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21266 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 21266 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 953 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 25571 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 26524 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 953 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 25571 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 26524 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41181755 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 363891160 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 405072915 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1243149416 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1243149416 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41181755 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1607040576 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 1648222331 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41181755 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1607040576 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 1648222331 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.981462 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020464 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024879 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083543 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083543 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.981462 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055001 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.056932 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.981462 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055001 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.056932 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43212.754460 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 84527.563298 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77039.352415 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58457.134205 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58457.134205 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43212.754460 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62846.215478 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62140.790642 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43212.754460 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62846.215478 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62140.790642 # average overall mshr miss latency
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.dcache.replacements 460826 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4090.898597 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 146919615 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 464922 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 316.009169 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 301835000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::cpu.data 4090.898597 # Average occupied blocks per requestor
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.dcache.occ_percent::cpu.data 0.998755 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.occ_percent::total 0.998755 # Average percentage of cache occupancy
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 109271003 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 109271003 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 37648598 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 37648598 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 14 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::total 14 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::cpu.data 146919601 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 146919601 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 146919601 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 146919601 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1024794 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 1024794 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1802723 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 1802723 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses::cpu.data 2827517 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 2827517 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 2827517 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 2827517 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 15336763000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 15336763000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 26197701326 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 26197701326 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 20000 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 20000 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 41534464326 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 41534464326 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 41534464326 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 41534464326 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 110295797 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 110295797 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 16 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 149747118 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 149747118 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 149747118 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 149747118 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009291 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.009291 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045695 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.045695 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.125000 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.125000 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.018882 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.018882 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.018882 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.018882 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14965.703351 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 14965.703351 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14532.294382 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 14532.294382 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10000 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10000 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14689.377403 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::total 14689.377403 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14689.377403 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::total 14689.377403 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 303569 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 2051 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 17829 # number of cycles access was blocked
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.026698 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 186.454545 # average number of cycles each access was blocked
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2013-03-01 19:20:30 +01:00
|
|
|
system.cpu.dcache.writebacks::writebacks 444903 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 444903 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 814423 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 814423 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1548172 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 1548172 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 2362595 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 2362595 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 2362595 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 2362595 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210371 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 210371 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254551 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 254551 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 464922 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 464922 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 464922 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 464922 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2696208000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2696208000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4103693497 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4103693497 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6799901497 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 6799901497 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6799901497 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 6799901497 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001907 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001907 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006452 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006452 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003105 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.003105 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003105 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.003105 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12816.443331 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12816.443331 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16121.301810 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16121.301810 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14625.897456 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14625.897456 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14625.897456 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14625.897456 # average overall mshr miss latency
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2006-10-12 21:04:14 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
