2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2013-03-28 00:36:21 +01:00
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sim_seconds 0.164563 # Number of seconds simulated
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sim_ticks 164562530500 # Number of ticks simulated
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final_tick 164562530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2013-03-28 00:36:21 +01:00
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host_inst_rate 62422 # Simulator instruction rate (inst/s)
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host_op_rate 65960 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 18020016 # Simulator tick rate (ticks/s)
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host_mem_usage 288128 # Number of bytes of host memory used
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host_seconds 9132.21 # Real time elapsed on the host
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2013-01-08 14:54:16 +01:00
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sim_insts 570051585 # Number of instructions simulated
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sim_ops 602359791 # Number of ops (including micro ops) simulated
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2013-03-28 00:36:21 +01:00
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system.physmem.bytes_read::cpu.inst 46976 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 1701120 # Number of bytes read from this memory
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system.physmem.bytes_read::total 1748096 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 46976 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 46976 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 162368 # Number of bytes written to this memory
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system.physmem.bytes_written::total 162368 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 734 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 26580 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 27314 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 2537 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 2537 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 285460 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 10337226 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 10622685 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 285460 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 285460 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 986664 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 986664 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 986664 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 285460 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 10337226 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 11609350 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 27315 # Total number of read requests seen
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system.physmem.writeReqs 2537 # Total number of write requests seen
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system.physmem.cpureqs 29852 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 1748096 # Total number of bytes read from memory
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system.physmem.bytesWritten 162368 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 1748096 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 162368 # bytesWritten derated as per pkt->getSize()
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2012-10-30 14:35:32 +01:00
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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2012-10-25 19:14:42 +02:00
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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2013-03-28 00:36:21 +01:00
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system.physmem.perBankRdReqs::0 1691 # Track reads on a per bank basis
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2013-01-31 13:49:16 +01:00
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system.physmem.perBankRdReqs::1 1726 # Track reads on a per bank basis
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2013-03-28 00:36:21 +01:00
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system.physmem.perBankRdReqs::2 1689 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 1687 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 1721 # Track reads on a per bank basis
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2013-01-31 13:49:16 +01:00
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system.physmem.perBankRdReqs::5 1753 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 1671 # Track reads on a per bank basis
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2013-03-28 00:36:21 +01:00
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system.physmem.perBankRdReqs::7 1696 # Track reads on a per bank basis
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2013-01-31 13:49:16 +01:00
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system.physmem.perBankRdReqs::8 1674 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 1668 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 1702 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 1735 # Track reads on a per bank basis
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2013-03-28 00:36:21 +01:00
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system.physmem.perBankRdReqs::12 1759 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 1740 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 1723 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 1680 # Track reads on a per bank basis
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2013-01-31 13:49:16 +01:00
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system.physmem.perBankWrReqs::0 161 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis
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2013-01-08 14:54:16 +01:00
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system.physmem.perBankWrReqs::2 158 # Track writes on a per bank basis
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2013-01-31 13:49:16 +01:00
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system.physmem.perBankWrReqs::3 158 # Track writes on a per bank basis
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2013-03-28 00:36:21 +01:00
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system.physmem.perBankWrReqs::4 159 # Track writes on a per bank basis
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2013-01-31 13:49:16 +01:00
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system.physmem.perBankWrReqs::5 158 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 156 # Track writes on a per bank basis
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2013-03-28 00:36:21 +01:00
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system.physmem.perBankWrReqs::7 157 # Track writes on a per bank basis
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2013-01-31 13:49:16 +01:00
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system.physmem.perBankWrReqs::8 158 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 156 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 157 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 160 # Track writes on a per bank basis
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2013-03-28 00:36:21 +01:00
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system.physmem.perBankWrReqs::12 163 # Track writes on a per bank basis
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2013-01-31 13:49:16 +01:00
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system.physmem.perBankWrReqs::13 162 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 160 # Track writes on a per bank basis
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2012-10-30 14:35:32 +01:00
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system.physmem.perBankWrReqs::15 157 # Track writes on a per bank basis
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2012-10-25 19:14:42 +02:00
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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2013-03-28 00:36:21 +01:00
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system.physmem.totGap 164562514500 # Total gap between requests
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2012-10-25 19:14:42 +02:00
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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2013-03-28 00:36:21 +01:00
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system.physmem.readPktSize::6 27315 # Categorize read packet sizes
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2013-03-01 19:20:30 +01:00
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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2013-03-28 00:36:21 +01:00
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system.physmem.writePktSize::6 2537 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 14709 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 3454 # What read queue length does an incoming req see
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2013-01-31 13:49:16 +01:00
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system.physmem.rdQLenPdf::2 8340 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 806 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
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2012-10-30 14:35:32 +01:00
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system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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2012-10-25 19:14:42 +02:00
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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2013-01-31 13:49:16 +01:00
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system.physmem.wrQLenPdf::0 71 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 96 # What write queue length does an incoming req see
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2012-10-30 14:35:32 +01:00
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system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 111 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 111 # What write queue length does an incoming req see
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2013-03-28 00:36:21 +01:00
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system.physmem.wrQLenPdf::7 110 # What write queue length does an incoming req see
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2013-01-31 13:49:16 +01:00
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system.physmem.wrQLenPdf::8 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 110 # What write queue length does an incoming req see
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2012-10-30 14:35:32 +01:00
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system.physmem.wrQLenPdf::10 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see
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2013-01-31 13:49:16 +01:00
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system.physmem.wrQLenPdf::23 40 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see
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2012-10-30 14:35:32 +01:00
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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2012-10-25 19:14:42 +02:00
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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2013-03-28 00:36:21 +01:00
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system.physmem.totQLat 922192000 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 1672085750 # Sum of mem lat for all requests
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system.physmem.totBusLat 136575000 # Total cycles spent in databus access
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system.physmem.totBankLat 613318750 # Total cycles spent in bank access
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system.physmem.avgQLat 33761.38 # Average queueing delay per request
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system.physmem.avgBankLat 22453.55 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 61214.93 # Average memory access latency
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system.physmem.avgRdBW 10.62 # Average achieved read bandwidth in MB/s
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2012-11-02 17:50:06 +01:00
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system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s
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2013-03-28 00:36:21 +01:00
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system.physmem.avgConsumedRdBW 10.62 # Average consumed read bandwidth in MB/s
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2012-11-02 17:50:06 +01:00
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system.physmem.avgConsumedWrBW 0.99 # Average consumed write bandwidth in MB/s
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2013-01-31 13:49:16 +01:00
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 0.09 # Data bus utilization in percentage
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2012-10-25 19:14:42 +02:00
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system.physmem.avgRdQLen 0.01 # Average read queue length over time
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2013-03-28 00:36:21 +01:00
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system.physmem.avgWrQLen 5.61 # Average write queue length over time
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system.physmem.readRowHits 16878 # Number of row buffer hits during reads
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2013-01-31 13:49:16 +01:00
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system.physmem.writeRowHits 1046 # Number of row buffer hits during writes
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2013-03-28 00:36:21 +01:00
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system.physmem.readRowHitRate 61.79 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 41.23 # Row buffer hit rate for writes
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system.physmem.avgGap 5512612.71 # Average gap between requests
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system.cpu.branchPred.lookups 85150983 # Number of BP lookups
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system.cpu.branchPred.condPredicted 79934550 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 2340692 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 47125153 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 46874770 # Number of BTB hits
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2013-01-24 19:29:00 +01:00
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2013-03-28 00:36:21 +01:00
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system.cpu.branchPred.BTBHitPct 99.468685 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 1426734 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 1006 # Number of incorrect RAS predictions.
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.workload.num_syscalls 48 # Number of system calls
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.numCycles 329125062 # number of cpu cycles simulated
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.fetch.icacheStallCycles 68488081 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.Insts 666859732 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.Branches 85150983 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.predictedBranches 48301504 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.Cycles 129623989 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.SquashCycles 13095310 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.BlockedCycles 119330996 # Number of cycles fetch has spent blocked
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.fetch.PendingTrapStallCycles 265 # Number of stall cycles due to pending traps
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.fetch.CacheLines 67073182 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 755353 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.rateDist::samples 328169942 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::mean 2.165410 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::stdev 3.193997 # Number of instructions fetched each cycle (Total)
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.fetch.rateDist::0 198546194 60.50% 60.50% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::1 20910126 6.37% 66.87% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::2 4967453 1.51% 68.39% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::3 14343462 4.37% 72.76% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::4 8888191 2.71% 75.47% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::5 9444820 2.88% 78.34% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::6 4399595 1.34% 79.68% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::7 5788141 1.76% 81.45% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::8 60881960 18.55% 100.00% # Number of instructions fetched each cycle (Total)
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.fetch.rateDist::total 328169942 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.branchRate 0.258719 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.rate 2.026159 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu.decode.IdleCycles 92898933 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.BlockedCycles 96237751 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.RunCycles 107895398 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.UnblockCycles 20412735 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.decode.SquashCycles 10725125 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.BranchResolved 4735181 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu.decode.BranchMispred 1555 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu.decode.DecodedInsts 703255584 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.SquashedInsts 5767 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu.rename.SquashCycles 10725125 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.IdleCycles 107098247 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.BlockCycles 14386106 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.serializeStallCycles 39798 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RunCycles 114033717 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.UnblockCycles 81886949 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RenamedInsts 694825042 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.ROBFullEvents 45 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu.rename.IQFullEvents 59412332 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.LSQFullEvents 20333868 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.FullRegisterEvents 677 # Number of times there has been no free registers
|
|
|
|
|
system.cpu.rename.RenamedOperands 721309974 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RenameLookups 3230585653 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.int_rename_lookups 3230585525 # Number of integer rename lookups
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.rename.CommittedMaps 627417373 # Number of HB maps that are committed
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.rename.UndoneMaps 93892601 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.serializingInsts 1652 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.tempSerializingInsts 1598 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.rename.skidInsts 170754110 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.memDep0.insertedLoads 172203089 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 80461729 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.conflictingLoads 21612175 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 28771400 # Number of conflicting stores.
|
|
|
|
|
system.cpu.iq.iqInstsAdded 679988719 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 2878 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqInstsIssued 645594653 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 1373062 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 77449325 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 193321568 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 174 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.issued_per_cycle::samples 328169942 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::mean 1.967257 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::stdev 1.725062 # Number of insts issued each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::0 68186439 20.78% 20.78% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::1 85247300 25.98% 46.75% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::2 75946350 23.14% 69.90% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::3 40813735 12.44% 82.33% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::4 28838397 8.79% 91.12% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::5 14924394 4.55% 95.67% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::6 5564389 1.70% 97.36% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::7 6539948 1.99% 99.36% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::8 2108990 0.64% 100.00% # Number of insts issued each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::total 328169942 # Number of insts issued each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.iq.fu_full::IntAlu 216923 5.73% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.73% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemRead 2702396 71.39% 77.12% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemWrite 865914 22.88% 100.00% # attempts to use FU when none available
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.iq.FU_type_0::IntAlu 403371824 62.48% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntMult 6559 0.00% 62.48% # Type of FU issued
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.48% # Type of FU issued
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.iq.FU_type_0::MemRead 165561293 25.64% 88.13% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 76654974 11.87% 100.00% # Type of FU issued
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.iq.FU_type_0::total 645594653 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 1.961548 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 3785233 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.005863 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 1624517507 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 757453052 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 637549292 # Number of integer instruction queue wakeup accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.iq.int_alu_accesses 649379866 # Number of integer alu accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 30368159 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 23250496 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 123413 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 12359 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 10240716 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 12899 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 36224 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.iew.iewSquashCycles 10725125 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 795867 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 92517 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 679994676 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 687635 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 172203089 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 80461729 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 1550 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 32824 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 16429 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 12359 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 1356301 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 1461196 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 2817497 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 641509024 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 163485499 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 4085629 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.iew.exec_nop 3079 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 239366742 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 74672084 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 75881243 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.949135 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 638953926 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 637549308 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 418527294 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 649860425 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.iew.wb_rate 1.937103 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.644026 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.commit.commitSquashedInsts 77643008 # The number of squashed insts skipped by commit
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.commit.commitNonSpecStalls 2704 # The number of times commit has been forced to stall to communicate backwards
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.commit.branchMispredicts 2339215 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 317444817 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.897526 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.237559 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::0 93252713 29.38% 29.38% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 104341557 32.87% 62.25% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 42984071 13.54% 75.79% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 8786627 2.77% 78.55% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 25947006 8.17% 86.73% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 12913913 4.07% 90.80% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 7624115 2.40% 93.20% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 1170537 0.37% 93.57% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 20424278 6.43% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::total 317444817 # Number of insts commited each cycle
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.commit.committedInsts 570051636 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.committedOps 602359842 # Number of ops (including micro ops) committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.commit.refs 219173606 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 148952593 # Number of loads committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.membars 1328 # Number of memory barriers committed
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.commit.branches 70892524 # Number of branches committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.commit.int_insts 533522631 # Number of committed integer instructions.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.function_calls 997573 # Number of function calls committed.
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.commit.bw_lim_events 20424278 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.rob.rob_reads 977022777 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 1370762747 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 43954 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 955120 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.committedInsts 570051585 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedOps 602359791 # Number of Ops (including micro ops) Simulated
|
|
|
|
|
system.cpu.committedInsts_total 570051585 # Number of Instructions Simulated
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.cpi 0.577360 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.577360 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.732021 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.732021 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 3204272502 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 663034338 # number of integer regfile writes
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.misc_regfile_reads 234758554 # number of misc regfile reads
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.misc_regfile_writes 2656 # number of misc regfile writes
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.icache.replacements 49 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 688.587828 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 67072069 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 83009.986386 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.icache.occ_blocks::cpu.inst 688.587828 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.occ_percent::cpu.inst 0.336225 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_percent::total 0.336225 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 67072069 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 67072069 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 67072069 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 67072069 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 67072069 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 67072069 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1113 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 1113 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 1113 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 1113 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 1113 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 1113 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 54408499 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 54408499 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 54408499 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::total 54408499 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 54408499 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::total 54408499 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 67073182 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 67073182 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 67073182 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 67073182 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 67073182 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 67073182 # number of overall (read+write) accesses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48884.545373 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 48884.545373 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 48884.545373 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total 48884.545373 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 48884.545373 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total 48884.545373 # average overall miss latency
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 288 # number of cycles access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 41.142857 # average number of cycles each access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 304 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits::total 304 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 304 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::total 304 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 304 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::total 304 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 809 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 809 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 809 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 809 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 809 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 809 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42322999 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 42322999 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42322999 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 42322999 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42322999 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 42322999 # number of overall MSHR miss cycles
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52315.202719 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52315.202719 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52315.202719 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 52315.202719 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52315.202719 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 52315.202719 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.l2cache.replacements 2559 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 22357.775190 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 517077 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 24151 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 21.410169 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.l2cache.occ_blocks::writebacks 20763.745562 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 648.701789 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.data 945.327839 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_percent::writebacks 0.633659 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.019797 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.028849 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::total 0.682305 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 74 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 192736 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 192810 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 421641 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 421641 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 225382 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 225382 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 74 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 418118 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 418192 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 74 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 418118 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 418192 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 735 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 4798 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 5533 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 21792 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 21792 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 735 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 26590 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 27325 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 735 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 26590 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 27325 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 40758000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 686475000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 727233000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1582356000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 1582356000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 40758000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 2268831000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 2309589000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 40758000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 2268831000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 2309589000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 809 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 197534 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 198343 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 421641 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 421641 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247174 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 247174 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 809 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 444708 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 445517 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 809 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 444708 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 445517 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.908529 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024289 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.027896 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.088165 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.088165 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.908529 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.059792 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::total 0.061333 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.908529 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.059792 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::total 0.061333 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55453.061224 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 143075.239683 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 131435.568408 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72611.784141 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72611.784141 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55453.061224 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85326.476119 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 84522.927722 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55453.061224 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85326.476119 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 84522.927722 # average overall miss latency
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.l2cache.writebacks::writebacks 2537 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.writebacks::total 2537 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 734 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4789 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 5523 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21792 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 21792 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 734 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 26581 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 27315 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 734 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 26581 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 27315 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31595584 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 627096612 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 658692196 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1310573848 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1310573848 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31595584 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1937670460 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 1969266044 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31595584 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1937670460 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 1969266044 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.907293 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024244 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027846 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088165 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088165 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.907293 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059772 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.061311 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.907293 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059772 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.061311 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43045.754768 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 130945.210274 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 119263.479269 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60140.136197 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60140.136197 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43045.754768 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72896.823295 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72094.674867 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43045.754768 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72896.823295 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72094.674867 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.dcache.replacements 440610 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4091.483802 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 197562457 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 444706 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 444.254085 # Average number of references to valid blocks.
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.dcache.warmup_cycle 314058000 # Cycle when the warmup percentage was hit.
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.dcache.occ_blocks::cpu.data 4091.483802 # Average occupied blocks per requestor
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.dcache.occ_percent::cpu.data 0.998897 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.occ_percent::total 0.998897 # Average percentage of cache occupancy
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 131512310 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 131512310 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 66047494 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 66047494 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1326 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::total 1326 # number of LoadLockedReq hits
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.dcache.demand_hits::cpu.data 197559804 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 197559804 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 197559804 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 197559804 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 341685 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 341685 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 3370037 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 3370037 # number of WriteReq misses
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 22 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses::total 22 # number of LoadLockedReq misses
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.dcache.demand_misses::cpu.data 3711722 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 3711722 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 3711722 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 3711722 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5064964500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 5064964500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 40707637762 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 40707637762 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 338000 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 338000 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 45772602262 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 45772602262 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 45772602262 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 45772602262 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 131853995 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 131853995 # number of ReadReq accesses(hits+misses)
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1348 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 1348 # number of LoadLockedReq accesses(hits+misses)
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses)
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 201271526 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 201271526 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 201271526 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 201271526 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002591 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.002591 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048547 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.048547 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.016320 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.016320 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.018441 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.018441 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.018441 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.018441 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14823.490935 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 14823.490935 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12079.285112 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 12079.285112 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15363.636364 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15363.636364 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 12331.904777 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::total 12331.904777 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 12331.904777 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::total 12331.904777 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 146535 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 32 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 5250 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.911429 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.dcache.writebacks::writebacks 421641 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 421641 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144151 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 144151 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3122863 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 3122863 # number of WriteReq MSHR hits
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 3267014 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 3267014 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 3267014 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 3267014 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197534 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 197534 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247174 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 247174 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 444708 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 444708 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 444708 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 444708 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2832398000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2832398000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4097760821 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4097760821 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6930158821 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 6930158821 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6930158821 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 6930158821 # number of overall MSHR miss cycles
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001498 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001498 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003561 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003561 # mshr miss rate for WriteReq accesses
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.002209 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14338.787247 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14338.787247 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16578.446038 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16578.446038 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15583.616263 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15583.616263 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15583.616263 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15583.616263 # average overall mshr miss latency
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
