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gem5/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt

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ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
sim_seconds 0.163308 # Number of seconds simulated
sim_ticks 163308075000 # Number of ticks simulated
final_tick 163308075000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
host_inst_rate 134720 # Simulator instruction rate (inst/s)
host_op_rate 142356 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 38594530 # Simulator tick rate (ticks/s)
host_mem_usage 233164 # Number of bytes of host memory used
host_seconds 4231.38 # Real time elapsed on the host
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
sim_insts 570052710 # Number of instructions simulated
sim_ops 602360916 # Number of ops (including micro ops) simulated
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.bytes_read::cpu.inst 48512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1771456 # Number of bytes read from this memory
system.physmem.bytes_read::total 1819968 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 48512 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 48512 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 204864 # Number of bytes written to this memory
system.physmem.bytes_written::total 204864 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 758 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 27679 # Number of read requests responded to by this memory
system.physmem.num_reads::total 28437 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 3201 # Number of write requests responded to by this memory
system.physmem.num_writes::total 3201 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 297058 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 10847326 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 11144385 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 297058 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 297058 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1254463 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1254463 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1254463 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 297058 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 10847326 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12398848 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 28438 # Total number of read requests seen
system.physmem.writeReqs 3201 # Total number of write requests seen
system.physmem.cpureqs 31639 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 1819968 # Total number of bytes read from memory
system.physmem.bytesWritten 204864 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 1819968 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 204864 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 110 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 1839 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 1814 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 1804 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 1805 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 1784 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 1796 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 1898 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 1731 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 1725 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 1752 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 1846 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 1712 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 1666 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 1720 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 1759 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 1677 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 264 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 255 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 220 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 240 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 223 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 185 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 230 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 159 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 159 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 204 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 229 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 177 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 158 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 159 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 166 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 173 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 163308062000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 28438 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 3201 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 10296 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 6854 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 8194 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 743 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1313 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 615 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 66 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 94 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 83 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 70 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 93 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 96 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 105 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 126 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 47 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 35 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 1146806136 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 1807266136 # Sum of mem lat for all requests
system.physmem.totBusLat 113312000 # Total cycles spent in databus access
system.physmem.totBankLat 547148000 # Total cycles spent in bank access
system.physmem.avgQLat 40483.13 # Average queueing delay per request
system.physmem.avgBankLat 19314.74 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 63797.87 # Average memory access latency
system.physmem.avgRdBW 11.14 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 1.25 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 11.14 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 1.25 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.08 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
system.physmem.avgWrQLen 8.45 # Average write queue length over time
system.physmem.readRowHits 18527 # Number of row buffer hits during reads
system.physmem.writeRowHits 1851 # Number of row buffer hits during writes
system.physmem.readRowHitRate 65.40 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 57.83 # Row buffer hit rate for writes
system.physmem.avgGap 5161606.31 # Average gap between requests
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 48 # Number of system calls
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.numCycles 326616151 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.BPredUnit.lookups 85529383 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 80327419 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 2411594 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 47239817 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 46868068 # Number of BTB hits
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.BPredUnit.usedRAS 1438897 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 976 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 68850265 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 669456795 # Number of instructions fetch has processed
system.cpu.fetch.Branches 85529383 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 48306965 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 130031029 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 13412588 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 115987741 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 596 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 67404301 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 787271 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 325854018 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.189155 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.204154 # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.fetch.rateDist::0 195823205 60.10% 60.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 20926796 6.42% 66.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 4974411 1.53% 68.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 14401150 4.42% 72.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 8914958 2.74% 75.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 9439818 2.90% 78.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 4393851 1.35% 79.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 5794662 1.78% 81.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 61185167 18.78% 100.00% # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.fetch.rateDist::total 325854018 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.261865 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.049674 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 92909986 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 93274931 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 108737205 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 19949035 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 10982861 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 4721514 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 1634 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 705778363 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 5683 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 10982861 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 107200735 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 12803432 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 41316 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 114329497 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 80496177 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 697076108 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 75 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 59278982 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 18940548 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 607 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 723768936 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3240980671 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3240980543 # Number of integer rename lookups
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.rename.CommittedMaps 627419173 # Number of HB maps that are committed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.rename.UndoneMaps 96349763 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2017 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1967 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 169248841 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 172890049 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 80617622 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 21466789 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 27949042 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 681898631 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 3279 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 646738917 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 1408601 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 79369513 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 197745870 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 350 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 325854018 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.984750 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.743125 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.issued_per_cycle::0 67303060 20.65% 20.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 84497277 25.93% 46.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 74959252 23.00% 69.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 40290304 12.36% 81.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 28820123 8.84% 90.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 15118844 4.64% 95.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 5732215 1.76% 97.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 6879322 2.11% 99.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 2253621 0.69% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.issued_per_cycle::total 325854018 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.fu_full::IntAlu 205105 5.40% 5.40% # attempts to use FU when none available
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.iq.fu_full::IntMult 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.40% # attempts to use FU when none available
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.fu_full::MemRead 2822579 74.31% 79.71% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 770924 20.29% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.FU_type_0::IntAlu 403867506 62.45% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 6566 0.00% 62.45% # Type of FU issued
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.FU_type_0::MemRead 166069409 25.68% 88.13% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 76795433 11.87% 100.00% # Type of FU issued
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.FU_type_0::total 646738917 # Type of FU issued
system.cpu.iq.rate 1.980119 # Inst issue rate
system.cpu.iq.fu_busy_cnt 3798608 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.005873 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1624539025 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 761282766 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 638466372 # Number of integer instruction queue wakeup accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.int_alu_accesses 650537505 # Number of integer alu accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.lsq.thread0.forwLoads 30381283 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 23937231 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 124667 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 11589 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 10396384 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 12749 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 16530 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.iewSquashCycles 10982861 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 283658 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 42314 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 681905072 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 702708 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 172890049 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 80617622 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1929 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 10939 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 4841 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 11589 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 1389637 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 1521620 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 2911257 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 642548978 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 163933240 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 4189939 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.exec_nop 3162 # number of nop insts executed
system.cpu.iew.exec_refs 239931847 # number of memory reference insts executed
system.cpu.iew.exec_branches 74717690 # Number of branches executed
system.cpu.iew.exec_stores 75998607 # Number of stores executed
system.cpu.iew.exec_rate 1.967291 # Inst execution rate
system.cpu.iew.wb_sent 639936452 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 638466388 # cumulative count of insts written-back
system.cpu.iew.wb_producers 420738662 # num instructions producing a value
system.cpu.iew.wb_consumers 656063471 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.wb_rate 1.954791 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.641308 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.commitSquashedInsts 79553511 # The number of squashed insts skipped by commit
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.commit.commitNonSpecStalls 2929 # The number of times commit has been forced to stall to communicate backwards
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.branchMispredicts 2410069 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 314871158 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.913040 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.240132 # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.committed_per_cycle::0 91119458 28.94% 28.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 103740730 32.95% 61.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 42921464 13.63% 75.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 8973909 2.85% 78.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 25553482 8.12% 86.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 13492783 4.29% 90.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 7636973 2.43% 93.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1102971 0.35% 93.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 20329388 6.46% 100.00% # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.committed_per_cycle::total 314871158 # Number of insts commited each cycle
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.commit.committedInsts 570052761 # Number of instructions committed
system.cpu.commit.committedOps 602360967 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.commit.refs 219174056 # Number of memory references committed
system.cpu.commit.loads 148952818 # Number of loads committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.membars 1328 # Number of memory barriers committed
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.commit.branches 70892749 # Number of branches committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.commit.int_insts 533523531 # Number of committed integer instructions.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.function_calls 997573 # Number of function calls committed.
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.bw_lim_events 20329388 # number cycles where commit BW limit reached
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.rob.rob_reads 976455636 # The number of ROB reads
system.cpu.rob.rob_writes 1374843243 # The number of ROB writes
system.cpu.timesIdled 13781 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 762133 # Total number of cycles that the CPU has spent unscheduled due to idling
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.committedInsts 570052710 # Number of Instructions Simulated
system.cpu.committedOps 602360916 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 570052710 # Number of Instructions Simulated
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.cpi 0.572958 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.572958 # CPI: Total CPI of All Threads
system.cpu.ipc 1.745329 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.745329 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3209817028 # number of integer regfile reads
system.cpu.int_regfile_writes 664078534 # number of integer regfile writes
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.misc_regfile_reads 904771120 # number of misc regfile reads
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.misc_regfile_writes 3106 # number of misc regfile writes
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.icache.replacements 68 # number of replacements
system.cpu.icache.tagsinuse 692.511005 # Cycle average of tags in use
system.cpu.icache.total_refs 67403190 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 831 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 81110.938628 # Average number of references to valid blocks.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.icache.occ_blocks::cpu.inst 692.511005 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.338140 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.338140 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 67403190 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 67403190 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 67403190 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 67403190 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 67403190 # number of overall hits
system.cpu.icache.overall_hits::total 67403190 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1111 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1111 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1111 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1111 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1111 # number of overall misses
system.cpu.icache.overall_misses::total 1111 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 39508000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 39508000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 39508000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 39508000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 39508000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 39508000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 67404301 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 67404301 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 67404301 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 67404301 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 67404301 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 67404301 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35560.756076 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 35560.756076 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 35560.756076 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 35560.756076 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 35560.756076 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 35560.756076 # average overall miss latency
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 280 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 280 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 280 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 280 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 280 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 831 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 831 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 831 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 831 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 831 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 831 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29618500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 29618500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29618500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 29618500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29618500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 29618500 # number of overall MSHR miss cycles
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35641.997593 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35641.997593 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35641.997593 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 35641.997593 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35641.997593 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 35641.997593 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.replacements 440563 # number of replacements
system.cpu.dcache.tagsinuse 4092.333527 # Cycle average of tags in use
system.cpu.dcache.total_refs 200225147 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 444659 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 450.289204 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 278327000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4092.333527 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999105 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999105 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 132095464 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 132095464 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 68126436 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 68126436 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1695 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 1695 # number of LoadLockedReq hits
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.StoreCondReq_hits::cpu.data 1552 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1552 # number of StoreCondReq hits
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.demand_hits::cpu.data 200221900 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 200221900 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 200221900 # number of overall hits
system.cpu.dcache.overall_hits::total 200221900 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 216514 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 216514 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1291095 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1291095 # number of WriteReq misses
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
system.cpu.dcache.LoadLockedReq_misses::cpu.data 22 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 22 # number of LoadLockedReq misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.demand_misses::cpu.data 1507609 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1507609 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1507609 # number of overall misses
system.cpu.dcache.overall_misses::total 1507609 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2275129000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2275129000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 13136790063 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 13136790063 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 217000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 217000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 15411919063 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 15411919063 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 15411919063 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 15411919063 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 132311978 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 132311978 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1717 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1717 # number of LoadLockedReq accesses(hits+misses)
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1552 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1552 # number of StoreCondReq accesses(hits+misses)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.demand_accesses::cpu.data 201729509 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 201729509 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 201729509 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 201729509 # number of overall (read+write) accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001636 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.001636 # miss rate for ReadReq accesses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018599 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.018599 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012813 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012813 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.007473 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.007473 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.007473 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.007473 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10507.999483 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 10507.999483 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10174.921337 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 10174.921337 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9863.636364 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9863.636364 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 10222.756075 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 10222.756075 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 10222.756075 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 10222.756075 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 57181 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 3033 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.852951 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.writebacks::writebacks 421155 # number of writebacks
system.cpu.dcache.writebacks::total 421155 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 18984 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 18984 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1043965 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1043965 # number of WriteReq MSHR hits
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.demand_mshr_hits::cpu.data 1062949 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1062949 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1062949 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1062949 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197530 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 197530 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247130 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 247130 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 444660 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 444660 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 444660 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 444660 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1126335500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1126335500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1838542063 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1838542063 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2964877563 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 2964877563 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2964877563 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 2964877563 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001493 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001493 # mshr miss rate for ReadReq accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002204 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002204 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002204 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002204 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 5702.098415 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 5702.098415 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7439.574568 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7439.574568 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 6667.740663 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 6667.740663 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 6667.740663 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 6667.740663 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.replacements 4260 # number of replacements
system.cpu.l2cache.tagsinuse 21882.249420 # Cycle average of tags in use
system.cpu.l2cache.total_refs 505380 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 25296 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 19.978653 # Average number of references to valid blocks.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.occ_blocks::writebacks 20736.940727 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 179.307999 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 966.000694 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.632841 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.005472 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.029480 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.667793 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 69 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 192020 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 192089 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 421155 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 421155 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 224950 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 224950 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 69 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 416970 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 417039 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 69 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 416970 # number of overall hits
system.cpu.l2cache.overall_hits::total 417039 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 762 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 5510 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 6272 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 22180 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 22180 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 762 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 27690 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 28452 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 762 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 27690 # number of overall misses
system.cpu.l2cache.overall_misses::total 28452 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 28687000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 722594500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 751281500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1350770000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1350770000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 28687000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 2073364500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 2102051500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 28687000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 2073364500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 2102051500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 831 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 197530 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 198361 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 421155 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 421155 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247130 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 247130 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 831 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 444660 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 445491 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 831 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 444660 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 445491 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.916968 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.027894 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.031619 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089750 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.089750 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.916968 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.062272 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.063867 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.916968 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.062272 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.063867 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 37646.981627 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 131142.377495 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 119783.402423 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60900.360685 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60900.360685 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 37646.981627 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74877.735645 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 73880.623506 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 37646.981627 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74877.735645 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 73880.623506 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 28123 # number of cycles access was blocked
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.blocked::no_mshrs 2973 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 9.459469 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.writebacks::writebacks 3201 # number of writebacks
system.cpu.l2cache.writebacks::total 3201 # number of writebacks
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 758 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 5500 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 6258 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 22180 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 22180 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 758 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 27680 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 28438 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 758 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 27680 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 28438 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25719146 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 701873552 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 727592698 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1275833198 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1275833198 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25719146 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1977706750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 2003425896 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25719146 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1977706750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 2003425896 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.912154 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.027844 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.031549 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089750 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089750 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.912154 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.062250 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.063835 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.912154 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.062250 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063835 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33930.271768 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 127613.373091 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 116266.011186 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57521.785302 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57521.785302 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33930.271768 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71448.943280 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70448.902736 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33930.271768 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71448.943280 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70448.902736 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink