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gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt

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Update ref stats. tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 23:47:43 +02:00
---------- Begin Simulation Statistics ----------
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
sim_seconds 1.959865 # Number of seconds simulated
sim_ticks 1959865139500 # Number of ticks simulated
final_tick 1959865139500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
host_inst_rate 1047911 # Simulator instruction rate (inst/s)
host_op_rate 1047910 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 33678986014 # Simulator tick rate (ticks/s)
host_mem_usage 308256 # Number of bytes of host memory used
host_seconds 58.19 # Real time elapsed on the host
sim_insts 60980539 # Number of instructions simulated
sim_ops 60980539 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 833408 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 24886848 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 31616 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 338688 # Number of bytes read from this memory
system.physmem.bytes_read::total 28741440 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 833408 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 31616 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7743232 # Number of bytes written to this memory
system.physmem.bytes_written::total 7743232 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 13022 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 388857 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 494 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 5292 # Number of read requests responded to by this memory
system.physmem.num_reads::total 449085 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 120988 # Number of write requests responded to by this memory
system.physmem.num_writes::total 120988 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 425237 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 12698245 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1352583 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 16132 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 172812 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14665009 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 425237 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 16132 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 441369 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3950900 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3950900 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3950900 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 425237 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 12698245 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1352583 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 16132 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 172812 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 18615909 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 449085 # Total number of read requests seen
system.physmem.writeReqs 120988 # Total number of write requests seen
system.physmem.cpureqs 577269 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 28741440 # Total number of bytes read from memory
system.physmem.bytesWritten 7743232 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 28741440 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 7743232 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 62 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 7195 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 28163 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 28468 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 28046 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 27665 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 27762 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 27794 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 28266 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 27878 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 28077 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 27763 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 27645 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 28133 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 28181 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 28495 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 28656 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 28031 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 7932 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 7895 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 7532 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 7157 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 7275 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 7314 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 7754 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 7257 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 7316 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 7137 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 7066 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 7523 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 7683 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 8132 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 8336 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 7679 # Track writes on a per bank basis
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry
system.physmem.totGap 1959858128500 # Total gap between requests
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.readPktSize::6 449085 # Categorize read packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.writePktSize::6 120988 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 408321 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 7066 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 5331 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3258 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3264 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 3003 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1531 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1505 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1476 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1451 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1408 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1429 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1415 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 2044 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 2352 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 2212 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 1198 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 461 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 203 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 95 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.wrQLenPdf::0 3817 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 3924 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 4968 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 5260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 5260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 5260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 5260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 5260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 5259 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 5260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 5260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 5260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 5260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 5260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 5260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 5260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 5260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 1444 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 1337 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 293 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 40092 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 909.867305 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 223.303664 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 2368.170282 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-67 14180 35.37% 35.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-131 6168 15.38% 50.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-195 3902 9.73% 60.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-259 2490 6.21% 66.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-323 1693 4.22% 70.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-387 1359 3.39% 74.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-451 1096 2.73% 77.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-515 872 2.17% 79.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-579 629 1.57% 80.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-643 634 1.58% 82.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-707 494 1.23% 83.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-771 427 1.07% 84.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-835 257 0.64% 85.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-899 230 0.57% 85.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-963 171 0.43% 86.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1027 248 0.62% 86.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1091 146 0.36% 87.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1155 121 0.30% 87.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1219 95 0.24% 87.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1283 102 0.25% 88.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1347 86 0.21% 88.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1411 112 0.28% 88.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1475 1028 2.56% 91.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1539 203 0.51% 91.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1603 118 0.29% 91.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1667 93 0.23% 92.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1731 68 0.17% 92.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1795 46 0.11% 92.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1859 38 0.09% 92.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1923 17 0.04% 92.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1987 17 0.04% 92.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2051 32 0.08% 92.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2115 19 0.05% 92.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2179 9 0.02% 92.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2243 6 0.01% 92.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2307 5 0.01% 92.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2371 9 0.02% 92.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2435 7 0.02% 92.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2563 3 0.01% 92.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2627 8 0.02% 92.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2691 5 0.01% 92.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2755 2 0.00% 92.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2819 4 0.01% 92.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2883 5 0.01% 92.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2947 3 0.01% 92.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3011 2 0.00% 92.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3075 1 0.00% 92.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3139 2 0.00% 92.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3203 2 0.00% 92.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3267 2 0.00% 92.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3331 3 0.01% 92.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3395 2 0.00% 92.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3459 2 0.00% 92.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3651 1 0.00% 92.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3779 1 0.00% 92.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3843 1 0.00% 92.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3971 2 0.00% 93.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4035 4 0.01% 93.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4099 2 0.00% 93.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4163 2 0.00% 93.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4227 3 0.01% 93.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4355 1 0.00% 93.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4419 1 0.00% 93.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4483 3 0.01% 93.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4547 1 0.00% 93.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4675 1 0.00% 93.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4739 1 0.00% 93.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4803 1 0.00% 93.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4867 1 0.00% 93.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4931 1 0.00% 93.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5379 1 0.00% 93.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5571 1 0.00% 93.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5763 2 0.00% 93.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6147 3 0.01% 93.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6403 1 0.00% 93.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6787 1 0.00% 93.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6851 1 0.00% 93.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7171 2 0.00% 93.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7235 1 0.00% 93.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7299 2 0.00% 93.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7363 1 0.00% 93.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7555 1 0.00% 93.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7619 2 0.00% 93.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7683 2 0.00% 93.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7747 1 0.00% 93.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7811 1 0.00% 93.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7939 2 0.00% 93.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8003 3 0.01% 93.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8131 6 0.01% 93.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8195 2435 6.07% 99.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15872-15875 1 0.00% 99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16387 243 0.61% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16448-16451 6 0.01% 99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16512-16515 10 0.02% 99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16576-16579 4 0.01% 99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16704-16707 2 0.00% 99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16896-16899 2 0.00% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17024-17027 4 0.01% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17088-17091 1 0.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17152-17155 1 0.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 40092 # Bytes accessed per row activation
system.physmem.totQLat 3740449750 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 12011516000 # Sum of mem lat for all requests
system.physmem.totBusLat 2245115000 # Total cycles spent in databus access
system.physmem.totBankLat 6025951250 # Total cycles spent in bank access
system.physmem.avgQLat 8330.20 # Average queueing delay per request
system.physmem.avgBankLat 13420.14 # Average bank access latency per request
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per request
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.avgMemAccLat 26750.34 # Average memory access latency
system.physmem.avgRdBW 14.67 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 14.67 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 3.95 # Average consumed write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.15 # Data bus utilization in percentage
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgRdQLen 0.01 # Average read queue length over time
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.avgWrQLen 10.21 # Average write queue length over time
system.physmem.readRowHits 433314 # Number of row buffer hits during reads
system.physmem.writeRowHits 96597 # Number of row buffer hits during writes
system.physmem.readRowHitRate 96.50 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 79.84 # Row buffer hit rate for writes
system.physmem.avgGap 3437907.30 # Average gap between requests
system.membus.throughput 18676649 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 292796 # Transaction distribution
system.membus.trans_dist::ReadResp 292796 # Transaction distribution
system.membus.trans_dist::WriteReq 14151 # Transaction distribution
system.membus.trans_dist::WriteResp 14151 # Transaction distribution
system.membus.trans_dist::Writeback 120988 # Transaction distribution
system.membus.trans_dist::UpgradeReq 16779 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 11846 # Transaction distribution
system.membus.trans_dist::UpgradeResp 7198 # Transaction distribution
system.membus.trans_dist::ReadExReq 164928 # Transaction distribution
system.membus.trans_dist::ReadExResp 164057 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42700 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 931752 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 974452 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.bridge.slave 42700 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.physmem.port 1056418 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1099118 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 82626 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31176512 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 31259138 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308160 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 5308160 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.bridge.slave 82626 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.physmem.port 36484672 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 36567298 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 36567298 # Total data (bytes)
system.membus.snoop_data_through_bus 36416 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 43346000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1579141500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 3832845053 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.respLayer2.occupancy 376210250 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.l2c.replacements 342163 # number of replacements
system.l2c.tagsinuse 65224.613124 # Cycle average of tags in use
system.l2c.total_refs 2440483 # Total number of references to valid blocks.
system.l2c.sampled_refs 407350 # Sample count of references to valid blocks.
system.l2c.avg_refs 5.991121 # Average number of references to valid blocks.
system.l2c.warmup_cycle 8355445750 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 55361.728852 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 4802.377103 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 4855.919486 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 161.173506 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 43.414178 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.844753 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.073278 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.074095 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.002459 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.000662 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.995249 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 678870 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 661225 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 323259 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 109447 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1772801 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 790404 # number of Writeback hits
system.l2c.Writeback_hits::total 790404 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 182 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 565 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 747 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 38 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 61 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 127727 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 43997 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 171724 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst 678870 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 788952 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 323259 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 153444 # number of demand (read+write) hits
system.l2c.demand_hits::total 1944525 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 678870 # number of overall hits
system.l2c.overall_hits::cpu0.data 788952 # number of overall hits
system.l2c.overall_hits::cpu1.inst 323259 # number of overall hits
system.l2c.overall_hits::cpu1.data 153444 # number of overall hits
system.l2c.overall_hits::total 1944525 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 13022 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 271666 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 505 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 241 # number of ReadReq misses
system.l2c.ReadReq_misses::total 285434 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 2971 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1796 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 4767 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 957 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 952 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1909 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 117966 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 5061 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 123027 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst 13022 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 389632 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 505 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 5302 # number of demand (read+write) misses
system.l2c.demand_misses::total 408461 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 13022 # number of overall misses
system.l2c.overall_misses::cpu0.data 389632 # number of overall misses
system.l2c.overall_misses::cpu1.inst 505 # number of overall misses
system.l2c.overall_misses::cpu1.data 5302 # number of overall misses
system.l2c.overall_misses::total 408461 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst 1040882000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 16855181499 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 39850000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 21000500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 17956913999 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 1322500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 10129500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 11452000 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 954000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 204000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 1158000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 7822362000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 373828000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 8196190000 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst 1040882000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 24677543499 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 39850000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 394828500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 26153103999 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst 1040882000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 24677543499 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 39850000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 394828500 # number of overall miss cycles
system.l2c.overall_miss_latency::total 26153103999 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst 691892 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 932891 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 323764 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 109688 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2058235 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 790404 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 790404 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 3153 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 2361 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 5514 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 995 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 975 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 1970 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 245693 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 49058 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 294751 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 691892 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 1178584 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 323764 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 158746 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2352986 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 691892 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 1178584 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 323764 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 158746 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2352986 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.018821 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.291209 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.001560 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.002197 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.138679 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942277 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.760695 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.864527 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.961809 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.976410 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.969036 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.480136 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.103164 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.417393 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.018821 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.330593 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.001560 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.033399 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.173593 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.018821 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.330593 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.001560 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.033399 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.173593 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 79932.575641 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 62043.765134 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78910.891089 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 87139.004149 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 62910.914604 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 445.136318 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5640.033408 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 2402.349486 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 996.865204 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 214.285714 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 606.600314 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 66310.309750 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73864.453665 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 66621.066920 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 79932.575641 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 63335.515304 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 78910.891089 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 74467.842324 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 64028.399282 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 79932.575641 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 63335.515304 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 78910.891089 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 74467.842324 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 64028.399282 # average overall miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.writebacks::writebacks 79468 # number of writebacks
system.l2c.writebacks::total 79468 # number of writebacks
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_misses::cpu0.inst 13022 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 271666 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 494 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 241 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 285423 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 2971 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1796 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 4767 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 957 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 952 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 1909 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 117966 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 5061 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 123027 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 13022 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 389632 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 494 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 5302 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 408450 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 13022 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 389632 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 494 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 5302 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 408450 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 877008002 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 13524537499 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 32847250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 18012000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 14452404751 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29895468 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 17998795 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 47894263 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 9591457 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 9520952 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 19112409 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6366934262 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 311018260 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 6677952522 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 877008002 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 19891471761 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 32847250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 329030260 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 21130357273 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 877008002 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 19891471761 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 32847250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 329030260 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 21130357273 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373163000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17611000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 1390774000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2158791500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 683644500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 2842436000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3531954500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 701255500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 4233210000 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018821 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.291209 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001526 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002197 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.138674 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942277 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.760695 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.864527 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.961809 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.976410 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969036 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.480136 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.103164 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.417393 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018821 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.330593 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001526 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.033399 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.173588 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018821 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.330593 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001526 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.033399 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.173588 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67348.180157 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 49783.695785 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66492.408907 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 74738.589212 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 50635.039051 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10062.426119 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10021.600780 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10047.044892 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10022.421108 # average SCUpgradeReq mshr miss latency
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10011.738607 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 53972.621450 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61453.914246 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 54280.381721 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67348.180157 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 51051.945839 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66492.408907 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62057.763108 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 51733.032863 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67348.180157 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 51051.945839 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66492.408907 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62057.763108 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 51733.032863 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.replacements 41694 # number of replacements
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iocache.tagsinuse 0.570240 # Cycle average of tags in use
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.iocache.total_refs 0 # Total number of references to valid blocks.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.sampled_refs 41710 # Sample count of references to valid blocks.
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.iocache.avg_refs 0 # Average number of references to valid blocks.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iocache.warmup_cycle 1753558786000 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide 0.570240 # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide 0.035640 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.035640 # Average percentage of cache occupancy
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses
system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses
system.iocache.overall_misses::total 41726 # number of overall misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iocache.ReadReq_miss_latency::tsunami.ide 21457883 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21457883 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide 10416109037 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 10416109037 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 10437566920 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 10437566920 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 10437566920 # number of overall miss cycles
system.iocache.overall_miss_latency::total 10437566920 # number of overall miss cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123321.166667 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 123321.166667 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 250676.478557 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 250676.478557 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 250145.399032 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 250145.399032 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 250145.399032 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 250145.399032 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 272227 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iocache.blocked::no_mshrs 27211 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 10.004300 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.iocache.writebacks::writebacks 41520 # number of writebacks
system.iocache.writebacks::total 41520 # number of writebacks
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12409133 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 12409133 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8254729537 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 8254729537 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 8267138670 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8267138670 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 8267138670 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8267138670 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71316.856322 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 71316.856322 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 198660.221818 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 198660.221818 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198129.192110 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 198129.192110 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198129.192110 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 198129.192110 # average overall mshr miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dtb.read_hits 7504093 # DTB read hits
system.cpu0.dtb.read_misses 7765 # DTB read misses
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu0.dtb.read_acv 210 # DTB read access violations
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dtb.read_accesses 524069 # DTB read accesses
system.cpu0.dtb.write_hits 5095666 # DTB write hits
system.cpu0.dtb.write_misses 910 # DTB write misses
system.cpu0.dtb.write_acv 133 # DTB write access violations
system.cpu0.dtb.write_accesses 202595 # DTB write accesses
system.cpu0.dtb.data_hits 12599759 # DTB hits
system.cpu0.dtb.data_misses 8675 # DTB misses
system.cpu0.dtb.data_acv 343 # DTB access violations
system.cpu0.dtb.data_accesses 726664 # DTB accesses
system.cpu0.itb.fetch_hits 3641096 # ITB hits
system.cpu0.itb.fetch_misses 3984 # ITB misses
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu0.itb.fetch_acv 184 # ITB acv
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.itb.fetch_accesses 3645080 # ITB accesses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.numCycles 3919730279 # number of cpu cycles simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.committedInsts 47851975 # Number of instructions committed
system.cpu0.committedOps 47851975 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 44398232 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 209056 # Number of float alu accesses
system.cpu0.num_func_calls 1198231 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 5625657 # number of instructions that are conditional controls
system.cpu0.num_int_insts 44398232 # number of integer instructions
system.cpu0.num_fp_insts 209056 # number of float instructions
system.cpu0.num_int_register_reads 61087554 # number of times the integer registers were read
system.cpu0.num_int_register_writes 33073995 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 102127 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 103890 # number of times the floating registers were written
system.cpu0.num_mem_refs 12640550 # number of memory refs
system.cpu0.num_load_insts 7531710 # Number of load instructions
system.cpu0.num_store_insts 5108840 # Number of store instructions
system.cpu0.num_idle_cycles 3699529015.998113 # Number of idle cycles
system.cpu0.num_busy_cycles 220201263.001888 # Number of busy cycles
system.cpu0.not_idle_fraction 0.056178 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.943822 # Percentage of idle cycles
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.kern.inst.quiesce 6830 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 164217 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 56358 40.22% 40.22% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 131 0.09% 40.31% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1973 1.41% 41.72% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30 445 0.32% 42.04% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31 81223 57.96% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 140130 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 55870 49.08% 49.08% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1973 1.73% 50.92% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30 445 0.39% 51.31% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 55425 48.69% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 113844 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1901694919500 97.03% 97.03% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 94927000 0.00% 97.04% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 766727000 0.04% 97.08% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30 329552000 0.02% 97.09% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 56978256500 2.91% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1959864382000 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.991341 # fraction of swpipl calls that actually changed the ipl
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.kern.ipl_used::31 0.682381 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total 0.812417 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed
system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed
system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed
system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed
system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed
system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed
system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed
system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed
system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed
system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed
system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed
system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed
system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed
system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed
system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed
system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed
system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed
system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed
system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed
system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed
system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed
system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed
system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed
system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed
system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed
system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed
system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 234 # number of syscalls executed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.kern.callpal::wripir 528 0.36% 0.36% # number of callpals executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed
system.cpu0.kern.callpal::swpctx 3061 2.06% 2.42% # number of callpals executed
system.cpu0.kern.callpal::tbi 51 0.03% 2.45% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.46% # number of callpals executed
system.cpu0.kern.callpal::swpipl 133182 89.70% 92.16% # number of callpals executed
system.cpu0.kern.callpal::rdps 6700 4.51% 96.67% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.67% # number of callpals executed
system.cpu0.kern.callpal::wrusp 4 0.00% 96.67% # number of callpals executed
system.cpu0.kern.callpal::rdusp 9 0.01% 96.68% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 96.68% # number of callpals executed
system.cpu0.kern.callpal::rti 4398 2.96% 99.64% # number of callpals executed
system.cpu0.kern.callpal::callsys 394 0.27% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed
system.cpu0.kern.callpal::total 148480 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 6996 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1373 # number of protection mode switches
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.kern.mode_good::kernel 1372
system.cpu0.kern.mode_good::user 1373
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.mode_good::idle 0
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.kern.mode_switch_good::kernel 0.196112 # fraction of useful protection mode switches
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.kern.mode_switch_good::total 0.327996 # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 1956039363000 99.80% 99.80% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 3825014500 0.20% 100.00% # number of ticks spent at the given mode
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.kern.swap_context 3062 # number of times the context was actually changed
Update ref stats. tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 23:47:43 +02:00
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
Update ref stats. tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 23:47:43 +02:00
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
Update ref stats. tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 23:47:43 +02:00
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
Update ref stats. tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 23:47:43 +02:00
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.throughput 103923821 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 2101274 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2101259 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 14151 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 14151 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 790404 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 17004 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 11907 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 28911 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 338243 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 296693 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1383805 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3109039 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 647529 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 472865 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count 5613238 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 44281088 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 118941040 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 20720896 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 17326866 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size 201269890 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 201259586 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 2417088 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 4784493652 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 3113609997 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 5406966495 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 1456953977 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 808879499 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.throughput 1400220 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 7373 # Transaction distribution
system.iobus.trans_dist::ReadResp 7373 # Transaction distribution
system.iobus.trans_dist::WriteReq 55703 # Transaction distribution
system.iobus.trans_dist::WriteResp 55703 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14090 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 42700 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.cchip.pio 14090 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 126152 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 56360 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 82626 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.cchip.pio 56360 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 2744242 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 2744242 # Total data (bytes)
system.iobus.reqLayer0.occupancy 13445000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer29.occupancy 378246920 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 28549000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 42012000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.icache.replacements 691283 # number of replacements
system.cpu0.icache.tagsinuse 508.523038 # Cycle average of tags in use
system.cpu0.icache.total_refs 47169081 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 691795 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 68.183611 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 38900732000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 508.523038 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.993209 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.993209 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 47169081 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 47169081 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 47169081 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 47169081 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 47169081 # number of overall hits
system.cpu0.icache.overall_hits::total 47169081 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 691913 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 691913 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 691913 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 691913 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 691913 # number of overall misses
system.cpu0.icache.overall_misses::total 691913 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9946018500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 9946018500 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 9946018500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 9946018500 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 9946018500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 9946018500 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 47860994 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 47860994 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 47860994 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 47860994 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 47860994 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 47860994 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014457 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.014457 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014457 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.014457 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014457 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.014457 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14374.666324 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14374.666324 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14374.666324 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14374.666324 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14374.666324 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14374.666324 # average overall miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 691913 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 691913 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 691913 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 691913 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 691913 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 691913 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8562191003 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 8562191003 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8562191003 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 8562191003 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8562191003 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 8562191003 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014457 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014457 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014457 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.014457 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014457 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.014457 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12374.664160 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12374.664160 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12374.664160 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12374.664160 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12374.664160 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12374.664160 # average overall mshr miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.replacements 1181525 # number of replacements
system.cpu0.dcache.tagsinuse 505.231432 # Cycle average of tags in use
system.cpu0.dcache.total_refs 11411955 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 1182037 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 9.654482 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 105721000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 505.231432 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.986780 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.986780 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 6427043 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 6427043 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 4684362 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 4684362 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139576 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 139576 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 146814 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 146814 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 11111405 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 11111405 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 11111405 # number of overall hits
system.cpu0.dcache.overall_hits::total 11111405 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 936498 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 936498 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 255602 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 255602 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13508 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 13508 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5738 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 5738 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 1192100 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1192100 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1192100 # number of overall misses
system.cpu0.dcache.overall_misses::total 1192100 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26205591500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 26205591500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9945079500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 9945079500 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 146904500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 146904500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44028500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 44028500 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 36150671000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 36150671000 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 36150671000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 36150671000 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7363541 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 7363541 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4939964 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 4939964 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 153084 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 153084 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 152552 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 152552 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 12303505 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 12303505 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 12303505 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 12303505 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127180 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.127180 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051742 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.051742 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088239 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088239 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037613 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037613 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096891 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.096891 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096891 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.096891 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27982.538671 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 27982.538671 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38908.457289 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 38908.457289 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10875.370151 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10875.370151 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7673.143953 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7673.143953 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30325.200067 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 30325.200067 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30325.200067 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 30325.200067 # average overall miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.writebacks::writebacks 678820 # number of writebacks
system.cpu0.dcache.writebacks::total 678820 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 936498 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 936498 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 255602 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 255602 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13508 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13508 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5737 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 5737 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 1192100 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 1192100 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 1192100 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 1192100 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24332593005 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24332593005 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9433875500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9433875500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 119888500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 119888500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32554500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32554500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 33766468505 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 33766468505 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 33766468505 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 33766468505 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465600500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465600500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2289389000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2289389000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3754989500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3754989500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127180 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127180 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051742 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051742 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088239 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088239 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037607 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037607 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096891 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.096891 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096891 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.096891 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25982.536006 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25982.536006 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36908.457289 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36908.457289 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8875.370151 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8875.370151 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5674.481436 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5674.481436 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28325.197974 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28325.197974 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28325.197974 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28325.197974 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dtb.read_hits 2417907 # DTB read hits
system.cpu1.dtb.read_misses 2620 # DTB read misses
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu1.dtb.read_acv 0 # DTB read access violations
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dtb.read_accesses 205337 # DTB read accesses
system.cpu1.dtb.write_hits 1735068 # DTB write hits
system.cpu1.dtb.write_misses 235 # DTB write misses
system.cpu1.dtb.write_acv 24 # DTB write access violations
system.cpu1.dtb.write_accesses 89739 # DTB write accesses
system.cpu1.dtb.data_hits 4152975 # DTB hits
system.cpu1.dtb.data_misses 2855 # DTB misses
system.cpu1.dtb.data_acv 24 # DTB access violations
system.cpu1.dtb.data_accesses 295076 # DTB accesses
system.cpu1.itb.fetch_hits 1826925 # ITB hits
system.cpu1.itb.fetch_misses 1064 # ITB misses
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu1.itb.fetch_acv 0 # ITB acv
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.itb.fetch_accesses 1827989 # ITB accesses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.numCycles 3917974909 # number of cpu cycles simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.committedInsts 13128564 # Number of instructions committed
system.cpu1.committedOps 13128564 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 12090481 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 177902 # Number of float alu accesses
system.cpu1.num_func_calls 416956 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 1297332 # number of instructions that are conditional controls
system.cpu1.num_int_insts 12090481 # number of integer instructions
system.cpu1.num_fp_insts 177902 # number of float instructions
system.cpu1.num_int_register_reads 16603924 # number of times the integer registers were read
system.cpu1.num_int_register_writes 8888139 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 92328 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 94344 # number of times the floating registers were written
system.cpu1.num_mem_refs 4176284 # number of memory refs
system.cpu1.num_load_insts 2431879 # Number of load instructions
system.cpu1.num_store_insts 1744405 # Number of store instructions
system.cpu1.num_idle_cycles 3867819461.141509 # Number of idle cycles
system.cpu1.num_busy_cycles 50155447.858491 # Number of busy cycles
system.cpu1.not_idle_fraction 0.012801 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.987199 # Percentage of idle cycles
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.kern.inst.quiesce 2741 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 79425 # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0 27091 38.34% 38.34% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22 1969 2.79% 41.13% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30 528 0.75% 41.87% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31 41074 58.13% 100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total 70662 # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0 26202 48.19% 48.19% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22 1969 3.62% 51.81% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30 528 0.97% 52.78% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31 25675 47.22% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total 54374 # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0 1908747944000 97.44% 97.44% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22 700841000 0.04% 97.47% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30 369371500 0.02% 97.49% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31 49169268000 2.51% 100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total 1958987424500 # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0 0.967185 # fraction of swpipl calls that actually changed the ipl
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.kern.ipl_used::31 0.625091 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total 0.769494 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed
system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed
system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed
system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed
system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed
system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed
system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed
system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed
system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed
system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed
system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed
system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed
system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 92 # number of syscalls executed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.kern.callpal::wripir 445 0.61% 0.61% # number of callpals executed
system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed
system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed
system.cpu1.kern.callpal::swpctx 2045 2.80% 3.42% # number of callpals executed
system.cpu1.kern.callpal::tbi 3 0.00% 3.42% # number of callpals executed
system.cpu1.kern.callpal::wrent 7 0.01% 3.43% # number of callpals executed
system.cpu1.kern.callpal::swpipl 64414 88.26% 91.69% # number of callpals executed
system.cpu1.kern.callpal::rdps 2145 2.94% 94.63% # number of callpals executed
system.cpu1.kern.callpal::wrkgp 1 0.00% 94.63% # number of callpals executed
system.cpu1.kern.callpal::wrusp 3 0.00% 94.63% # number of callpals executed
system.cpu1.kern.callpal::whami 3 0.00% 94.64% # number of callpals executed
system.cpu1.kern.callpal::rti 3751 5.14% 99.78% # number of callpals executed
system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed
system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.kern.callpal::total 72984 # number of callpals executed
system.cpu1.kern.mode_switch::kernel 1994 # number of protection mode switches
system.cpu1.kern.mode_switch::user 369 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 2923 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 821
system.cpu1.kern.mode_good::user 369
system.cpu1.kern.mode_good::idle 452
system.cpu1.kern.mode_switch_good::kernel 0.411735 # fraction of useful protection mode switches
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.kern.mode_switch_good::idle 0.154636 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total 0.310632 # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 18283551000 0.93% 0.93% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 1485621000 0.08% 1.01% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 1938326244500 98.99% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context 2046 # number of times the context was actually changed
system.cpu1.icache.replacements 323214 # number of replacements
system.cpu1.icache.tagsinuse 446.824291 # Cycle average of tags in use
system.cpu1.icache.total_refs 12807678 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 323725 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 39.563450 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 1958057375000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst 446.824291 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.872704 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.872704 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 12807678 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 12807678 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 12807678 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 12807678 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 12807678 # number of overall hits
system.cpu1.icache.overall_hits::total 12807678 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 323765 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 323765 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 323765 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 323765 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 323765 # number of overall misses
system.cpu1.icache.overall_misses::total 323765 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4261948000 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 4261948000 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 4261948000 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 4261948000 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 4261948000 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 4261948000 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 13131443 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 13131443 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 13131443 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 13131443 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 13131443 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 13131443 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024656 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.024656 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024656 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.024656 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024656 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.024656 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13163.708245 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13163.708245 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13163.708245 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13163.708245 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13163.708245 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13163.708245 # average overall miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 323765 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 323765 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 323765 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 323765 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 323765 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 323765 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3614406523 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 3614406523 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3614406523 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 3614406523 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3614406523 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 3614406523 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024656 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024656 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024656 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.024656 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024656 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.024656 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11163.672797 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11163.672797 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11163.672797 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11163.672797 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11163.672797 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11163.672797 # average overall mshr miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dcache.replacements 161925 # number of replacements
system.cpu1.dcache.tagsinuse 486.809606 # Cycle average of tags in use
system.cpu1.dcache.total_refs 3976206 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 162254 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 24.506058 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 70872567000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data 486.809606 # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data 0.950800 # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total 0.950800 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 2251927 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 2251927 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 1621193 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 1621193 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 49026 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 49026 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 51669 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 51669 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 3873120 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 3873120 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 3873120 # number of overall hits
system.cpu1.dcache.overall_hits::total 3873120 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 118911 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 118911 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 58093 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 58093 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9306 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 9306 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6171 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 6171 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 177004 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 177004 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 177004 # number of overall misses
system.cpu1.dcache.overall_misses::total 177004 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1440878500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 1440878500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1041850000 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 1041850000 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84410500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 84410500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 44897500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 44897500 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 2482728500 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 2482728500 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 2482728500 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 2482728500 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 2370838 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 2370838 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 1679286 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 1679286 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 58332 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 58332 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 57840 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 57840 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 4050124 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 4050124 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 4050124 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 4050124 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050156 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.050156 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034594 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.034594 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.159535 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.159535 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106691 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106691 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043703 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.043703 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043703 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.043703 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12117.285196 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12117.285196 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17934.174513 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 17934.174513 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9070.545884 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9070.545884 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7275.563118 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7275.563118 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14026.397709 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 14026.397709 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14026.397709 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 14026.397709 # average overall miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dcache.writebacks::writebacks 111584 # number of writebacks
system.cpu1.dcache.writebacks::total 111584 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118911 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 118911 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58093 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 58093 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9306 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9306 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6171 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 6171 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 177004 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 177004 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 177004 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 177004 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1203056001 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1203056001 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 925664000 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 925664000 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 65798500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 65798500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32557500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32557500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2128720001 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 2128720001 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2128720001 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 2128720001 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18768000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18768000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 722866000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 722866000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 741634000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 741634000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050156 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050156 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034594 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034594 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.159535 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.159535 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106691 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106691 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043703 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.043703 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043703 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.043703 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10117.281000 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10117.281000 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15934.174513 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15934.174513 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7070.545884 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7070.545884 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5275.887214 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5275.887214 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12026.394889 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12026.394889 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12026.394889 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12026.394889 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
Update ref stats. tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 23:47:43 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink