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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt

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arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
sim_seconds 51.318151 # Number of seconds simulated
sim_ticks 51318151431000 # Number of ticks simulated
final_tick 51318151431000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
host_inst_rate 262276 # Simulator instruction rate (inst/s)
host_op_rate 308198 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 15864240835 # Simulator tick rate (ticks/s)
host_mem_usage 687920 # Number of bytes of host memory used
host_seconds 3234.83 # Real time elapsed on the host
sim_insts 848418690 # Number of instructions simulated
sim_ops 996969189 # Number of ops (including micro ops) simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.physmem.bytes_read::cpu0.dtb.walker 76672 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 79744 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 2462068 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 43565640 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 25536 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 20992 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 433216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 6171840 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker 28864 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.itb.walker 29440 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 1450304 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 8009024 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.dtb.walker 65344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.itb.walker 58432 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst 1793920 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 14730432 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 421568 # Number of bytes read from this memory
system.physmem.bytes_read::total 79423036 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 2462068 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 433216 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 1450304 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst 1793920 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 6139508 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 67636992 # Number of bytes written to this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.physmem.bytes_written::total 67657572 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 1198 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1246 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 78877 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 680726 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 399 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 328 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 6769 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 96435 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker 451 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.itb.walker 460 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 22661 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 125141 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.dtb.walker 1021 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.itb.walker 913 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst 28030 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 230163 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6587 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1281405 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1056828 # Number of write requests responded to by this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.physmem.num_writes::total 1059401 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 1494 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 1554 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 47977 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 848932 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 498 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 409 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 8442 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 120266 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker 562 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.itb.walker 574 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 28261 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 156066 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.dtb.walker 1273 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.itb.walker 1139 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst 34957 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data 287041 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8215 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1547660 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 47977 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 8442 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 28261 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst 34957 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 119636 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1317994 # Write bandwidth from this memory (bytes/s)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.physmem.bw_write::total 1318395 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1317994 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 1494 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 1554 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 47977 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 849333 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 498 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 409 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 8442 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 120266 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker 562 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.itb.walker 574 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 28261 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 156066 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.dtb.walker 1273 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.itb.walker 1139 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst 34957 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 287041 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8215 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2866054 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 517103 # Number of read requests accepted
system.physmem.writeReqs 450227 # Number of write requests accepted
system.physmem.readBursts 517103 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 450227 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 33073280 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 21312 # Total number of bytes read from write queue
system.physmem.bytesWritten 28812544 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 33094592 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 28814528 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 333 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 174284 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 32820 # Per bank write bursts
system.physmem.perBankRdBursts::1 35061 # Per bank write bursts
system.physmem.perBankRdBursts::2 31334 # Per bank write bursts
system.physmem.perBankRdBursts::3 30738 # Per bank write bursts
system.physmem.perBankRdBursts::4 32772 # Per bank write bursts
system.physmem.perBankRdBursts::5 36727 # Per bank write bursts
system.physmem.perBankRdBursts::6 31736 # Per bank write bursts
system.physmem.perBankRdBursts::7 32381 # Per bank write bursts
system.physmem.perBankRdBursts::8 29681 # Per bank write bursts
system.physmem.perBankRdBursts::9 35684 # Per bank write bursts
system.physmem.perBankRdBursts::10 31546 # Per bank write bursts
system.physmem.perBankRdBursts::11 32698 # Per bank write bursts
system.physmem.perBankRdBursts::12 33025 # Per bank write bursts
system.physmem.perBankRdBursts::13 31465 # Per bank write bursts
system.physmem.perBankRdBursts::14 29673 # Per bank write bursts
system.physmem.perBankRdBursts::15 29429 # Per bank write bursts
system.physmem.perBankWrBursts::0 27864 # Per bank write bursts
system.physmem.perBankWrBursts::1 28674 # Per bank write bursts
system.physmem.perBankWrBursts::2 26960 # Per bank write bursts
system.physmem.perBankWrBursts::3 27504 # Per bank write bursts
system.physmem.perBankWrBursts::4 29012 # Per bank write bursts
system.physmem.perBankWrBursts::5 31175 # Per bank write bursts
system.physmem.perBankWrBursts::6 28381 # Per bank write bursts
system.physmem.perBankWrBursts::7 29346 # Per bank write bursts
system.physmem.perBankWrBursts::8 26700 # Per bank write bursts
system.physmem.perBankWrBursts::9 31017 # Per bank write bursts
system.physmem.perBankWrBursts::10 26800 # Per bank write bursts
system.physmem.perBankWrBursts::11 28289 # Per bank write bursts
system.physmem.perBankWrBursts::12 28254 # Per bank write bursts
system.physmem.perBankWrBursts::13 27295 # Per bank write bursts
system.physmem.perBankWrBursts::14 26424 # Per bank write bursts
system.physmem.perBankWrBursts::15 26501 # Per bank write bursts
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.physmem.numWrRetry 4 # Number of times write queue was full causing retry
system.physmem.totGap 51317151101500 # Total gap between requests
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.physmem.readPktSize::6 517103 # Read request sizes (log2)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.physmem.writePktSize::6 450227 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 365842 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 95262 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 32310 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 19750 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 435 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 384 # What read queue length does an incoming req see
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.physmem.rdQLenPdf::6 374 # What read queue length does an incoming req see
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.physmem.rdQLenPdf::7 741 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 491 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 222 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 244 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 118 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 108 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 92 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 83 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 80 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 73 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 66 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 51 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 38 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.physmem.wrQLenPdf::0 600 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 593 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 586 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 582 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 578 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 573 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 569 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 566 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 566 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 566 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 565 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 560 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 556 # What write queue length does an incoming req see
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.physmem.wrQLenPdf::13 551 # What write queue length does an incoming req see
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.physmem.wrQLenPdf::14 550 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 7435 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 8261 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 18409 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 21789 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 24777 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 26143 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 27073 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 27056 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 27725 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 27794 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 27996 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 30008 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 27705 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 27676 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 29590 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 26243 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 26383 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 25171 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 575 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 403 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 250 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 234 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 253 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 241 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 181 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 176 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 170 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 132 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 176 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 142 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 122 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 173 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 128 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 163 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 128 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 102 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 80 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 59 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 21 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 19 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 260816 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 237.276486 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 143.923814 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 277.776542 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 119999 46.01% 46.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 65306 25.04% 71.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 23923 9.17% 80.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 11962 4.59% 84.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 8906 3.41% 88.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 5685 2.18% 90.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 4538 1.74% 92.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 3514 1.35% 93.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 16983 6.51% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 260816 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 25134 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 20.558447 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 13.007693 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-31 22781 90.64% 90.64% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::32-63 2174 8.65% 99.29% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::64-95 141 0.56% 99.85% # Reads before turning the bus around for writes
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.physmem.rdPerTurnAround::96-127 17 0.07% 99.92% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::128-159 6 0.02% 99.94% # Reads before turning the bus around for writes
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.physmem.rdPerTurnAround::192-223 6 0.02% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::224-255 3 0.01% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::256-287 1 0.00% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::320-351 2 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::576-607 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::608-639 1 0.00% 100.00% # Reads before turning the bus around for writes
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.physmem.rdPerTurnAround::672-703 1 0.00% 100.00% # Reads before turning the bus around for writes
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.physmem.rdPerTurnAround::total 25134 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 25134 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.911833 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.251303 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 7.505158 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 24 0.10% 0.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 17 0.07% 0.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11 14 0.06% 0.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15 60 0.24% 0.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 23322 92.79% 93.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 527 2.10% 95.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 146 0.58% 95.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 283 1.13% 97.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 54 0.21% 97.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 168 0.67% 97.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 80 0.32% 98.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 22 0.09% 98.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 25 0.10% 98.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 58 0.23% 98.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 20 0.08% 98.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 9 0.04% 98.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 213 0.85% 99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 11 0.04% 99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 9 0.04% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 35 0.14% 99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 6 0.02% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 2 0.01% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 2 0.01% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 3 0.01% 99.90% # Writes before turning the bus around for reads
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.physmem.wrPerTurnAround::108-111 1 0.00% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 14 0.06% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 2 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 2 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 25134 # Writes before turning the bus around for reads
system.physmem.totQLat 10819472737 # Total ticks spent queuing
system.physmem.totMemAccLat 20508910237 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2583850000 # Total ticks spent in databus transfers
system.physmem.avgQLat 20936.73 # Average queueing delay per DRAM burst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.physmem.avgMemAccLat 39686.73 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 0.64 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.56 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 0.64 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.56 # Average system write bandwidth in MiByte/s
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.physmem.busUtil 0.01 # Data bus utilization in percentage
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.physmem.avgWrQLen 13.27 # Average write queue length when enqueuing
system.physmem.readRowHits 394016 # Number of row buffer hits during reads
system.physmem.writeRowHits 312132 # Number of row buffer hits during writes
system.physmem.readRowHitRate 76.25 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 69.33 # Row buffer hit rate for writes
system.physmem.avgGap 53050304.55 # Average gap between requests
system.physmem.pageHitRate 73.02 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 1012329360 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 550658625 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 2055807000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 1483375680 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3312957669840 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1179842633775 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 29693796398250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 34191698872530 # Total energy per rank (pJ)
system.physmem_0.averagePower 667.616546 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 48906772559460 # Time in different power states
system.physmem_0.memoryStateTime::REF 1693741140000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.physmem_0.memoryStateTime::ACT 122637370540 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.physmem_1.actEnergy 959439600 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 521932125 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1974960000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 1433894400 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3312957669840 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1178190529245 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 30742990092750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 35239028517960 # Total energy per rank (pJ)
system.physmem_1.averagePower 665.379239 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 48909312036157 # Time in different power states
system.physmem_1.memoryStateTime::REF 1693741140000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.physmem_1.memoryStateTime::ACT 120107401343 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.realview.nvmem.bytes_read::cpu2.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 196 # Number of bytes read from this memory
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.realview.nvmem.bytes_inst_read::cpu2.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.realview.nvmem.num_reads::cpu2.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.realview.nvmem.bw_read::cpu2.inst 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.realview.nvmem.bw_inst_read::cpu2.inst 1 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.realview.nvmem.bw_total::cpu2.inst 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.walker.walks 90147 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 90147 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walkWaitTime::samples 90147 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 90147 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 90147 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples 390083894328 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 1.522589 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 -203853691422 -52.26% -52.26% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1 593937585750 152.26% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 390083894328 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 65853 84.82% 84.82% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 11789 15.18% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 77642 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 90147 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 90147 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 77642 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 77642 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 167789 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.read_hits 64842340 # DTB read hits
system.cpu0.dtb.read_misses 68503 # DTB read misses
system.cpu0.dtb.write_hits 59153195 # DTB write hits
system.cpu0.dtb.write_misses 21644 # DTB write misses
system.cpu0.dtb.flush_tlb 1197 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.flush_tlb_mva_asid 16138 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 390 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 41112 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.prefetch_faults 2836 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.perms_faults 7541 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 64910843 # DTB read accesses
system.cpu0.dtb.write_accesses 59174839 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.hits 123995535 # DTB hits
system.cpu0.dtb.misses 90147 # DTB misses
system.cpu0.dtb.accesses 124085682 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.itb.walker.walks 53264 # Table walker walks requested
system.cpu0.itb.walker.walksLong 53264 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walkWaitTime::samples 53264 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 53264 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 53264 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples 390083894328 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 1.522690 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 -203892956422 -52.27% -52.27% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 593976850750 152.27% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 390083894328 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 46252 94.85% 94.85% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 2512 5.15% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 48764 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53264 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53264 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 48764 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 48764 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 102028 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 346149733 # ITB inst hits
system.cpu0.itb.inst_misses 53264 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.itb.flush_tlb 1197 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.itb.flush_tlb_mva_asid 16138 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 390 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 28909 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.itb.inst_accesses 346202997 # ITB inst accesses
system.cpu0.itb.hits 346149733 # DTB hits
system.cpu0.itb.misses 53264 # DTB misses
system.cpu0.itb.accesses 346202997 # DTB accesses
system.cpu0.numCycles 417561800 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update for UDelayEvent quiesce change
2015-10-10 23:45:41 +02:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.kern.inst.quiesce 16515 # number of quiesce instructions executed
system.cpu0.committedInsts 346008550 # Number of instructions committed
system.cpu0.committedOps 406987651 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 373920117 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 356678 # Number of float alu accesses
system.cpu0.num_func_calls 20899397 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 52499689 # number of instructions that are conditional controls
system.cpu0.num_int_insts 373920117 # number of integer instructions
system.cpu0.num_fp_insts 356678 # number of float instructions
system.cpu0.num_int_register_reads 546105589 # number of times the integer registers were read
system.cpu0.num_int_register_writes 296761298 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 572858 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 307664 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 90112158 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 89900490 # number of times the CC registers were written
system.cpu0.num_mem_refs 124068171 # number of memory refs
system.cpu0.num_load_insts 64899300 # Number of load instructions
system.cpu0.num_store_insts 59168871 # Number of store instructions
system.cpu0.num_idle_cycles 407652478.881758 # Number of idle cycles
system.cpu0.num_busy_cycles 9909321.118242 # Number of busy cycles
system.cpu0.not_idle_fraction 0.023731 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.976269 # Percentage of idle cycles
system.cpu0.Branches 77190718 # Number of branches fetched
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.op_class::IntAlu 282157616 69.29% 69.29% # Class of executed instruction
system.cpu0.op_class::IntMult 905041 0.22% 69.51% # Class of executed instruction
system.cpu0.op_class::IntDiv 41769 0.01% 69.52% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 48126 0.01% 69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction
system.cpu0.op_class::MemRead 64899300 15.94% 85.47% # Class of executed instruction
system.cpu0.op_class::MemWrite 59168871 14.53% 100.00% # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.op_class::total 407220723 # Class of executed instruction
system.cpu0.dcache.tags.replacements 9652340 # number of replacements
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.tags.tagsinuse 511.999717 # Cycle average of tags in use
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.tags.total_refs 292908190 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 9652852 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 30.344212 # Average number of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.670724 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 4.324705 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.721037 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu3.data 5.283251 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970060 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.008447 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.011174 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu3.data 0.010319 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.tags.tag_accesses 1241214397 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 1241214397 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 60685320 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 18803520 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 26329065 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu3.data 44829860 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 150647765 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 55967588 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 17443504 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 23296963 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu3.data 37688434 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 134396489 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 158786 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 47711 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data 76477 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu3.data 112686 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 395660 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 125958 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data 46133 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu2.data 59042 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu3.data 98089 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 329222 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1437510 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 434789 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 583575 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 933284 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 3389158 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1528933 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 473870 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 632507 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu3.data 1071003 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 3706313 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 116652908 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 36247024 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 49626028 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu3.data 82518294 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 285044254 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 116811694 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 36294735 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 49702505 # number of overall hits
system.cpu0.dcache.overall_hits::cpu3.data 82630980 # number of overall hits
system.cpu0.dcache.overall_hits::total 285439914 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 2050128 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 627869 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 999043 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu3.data 3448243 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 7125283 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 845493 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 257929 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 592373 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu3.data 3452560 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 5148355 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 464960 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 152113 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data 201110 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu3.data 351568 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 1169751 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 684118 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data 112802 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu2.data 149261 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu3.data 279937 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 1226118 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 92149 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 39328 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 49168 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 175617 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 356262 # number of LoadLockedReq misses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.StoreCondReq_misses::cpu3.data 4 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 2895621 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 885798 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 1591416 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu3.data 6900803 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 12273638 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 3360581 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 1037911 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 1792526 # number of overall misses
system.cpu0.dcache.overall_misses::cpu3.data 7252371 # number of overall misses
system.cpu0.dcache.overall_misses::total 13443389 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 10396496000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 17205303000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 60680026500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 88281825500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 9995323500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 21800622500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 118348465967 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 150144411967 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 3701005000 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data 5339603500 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data 11362352929 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 20402961429 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 557489000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 738688500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 2354578500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 3650756000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 125500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 125500 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 20391819500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 39005925500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu3.data 179028492467 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 238426237467 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 20391819500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 39005925500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu3.data 179028492467 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 238426237467 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 62735448 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 19431389 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 27328108 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu3.data 48278103 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 157773048 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 56813081 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 17701433 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 23889336 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu3.data 41140994 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 139544844 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 623746 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 199824 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 277587 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 464254 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 1565411 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 810076 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 158935 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu2.data 208303 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu3.data 378026 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 1555340 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1529659 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 474117 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 632743 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 1108901 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 3745420 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1528934 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 473870 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 632507 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 1071007 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 3706318 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 119548529 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 37132822 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 51217444 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu3.data 89419097 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 297317892 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 120172275 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 37332646 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 51495031 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu3.data 89883351 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 298883303 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032679 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.032312 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.036557 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.071425 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.045162 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014882 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014571 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.024797 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.083920 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.036894 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.745432 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.761235 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.724494 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.757275 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.747248 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.844511 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.709737 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data 0.716557 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data 0.740523 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.788328 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060242 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.082950 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.077706 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.158370 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.095119 # miss rate for LoadLockedReq accesses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000001 # miss rate for StoreCondReq accesses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000004 # miss rate for StoreCondReq accesses
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024221 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023855 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.031072 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu3.data 0.077174 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.041281 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027965 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.027802 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.034810 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu3.data 0.080686 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.044979 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16558.383994 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17221.784248 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17597.375388 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 12389.939529 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38752.228326 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 36802.187980 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 34278.467562 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 29163.570105 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 32809.746281 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 35773.601276 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 40588.964406 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 16640.291904 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14175.371237 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15023.765457 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13407.463400 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10247.390965 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 31375 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25100 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23020.846175 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24510.200664 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 25943.139149 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 19425.881509 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19646.982737 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21760.312263 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 24685.512154 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 17735.575268 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 14877388 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 44459 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 886775 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 413 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.776959 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 107.648910 # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.writebacks::writebacks 7483477 # number of writebacks
system.cpu0.dcache.writebacks::total 7483477 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3222 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 130575 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 1920030 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 2053827 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 4922 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 261783 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 2870322 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 3137027 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data 26 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data 2099 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total 2125 # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8352 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 10672 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 107753 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 126777 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 8144 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 392358 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu3.data 4790352 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 5190854 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 8144 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 392358 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu3.data 4790352 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 5190854 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 624647 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 868468 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 1528213 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 3021328 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 253007 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 330590 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 582238 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 1165835 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 151732 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 198469 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 344358 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 694559 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 112802 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data 149235 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data 277838 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 539875 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 30976 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 38496 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 67864 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 137336 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 4 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 877654 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 1199058 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu3.data 2110451 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 4187163 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 1029386 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 1397527 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu3.data 2454809 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 4881722 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 6935 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 6911 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 6765 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20611 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 6456 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 6468 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 6500 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19424 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 13391 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 13379 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 13265 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 40035 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 9554770500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 13722884500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 26401240500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 49678895500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 9526378000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 11636542500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 21578675477 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 42741595977 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 3041699000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 3963544500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 6809698000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13814941500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 3588203000 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 5189095500 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data 10959309429 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 19736607929 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 400391000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 515235000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 967704000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1883330000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 121500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 121500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 19081148500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 25359427000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 47979915977 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 92420491477 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 22122847500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 29322971500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 54789613977 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 106235432977 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1364610000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1364502500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1307720500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4036833000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1311207000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1311882500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1281361955 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3904451455 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2675817000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2676385000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 2589082455 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7941284455 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032146 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.031779 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.031654 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019150 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014293 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.013838 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.014152 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008355 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.759328 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.714979 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.741745 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.443691 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.709737 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.716432 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.734971 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.347111 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065334 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.060840 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.061199 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.036668 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000004 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023636 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023411 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.023602 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.014083 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027573 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.027139 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.027311 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.016333 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15296.272135 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15801.255199 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17275.890534 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16442.734950 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 37652.626212 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35199.317886 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 37061.606211 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36661.788312 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20046.522817 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 19970.597423 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 19775.053868 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19890.234667 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 31809.746281 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 34771.303649 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 39444.962277 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36557.736382 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12925.845816 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13384.117830 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14259.460097 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13713.301683 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 30375 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 30375 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21741.083046 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21149.458158 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 22734.437320 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22072.341458 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21491.304039 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20982.042923 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 22319.298152 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21761.876849 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 196771.449171 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 197439.227319 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 193306.799704 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 195858.182524 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 203098.977695 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 202826.607916 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 197132.608462 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 201011.709998 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 199822.044657 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 200043.725241 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 195181.489257 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 198358.547646 # average overall mshr uncacheable latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.icache.tags.replacements 15741403 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.971353 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 557979460 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 15741915 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 35.445463 # Average number of references to valid blocks.
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.icache.tags.warmup_cycle 11785355500 # Cycle when the warmup percentage was hit.
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.icache.tags.occ_blocks::cpu0.inst 478.989508 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 3.251405 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 22.715639 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu3.inst 7.014801 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.935526 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.006350 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.044366 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu3.inst 0.013701 # Average percentage of cache occupancy
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.icache.tags.occ_percent::total 0.999944 # Average percentage of cache occupancy
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.icache.tags.tag_accesses 589817883 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 589817883 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 340610645 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 106018813 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 63853653 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu3.inst 47496349 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 557979460 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 340610645 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 106018813 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 63853653 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu3.inst 47496349 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 557979460 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 340610645 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 106018813 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 63853653 # number of overall hits
system.cpu0.icache.overall_hits::cpu3.inst 47496349 # number of overall hits
system.cpu0.icache.overall_hits::total 557979460 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 5587852 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 1682310 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 3897820 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu3.inst 4928444 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 16096426 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 5587852 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 1682310 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 3897820 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu3.inst 4928444 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 16096426 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 5587852 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 1682310 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 3897820 # number of overall misses
system.cpu0.icache.overall_misses::cpu3.inst 4928444 # number of overall misses
system.cpu0.icache.overall_misses::total 16096426 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 22725716500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 53501368000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 66794187305 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 143021271805 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 22725716500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 53501368000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu3.inst 66794187305 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 143021271805 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 22725716500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 53501368000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu3.inst 66794187305 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 143021271805 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 346198497 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 107701123 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 67751473 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu3.inst 52424793 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 574075886 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 346198497 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 107701123 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 67751473 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu3.inst 52424793 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 574075886 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 346198497 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 107701123 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 67751473 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu3.inst 52424793 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 574075886 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016141 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015620 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.057531 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu3.inst 0.094010 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.028039 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016141 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015620 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.057531 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu3.inst 0.094010 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.028039 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016141 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015620 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.057531 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu3.inst 0.094010 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.028039 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13508.637825 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13725.971954 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13552.794209 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 8885.281230 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13508.637825 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13725.971954 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13552.794209 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 8885.281230 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13508.637825 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13725.971954 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13552.794209 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 8885.281230 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 61852 # number of cycles access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.icache.blocked::no_mshrs 3678 # number of cycles access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.816748 # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.icache.writebacks::writebacks 15741403 # number of writebacks
system.cpu0.icache.writebacks::total 15741403 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 354429 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 354429 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu3.inst 354429 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 354429 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu3.inst 354429 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 354429 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 1682310 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 3897820 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 4574015 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 10154145 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 1682310 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 3897820 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu3.inst 4574015 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 10154145 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 1682310 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 3897820 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu3.inst 4574015 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 10154145 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 21043406500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 49603548000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 58927308844 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 129574263344 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 21043406500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 49603548000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 58927308844 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 129574263344 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 21043406500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 49603548000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 58927308844 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 129574263344 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015620 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.057531 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.087249 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017688 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015620 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.057531 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.087249 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.017688 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015620 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.057531 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.087249 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.017688 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12508.637825 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12725.971954 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12883.059816 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12760.726122 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12508.637825 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12725.971954 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12883.059816 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12760.726122 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12508.637825 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12725.971954 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12883.059816 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12760.726122 # average overall mshr miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.walker.walks 31832 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 31832 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4623 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 23155 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 6 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 31826 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 1.131151 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 163.231245 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-2047 31824 99.99% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.walker.walkWaitTime::total 31826 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 27784 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 25027.875756 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 21593.645021 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 16285.465271 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767 18174 65.41% 65.41% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535 9447 34.00% 99.41% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-131071 1 0.00% 99.42% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-163839 131 0.47% 99.89% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::163840-196607 9 0.03% 99.92% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-229375 1 0.00% 99.92% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::229376-262143 1 0.00% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911 8 0.03% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::294912-327679 2 0.01% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::360448-393215 5 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-425983 2 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::491520-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 27784 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples -2880889132 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 1.351726 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 1013283500 -35.17% -35.17% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1 -3894172632 135.17% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total -2880889132 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 23155 83.36% 83.36% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 4623 16.64% 100.00% # Table walker page sizes translated
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.dtb.walker.walkPageSizes::total 27778 # Table walker page sizes translated
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 31832 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 31832 # Table walker requests started/completed, data/inst
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 27778 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 27778 # Table walker requests started/completed, data/inst
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.walker.walkRequestOrigin::total 59610 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.read_hits 20112265 # DTB read hits
system.cpu1.dtb.read_misses 24546 # DTB read misses
system.cpu1.dtb.write_hits 18343322 # DTB write hits
system.cpu1.dtb.write_misses 7286 # DTB write misses
system.cpu1.dtb.flush_tlb 1188 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.flush_tlb_mva_asid 5429 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 141 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 18466 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.prefetch_faults 996 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.perms_faults 2613 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 20136811 # DTB read accesses
system.cpu1.dtb.write_accesses 18350608 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.hits 38455587 # DTB hits
system.cpu1.dtb.misses 31832 # DTB misses
system.cpu1.dtb.accesses 38487419 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu1.itb.walker.walks 20094 # Table walker walks requested
system.cpu1.itb.walker.walksLong 20094 # Table walker walks initiated with long descriptors
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 971 # Level at which table walker walks with long descriptors terminate
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 17728 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples 20094 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 20094 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 20094 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 18699 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 28327.343708 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 25076.534832 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 18332.547535 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535 18529 99.09% 99.09% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607 145 0.78% 99.87% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143 7 0.04% 99.90% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679 8 0.04% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215 6 0.03% 99.98% # Table walker service (enqueue to completion) latency
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.02% 99.99% # Table walker service (enqueue to completion) latency
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 18699 # Table walker service (enqueue to completion) latency
stats: Update switcheroo reference stats The Minor draining fixes affect perturb the timing slightly since it affects how the simulator is drained. Update reference statistics to reflect this expected change.
2015-07-31 18:04:59 +02:00
system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu1.itb.walker.walkPageSizes::4K 17728 94.81% 94.81% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 971 5.19% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 18699 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20094 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20094 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18699 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18699 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 38793 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 107701123 # ITB inst hits
system.cpu1.itb.inst_misses 20094 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu1.itb.flush_tlb 1188 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu1.itb.flush_tlb_mva_asid 5429 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 141 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 13720 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu1.itb.inst_accesses 107721217 # ITB inst accesses
system.cpu1.itb.hits 107701123 # DTB hits
system.cpu1.itb.misses 20094 # DTB misses
system.cpu1.itb.accesses 107721217 # DTB accesses
system.cpu1.numCycles 1188094365 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update for UDelayEvent quiesce change
2015-10-10 23:45:41 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu1.committedInsts 107621607 # Number of instructions committed
system.cpu1.committedOps 126383134 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 116203246 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 115467 # Number of float alu accesses
system.cpu1.num_func_calls 6450925 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 16259693 # number of instructions that are conditional controls
system.cpu1.num_int_insts 116203246 # number of integer instructions
system.cpu1.num_fp_insts 115467 # number of float instructions
system.cpu1.num_int_register_reads 168004862 # number of times the integer registers were read
system.cpu1.num_int_register_writes 92163558 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 188871 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 91760 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 27757608 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 27690244 # number of times the CC registers were written
system.cpu1.num_mem_refs 38453101 # number of memory refs
system.cpu1.num_load_insts 20111693 # Number of load instructions
system.cpu1.num_store_insts 18341408 # Number of store instructions
system.cpu1.num_idle_cycles 1162766845.919452 # Number of idle cycles
system.cpu1.num_busy_cycles 25327519.080548 # Number of busy cycles
system.cpu1.not_idle_fraction 0.021318 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.978682 # Percentage of idle cycles
system.cpu1.Branches 23943919 # Number of branches fetched
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu1.op_class::IntAlu 87732322 69.37% 69.37% # Class of executed instruction
system.cpu1.op_class::IntMult 254511 0.20% 69.58% # Class of executed instruction
system.cpu1.op_class::IntDiv 10291 0.01% 69.58% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 12383 0.01% 69.59% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction
system.cpu1.op_class::MemRead 20111693 15.90% 85.50% # Class of executed instruction
system.cpu1.op_class::MemWrite 18341408 14.50% 100.00% # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu1.op_class::total 126462650 # Class of executed instruction
system.cpu2.branchPred.lookups 39591395 # Number of BP lookups
system.cpu2.branchPred.condPredicted 27402166 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 2021243 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 28606558 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 20093171 # Number of BTB hits
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu2.branchPred.BTBHitPct 70.239737 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 4887391 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 324081 # Number of incorrect RAS predictions.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu2.dtb.walker.walks 95006 # Table walker walks requested
system.cpu2.dtb.walker.walksLong 95006 # Table walker walks initiated with long descriptors
system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 6740 # Level at which table walker walks with long descriptors terminate
system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 29708 # Level at which table walker walks with long descriptors terminate
system.cpu2.dtb.walker.walkWaitTime::samples 95006 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::0 95006 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::total 95006 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkCompletionTime::samples 36448 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::mean 25417.457748 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::gmean 22182.749988 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::stdev 16592.444485 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::0-65535 36232 99.41% 99.41% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::65536-131071 1 0.00% 99.41% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::131072-196607 183 0.50% 99.91% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::196608-262143 9 0.02% 99.94% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::262144-327679 9 0.02% 99.96% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::327680-393215 3 0.01% 99.97% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::393216-458751 8 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::589824-655359 2 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::total 36448 # Table walker service (enqueue to completion) latency
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu2.dtb.walker.walksPending::samples 2000224000 # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::0 2000224000 100.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::total 2000224000 # Table walker pending requests distribution
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu2.dtb.walker.walkPageSizes::4K 29708 81.51% 81.51% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::2M 6740 18.49% 100.00% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::total 36448 # Table walker page sizes translated
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 95006 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 95006 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 36448 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 36448 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin::total 131454 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu2.dtb.read_hits 28518980 # DTB read hits
system.cpu2.dtb.read_misses 79318 # DTB read misses
system.cpu2.dtb.write_hits 24832866 # DTB write hits
system.cpu2.dtb.write_misses 15688 # DTB write misses
system.cpu2.dtb.flush_tlb 1188 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu2.dtb.flush_tlb_mva_asid 6544 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid 184 # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries 22314 # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults 75 # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults 2052 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu2.dtb.perms_faults 3674 # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses 28598298 # DTB read accesses
system.cpu2.dtb.write_accesses 24848554 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu2.dtb.hits 53351846 # DTB hits
system.cpu2.dtb.misses 95006 # DTB misses
system.cpu2.dtb.accesses 53446852 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu2.itb.walker.walks 27923 # Table walker walks requested
system.cpu2.itb.walker.walksLong 27923 # Table walker walks initiated with long descriptors
system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1838 # Level at which table walker walks with long descriptors terminate
system.cpu2.itb.walker.walksLongTerminationLevel::Level3 23508 # Level at which table walker walks with long descriptors terminate
system.cpu2.itb.walker.walkWaitTime::samples 27923 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::0 27923 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::total 27923 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkCompletionTime::samples 25346 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::mean 28940.858518 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::gmean 25854.889269 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::stdev 17791.815030 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::0-32767 13319 52.55% 52.55% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::32768-65535 11735 46.30% 98.85% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::131072-163839 221 0.87% 99.72% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::163840-196607 46 0.18% 99.90% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::196608-229375 3 0.01% 99.91% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::229376-262143 3 0.01% 99.93% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::262144-294911 12 0.05% 99.97% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::294912-327679 3 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::327680-360447 2 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::total 25346 # Table walker service (enqueue to completion) latency
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu2.itb.walker.walksPending::samples 2000197500 # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::0 2000197500 100.00% 100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::total 2000197500 # Table walker pending requests distribution
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu2.itb.walker.walkPageSizes::4K 23508 92.75% 92.75% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::2M 1838 7.25% 100.00% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::total 25346 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27923 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27923 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 25346 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::total 25346 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin::total 53269 # Table walker requests started/completed, data/inst
system.cpu2.itb.inst_hits 67809364 # ITB inst hits
system.cpu2.itb.inst_misses 27923 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu2.itb.flush_tlb 1188 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu2.itb.flush_tlb_mva_asid 6544 # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid 184 # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries 17096 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu2.itb.perms_faults 54805 # Number of TLB faults due to permissions restrictions
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu2.itb.inst_accesses 67837287 # ITB inst accesses
system.cpu2.itb.hits 67809364 # DTB hits
system.cpu2.itb.misses 27923 # DTB misses
system.cpu2.itb.accesses 67837287 # DTB accesses
system.cpu2.numCycles 6729019952 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu2.committedInsts 145507421 # Number of instructions committed
system.cpu2.committedOps 170762991 # Number of ops (including micro ops) committed
system.cpu2.discardedOps 13321557 # Number of ops (including micro ops) which were discarded before commit
system.cpu2.numFetchSuspends 1585 # Number of times Execute suspended instruction fetching
system.cpu2.quiesceCycles 95906188119 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.cpi 46.245201 # CPI: cycles per instruction
system.cpu2.ipc 0.021624 # IPC: instructions per cycle
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu2.tickCycles 269790363 # Number of cycles that the object actually ticked
system.cpu2.idleCycles 6459229589 # Total number of cycles that the object has spent stopped
system.cpu3.branchPred.lookups 72990389 # Number of BP lookups
system.cpu3.branchPred.condPredicted 49393926 # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect 3261178 # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups 49526964 # Number of BTB lookups
system.cpu3.branchPred.BTBHits 35642873 # Number of BTB hits
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.branchPred.BTBHitPct 71.966602 # BTB Hit Percentage
system.cpu3.branchPred.usedRAS 9524201 # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect 103362 # Number of incorrect RAS predictions.
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu3.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu3.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu3.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu3.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu3.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu3.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu3.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu3.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu3.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.dtb.walker.walks 500429 # Table walker walks requested
system.cpu3.dtb.walker.walksLong 500429 # Table walker walks initiated with long descriptors
system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8187 # Level at which table walker walks with long descriptors terminate
system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 49422 # Level at which table walker walks with long descriptors terminate
system.cpu3.dtb.walker.walksSquashedBefore 313054 # Table walks squashed before starting
system.cpu3.dtb.walker.walkWaitTime::samples 187375 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::mean 2308.042695 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::stdev 13865.789258 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::0-65535 186198 99.37% 99.37% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::65536-131071 657 0.35% 99.72% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::131072-196607 362 0.19% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::196608-262143 70 0.04% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::262144-327679 56 0.03% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::327680-393215 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::393216-458751 9 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::458752-524287 11 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::total 187375 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkCompletionTime::samples 233412 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::mean 22762.724282 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::gmean 18452.196764 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::stdev 18647.508849 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::0-65535 228859 98.05% 98.05% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::65536-131071 3345 1.43% 99.48% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::131072-196607 881 0.38% 99.86% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::196608-262143 33 0.01% 99.87% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::262144-327679 195 0.08% 99.96% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::327680-393215 58 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::393216-458751 30 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::458752-524287 10 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::total 233412 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walksPending::samples -23888540384 # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::mean -0.243050 # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::0-3 -24451568384 102.36% 102.36% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::4-7 309528500 -1.30% 101.06% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::8-11 106605000 -0.45% 100.61% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::12-15 67439500 -0.28% 100.33% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::16-19 25633500 -0.11% 100.23% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::20-23 15083500 -0.06% 100.16% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::24-27 13632500 -0.06% 100.11% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::28-31 20996500 -0.09% 100.02% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::32-35 3974500 -0.02% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::36-39 102000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::40-43 25000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::44-47 6000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::48-51 1500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::total -23888540384 # Table walker pending requests distribution
system.cpu3.dtb.walker.walkPageSizes::4K 49422 85.79% 85.79% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::2M 8187 14.21% 100.00% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::total 57609 # Table walker page sizes translated
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 500429 # Table walker requests started/completed, data/inst
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 500429 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 57609 # Table walker requests started/completed, data/inst
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 57609 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin::total 558038 # Table walker requests started/completed, data/inst
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.inst_hits 0 # ITB inst hits
system.cpu3.dtb.inst_misses 0 # ITB inst misses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.dtb.read_hits 58164219 # DTB read hits
system.cpu3.dtb.read_misses 342154 # DTB read misses
system.cpu3.dtb.write_hits 45137816 # DTB write hits
system.cpu3.dtb.write_misses 158275 # DTB write misses
system.cpu3.dtb.flush_tlb 1187 # Number of times complete TLB was flushed
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.dtb.flush_tlb_mva_asid 11250 # Number of times TLB was flushed by MVA & ASID
system.cpu3.dtb.flush_tlb_asid 304 # Number of times TLB was flushed by ASID
system.cpu3.dtb.flush_entries 29745 # Number of entries that have been flushed from TLB
system.cpu3.dtb.align_faults 69 # Number of TLB faults due to alignment restrictions
system.cpu3.dtb.prefetch_faults 4820 # Number of TLB faults due to prefetch
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.dtb.perms_faults 32652 # Number of TLB faults due to permissions restrictions
system.cpu3.dtb.read_accesses 58506373 # DTB read accesses
system.cpu3.dtb.write_accesses 45296091 # DTB write accesses
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.inst_accesses 0 # ITB inst accesses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.dtb.hits 103302035 # DTB hits
system.cpu3.dtb.misses 500429 # DTB misses
system.cpu3.dtb.accesses 103802464 # DTB accesses
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu3.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu3.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu3.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu3.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu3.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu3.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu3.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu3.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu3.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.itb.walker.walks 60030 # Table walker walks requested
system.cpu3.itb.walker.walksLong 60030 # Table walker walks initiated with long descriptors
system.cpu3.itb.walker.walksLongTerminationLevel::Level2 1961 # Level at which table walker walks with long descriptors terminate
system.cpu3.itb.walker.walksLongTerminationLevel::Level3 41132 # Level at which table walker walks with long descriptors terminate
system.cpu3.itb.walker.walksSquashedBefore 8185 # Table walks squashed before starting
system.cpu3.itb.walker.walkWaitTime::samples 51845 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::mean 1585.842415 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::stdev 9699.543374 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::0-32767 51363 99.07% 99.07% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::32768-65535 302 0.58% 99.65% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::65536-98303 36 0.07% 99.72% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::98304-131071 44 0.08% 99.81% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::131072-163839 73 0.14% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::163840-196607 15 0.03% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::229376-262143 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::total 51845 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkCompletionTime::samples 51278 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::mean 29392.673271 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::gmean 24917.769531 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::stdev 21411.451197 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::0-65535 50198 97.89% 97.89% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::65536-131071 365 0.71% 98.61% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::131072-196607 621 1.21% 99.82% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::196608-262143 29 0.06% 99.87% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::262144-327679 49 0.10% 99.97% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::327680-393215 9 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::total 51278 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walksPending::samples -28186036180 # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::mean 0.973417 # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::stdev 0.149857 # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::0 -706639900 2.51% 2.51% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::1 -27517172780 97.63% 100.13% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::2 33476500 -0.12% 100.02% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::3 3852500 -0.01% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::4 369000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::5 47500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::6 31000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::total -28186036180 # Table walker pending requests distribution
system.cpu3.itb.walker.walkPageSizes::4K 41132 95.45% 95.45% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::2M 1961 4.55% 100.00% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::total 43093 # Table walker page sizes translated
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 60030 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Requested::total 60030 # Table walker requests started/completed, data/inst
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 43093 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::total 43093 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin::total 103123 # Table walker requests started/completed, data/inst
system.cpu3.itb.inst_hits 52557456 # ITB inst hits
system.cpu3.itb.inst_misses 60030 # ITB inst misses
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.itb.read_hits 0 # DTB read hits
system.cpu3.itb.read_misses 0 # DTB read misses
system.cpu3.itb.write_hits 0 # DTB write hits
system.cpu3.itb.write_misses 0 # DTB write misses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.itb.flush_tlb 1187 # Number of times complete TLB was flushed
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.itb.flush_tlb_mva_asid 11250 # Number of times TLB was flushed by MVA & ASID
system.cpu3.itb.flush_tlb_asid 304 # Number of times TLB was flushed by ASID
system.cpu3.itb.flush_entries 23210 # Number of entries that have been flushed from TLB
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.itb.perms_faults 115031 # Number of TLB faults due to permissions restrictions
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.itb.read_accesses 0 # DTB read accesses
system.cpu3.itb.write_accesses 0 # DTB write accesses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.itb.inst_accesses 52617486 # ITB inst accesses
system.cpu3.itb.hits 52557456 # DTB hits
system.cpu3.itb.misses 60030 # DTB misses
system.cpu3.itb.accesses 52617486 # DTB accesses
system.cpu3.numCycles 367681719 # number of cpu cycles simulated
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.fetch.icacheStallCycles 137382452 # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts 324487112 # Number of instructions fetch has processed
system.cpu3.fetch.Branches 72990389 # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches 45167074 # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles 207382227 # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles 7378767 # Number of cycles fetch has spent squashing
system.cpu3.fetch.TlbCycles 1499130 # Number of cycles fetch has spent waiting for tlb
system.cpu3.fetch.MiscStallCycles 9416 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.PendingDrainCycles 2414 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu3.fetch.PendingTrapStallCycles 2929845 # Number of stall cycles due to pending traps
system.cpu3.fetch.PendingQuiesceStallCycles 92895 # Number of stall cycles due to pending quiesce instructions
system.cpu3.fetch.IcacheWaitRetryStallCycles 5499 # Number of stall cycles due to full MSHR
system.cpu3.fetch.CacheLines 52424871 # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes 2006412 # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.ItlbSquashes 23984 # Number of outstanding ITLB misses that were squashed
system.cpu3.fetch.rateDist::samples 352993106 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean 1.076120 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev 2.324101 # Number of instructions fetched each cycle (Total)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.fetch.rateDist::0 272962947 77.33% 77.33% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1 10013633 2.84% 80.16% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2 10141075 2.87% 83.04% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3 7427569 2.10% 85.14% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4 15412828 4.37% 89.51% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5 5010537 1.42% 90.93% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6 5410828 1.53% 92.46% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7 4793943 1.36% 93.82% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8 21819746 6.18% 100.00% # Number of instructions fetched each cycle (Total)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.fetch.rateDist::total 352993106 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate 0.198515 # Number of branch fetches per cycle
system.cpu3.fetch.rate 0.882522 # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles 112311908 # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles 171536917 # Number of cycles decode is blocked
system.cpu3.decode.RunCycles 59078029 # Number of cycles decode is running
system.cpu3.decode.UnblockCycles 7166258 # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles 2898243 # Number of cycles decode is squashing
system.cpu3.decode.BranchResolved 10967565 # Number of times decode resolved a branch
system.cpu3.decode.BranchMispred 802193 # Number of times decode detected a branch misprediction
system.cpu3.decode.DecodedInsts 354637256 # Number of instructions handled by decode
system.cpu3.decode.SquashedInsts 2468190 # Number of squashed instructions handled by decode
system.cpu3.rename.SquashCycles 2898243 # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles 116412746 # Number of cycles rename is idle
system.cpu3.rename.BlockCycles 14091886 # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles 135873689 # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles 62053830 # Number of cycles rename is running
system.cpu3.rename.UnblockCycles 21660921 # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts 346387617 # Number of instructions processed by rename
system.cpu3.rename.ROBFullEvents 69362 # Number of times rename has blocked due to ROB full
system.cpu3.rename.IQFullEvents 1230764 # Number of times rename has blocked due to IQ full
system.cpu3.rename.LQFullEvents 966889 # Number of times rename has blocked due to LQ full
system.cpu3.rename.SQFullEvents 11283496 # Number of times rename has blocked due to SQ full
system.cpu3.rename.FullRegisterEvents 2101 # Number of times there has been no free registers
system.cpu3.rename.RenamedOperands 331152482 # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups 530946274 # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups 409391445 # Number of integer rename lookups
system.cpu3.rename.fp_rename_lookups 488669 # Number of floating rename lookups
system.cpu3.rename.CommittedMaps 278384590 # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps 52767887 # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts 7985124 # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts 6877230 # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts 39792362 # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads 55963963 # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores 47449628 # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads 7288791 # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores 7899727 # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded 329013774 # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded 7979579 # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued 328894803 # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued 473789 # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined 44157935 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined 28349943 # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved 195322 # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples 352993106 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean 0.931732 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev 1.657853 # Number of insts issued each cycle
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.iq.issued_per_cycle::0 225053646 63.76% 63.76% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1 52887195 14.98% 78.74% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2 24125112 6.83% 85.57% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3 17152120 4.86% 90.43% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4 12799961 3.63% 94.06% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5 9006883 2.55% 96.61% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6 6061659 1.72% 98.33% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7 3555429 1.01% 99.33% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8 2351101 0.67% 100.00% # Number of insts issued each cycle
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.iq.issued_per_cycle::total 352993106 # Number of insts issued each cycle
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.iq.fu_full::IntAlu 1666434 25.55% 25.55% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult 16334 0.25% 25.81% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv 1493 0.02% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead 2666569 40.89% 66.72% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite 2170161 33.28% 100.00% # attempts to use FU when none available
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.iq.FU_type_0::No_OpClass 37 0.00% 0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu 222970071 67.79% 67.79% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult 784272 0.24% 68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv 39650 0.01% 68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd 183 0.00% 68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp 1 0.00% 68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc 1 0.00% 68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc 42230 0.01% 68.06% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.06% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.06% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.06% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead 59327329 18.04% 86.10% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite 45731029 13.90% 100.00% # Type of FU issued
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.iq.FU_type_0::total 328894803 # Type of FU issued
system.cpu3.iq.rate 0.894510 # Inst issue rate
system.cpu3.iq.fu_busy_cnt 6520991 # FU busy when requested
system.cpu3.iq.fu_busy_rate 0.019827 # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads 1017124188 # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes 381195731 # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses 316969788 # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads 653304 # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes 324459 # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses 290942 # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses 335066450 # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses 349307 # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads 2611645 # Number of loads that had data forwarded from stores
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.iew.lsq.thread0.squashedLoads 8878101 # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses 11627 # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation 374989 # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores 4859757 # Number of stores squashed
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.iew.lsq.thread0.rescheduledLoads 2089653 # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked 4248814 # Number of times an access to memory failed due to the cache being blocked
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.iew.iewSquashCycles 2898243 # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles 8732301 # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles 4121646 # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts 337068759 # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts 994758 # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts 55963963 # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts 47449628 # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts 6728240 # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents 117681 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents 3958014 # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents 374989 # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect 1476989 # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect 1294241 # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts 2771230 # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts 325158275 # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts 58155452 # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts 3242017 # Number of squashed instructions skipped in execute
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iew.exec_swp 0 # number of swp insts executed
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.iew.exec_nop 75406 # number of nop insts executed
system.cpu3.iew.exec_refs 103291863 # number of memory reference insts executed
system.cpu3.iew.exec_branches 60348156 # Number of branches executed
system.cpu3.iew.exec_stores 45136411 # Number of stores executed
system.cpu3.iew.exec_rate 0.884347 # Inst execution rate
system.cpu3.iew.wb_sent 317931631 # cumulative count of insts sent to commit
system.cpu3.iew.wb_count 317260730 # cumulative count of insts written-back
system.cpu3.iew.wb_producers 156804040 # num instructions producing a value
system.cpu3.iew.wb_consumers 272237503 # num instructions consuming a value
system.cpu3.iew.wb_rate 0.862868 # insts written-back per cycle
system.cpu3.iew.wb_fanout 0.575983 # average fanout of values written-back
system.cpu3.commit.commitSquashedInsts 44184156 # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls 7784257 # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts 2469882 # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples 345475115 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean 0.847631 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev 1.845112 # Number of insts commited each cycle
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.commit.committed_per_cycle::0 238965063 69.17% 69.17% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1 51652898 14.95% 84.12% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2 18588674 5.38% 89.50% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3 8404155 2.43% 91.93% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4 6041826 1.75% 93.68% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5 3641114 1.05% 94.74% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6 3441360 1.00% 95.73% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7 2148532 0.62% 96.36% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8 12591493 3.64% 100.00% # Number of insts commited each cycle
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.commit.committed_per_cycle::total 345475115 # Number of insts commited each cycle
system.cpu3.commit.committedInsts 249281112 # Number of instructions committed
system.cpu3.commit.committedOps 292835413 # Number of ops (including micro ops) committed
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.commit.refs 89675732 # Number of memory references committed
system.cpu3.commit.loads 47085861 # Number of loads committed
system.cpu3.commit.membars 1972703 # Number of memory barriers committed
system.cpu3.commit.branches 55678709 # Number of branches committed
system.cpu3.commit.fp_insts 279951 # Number of committed floating point instructions.
system.cpu3.commit.int_insts 269023900 # Number of committed integer instructions.
system.cpu3.commit.function_calls 7382684 # Number of function calls committed.
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.commit.op_class_0::IntAlu 202481834 69.15% 69.15% # Class of committed instruction
system.cpu3.commit.op_class_0::IntMult 611500 0.21% 69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv 29936 0.01% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMisc 36411 0.01% 69.38% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.38% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.38% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.38% # Class of committed instruction
system.cpu3.commit.op_class_0::MemRead 47085861 16.08% 85.46% # Class of committed instruction
system.cpu3.commit.op_class_0::MemWrite 42589871 14.54% 100.00% # Class of committed instruction
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu3.commit.op_class_0::total 292835413 # Class of committed instruction
system.cpu3.commit.bw_lim_events 12591493 # number cycles where commit BW limit reached
system.cpu3.rob.rob_reads 667852271 # The number of ROB reads
system.cpu3.rob.rob_writes 681568770 # The number of ROB writes
system.cpu3.timesIdled 2347442 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles 14688613 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles 98704312464 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts 249281112 # Number of Instructions Simulated
system.cpu3.committedOps 292835413 # Number of Ops (including micro ops) Simulated
system.cpu3.cpi 1.474968 # CPI: Cycles Per Instruction
system.cpu3.cpi_total 1.474968 # CPI: Total CPI of All Threads
system.cpu3.ipc 0.677981 # IPC: Instructions Per Cycle
system.cpu3.ipc_total 0.677981 # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads 383320839 # number of integer regfile reads
system.cpu3.int_regfile_writes 226802116 # number of integer regfile writes
system.cpu3.fp_regfile_reads 566354 # number of floating regfile reads
system.cpu3.fp_regfile_writes 353692 # number of floating regfile writes
system.cpu3.cc_regfile_reads 69391716 # number of cc regfile reads
system.cpu3.cc_regfile_writes 70028526 # number of cc regfile writes
system.cpu3.misc_regfile_reads 653217985 # number of misc regfile reads
system.cpu3.misc_regfile_writes 7838267 # number of misc regfile writes
system.iobus.trans_dist::ReadReq 40272 # Transaction distribution
system.iobus.trans_dist::ReadResp 40272 # Transaction distribution
system.iobus.trans_dist::WriteReq 136541 # Transaction distribution
system.iobus.trans_dist::WriteResp 136541 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47702 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::total 122584 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count::total 353626 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47722 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::total 155714 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size::total 7492080 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 34502500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer1.occupancy 5500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer2.occupancy 217500 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer16.occupancy 5500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer23.occupancy 12266000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer24.occupancy 21519500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer25.occupancy 257935387 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.respLayer0.occupancy 58894000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.respLayer3.occupancy 75406000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iocache.tags.replacements 115463 # number of replacements
system.iocache.tags.tagsinuse 10.424920 # Cycle average of tags in use
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iocache.tags.warmup_cycle 13089166486009 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.544579 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 6.880341 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.221536 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.430021 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.651557 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iocache.tags.tag_accesses 1039686 # Number of tag accesses
system.iocache.tags.data_accesses 1039686 # Number of data accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses
system.iocache.demand_misses::total 8857 # number of demand (read+write) misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iocache.overall_misses::realview.ide 8817 # number of overall misses
system.iocache.overall_misses::total 8857 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 1102393747 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1102393747 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 6261704640 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 6261704640 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 1102393747 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 1102393747 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 1102393747 # number of overall miss cycles
system.iocache.overall_miss_latency::total 1102393747 # number of overall miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_accesses::realview.ide 8817 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 125030.480549 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124507.990400 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 58704.948624 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 58704.948624 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 125030.480549 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124465.817658 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 125030.480549 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124465.817658 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 24279 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iocache.blocked::no_mshrs 2397 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 10.128911 # average number of cycles each access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.iocache.writebacks::writebacks 106631 # number of writebacks
system.iocache.writebacks::total 106631 # number of writebacks
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_mshr_misses::realview.ide 5695 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 5695 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 48080 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 48080 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 5695 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 5695 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 5695 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 5695 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 817643747 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 817643747 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 3857704640 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 3857704640 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 817643747 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 817643747 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 817643747 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 817643747 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.645911 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.643212 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.450761 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 0.450761 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 0.645911 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.642994 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 0.645911 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.642994 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 143572.211940 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 143572.211940 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80235.121464 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80235.121464 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 143572.211940 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 143572.211940 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 143572.211940 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 143572.211940 # average overall mshr miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.l2c.tags.replacements 1138666 # number of replacements
system.l2c.tags.tagsinuse 65322.262178 # Cycle average of tags in use
system.l2c.tags.total_refs 47289153 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1201213 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 39.367833 # Average number of references to valid blocks.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.l2c.tags.occ_blocks::writebacks 36868.228473 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 143.137292 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 207.018752 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 3683.589947 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 7937.199418 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 31.598194 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 49.489312 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 262.199860 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 1950.255648 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker 35.983983 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.itb.walker 62.743334 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 1641.772402 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 3638.516325 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.dtb.walker 77.227279 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.itb.walker 111.401868 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst 2775.336167 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data 5846.563924 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.562565 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002184 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.003159 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.056207 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.121112 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000482 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000755 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.004001 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.029759 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000549 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.itb.walker 0.000957 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.025051 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.055519 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.dtb.walker 0.001178 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.itb.walker 0.001700 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst 0.042348 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data 0.089211 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.996739 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 289 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 62258 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 289 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 551 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2814 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 5213 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 53546 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.004410 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.949982 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 418516157 # Number of tag accesses
system.l2c.tags.data_accesses 418516157 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 157261 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 108108 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 55934 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 41818 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker 153552 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker 59055 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.dtb.walker 287259 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.itb.walker 109772 # number of ReadReq hits
system.l2c.ReadReq_hits::total 972759 # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks 7483477 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 7483477 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 15738935 # number of WritebackClean hits
system.l2c.WritebackClean_hits::total 15738935 # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data 3877 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 1349 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 1492 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3.data 2643 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 9361 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu3.data 3 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 649263 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 196007 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 263508 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3.data 471779 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 1580557 # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 5552063 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 1675541 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst 3875158 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu3.inst 4545901 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 15648663 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 2501274 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 780488 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data 1066018 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3.data 1858859 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 6206639 # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data 287190 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data 94194 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu2.data 123070 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu3.data 227443 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total 731897 # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker 157261 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 108108 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 5552063 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 3150537 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 55934 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 41818 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 1675541 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 976495 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker 153552 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker 59055 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 3875158 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 1329526 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.dtb.walker 287259 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.itb.walker 109772 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst 4545901 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data 2330638 # number of demand (read+write) hits
system.l2c.demand_hits::total 24408618 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 157261 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 108108 # number of overall hits
system.l2c.overall_hits::cpu0.inst 5552063 # number of overall hits
system.l2c.overall_hits::cpu0.data 3150537 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 55934 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 41818 # number of overall hits
system.l2c.overall_hits::cpu1.inst 1675541 # number of overall hits
system.l2c.overall_hits::cpu1.data 976495 # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker 153552 # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker 59055 # number of overall hits
system.l2c.overall_hits::cpu2.inst 3875158 # number of overall hits
system.l2c.overall_hits::cpu2.data 1329526 # number of overall hits
system.l2c.overall_hits::cpu3.dtb.walker 287259 # number of overall hits
system.l2c.overall_hits::cpu3.itb.walker 109772 # number of overall hits
system.l2c.overall_hits::cpu3.inst 4545901 # number of overall hits
system.l2c.overall_hits::cpu3.data 2330638 # number of overall hits
system.l2c.overall_hits::total 24408618 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 1198 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 1246 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 399 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker 328 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker 451 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.itb.walker 460 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.dtb.walker 1023 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.itb.walker 927 # number of ReadReq misses
system.l2c.ReadReq_misses::total 6032 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 13762 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 4541 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 5827 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data 9417 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 33547 # number of UpgradeReq misses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.l2c.SCUpgradeReq_misses::cpu3.data 1 # number of SCUpgradeReq misses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.l2c.ReadExReq_misses::cpu0.data 178591 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 51110 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 59801 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data 100893 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 390395 # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst 35789 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst 6769 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst 22662 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu3.inst 28031 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total 93251 # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 105963 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 26867 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data 39377 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3.data 79082 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 251289 # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data 396928 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data 18608 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu2.data 26165 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu3.data 50395 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total 492096 # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker 1198 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 1246 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 35789 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 284554 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 399 # number of demand (read+write) misses
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stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.SCUpgradeReq_accesses::cpu0.data 1 # number of SCUpgradeReq accesses(hits+misses)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
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system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.007560 # miss rate for ReadReq accesses
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system.l2c.UpgradeReq_miss_rate::cpu0.data 0.780203 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.770968 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.796147 # miss rate for UpgradeReq accesses
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stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.l2c.SCUpgradeReq_miss_rate::cpu3.data 0.250000 # miss rate for SCUpgradeReq accesses
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system.l2c.ReadExReq_miss_rate::cpu2.data 0.184965 # miss rate for ReadExReq accesses
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system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006405 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004024 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.005814 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.006128 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total 0.005924 # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.040642 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.033278 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.035623 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.040807 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.038912 # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data 0.580204 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data 0.164962 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu2.data 0.175328 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu3.data 0.181383 # miss rate for InvalidateReq accesses
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system.l2c.demand_miss_rate::cpu0.dtb.walker 0.007560 # miss rate for demand accesses
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system.l2c.demand_miss_rate::cpu2.inst 0.005814 # miss rate for demand accesses
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system.l2c.overall_miss_rate::cpu0.dtb.walker 0.007560 # miss rate for overall accesses
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system.l2c.overall_miss_rate::cpu0.inst 0.006405 # miss rate for overall accesses
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system.l2c.overall_miss_rate::cpu2.itb.walker 0.007729 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.005814 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.069418 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.dtb.walker 0.003549 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.itb.walker 0.008374 # miss rate for overall accesses
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system.l2c.overall_miss_rate::total 0.029462 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 137466.165414 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 138175.304878 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 135605.321508 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 136805.434783 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 138240.957967 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker 135691.477886 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 81476.375995 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 42129.376789 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 41412.047366 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 42612.456196 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 24857.632575 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131128.673449 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 131820.663534 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 147233.162856 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 75410.262683 # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 131892.820210 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 133749.867620 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 136053.066212 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 82975.254946 # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 133297.651394 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 134678.721081 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 141497.641688 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 79885.981877 # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 130586.978719 # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu2.data 139175.386967 # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu3.data 155662.198631 # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total 28279.203651 # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 137466.165414 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 138175.304878 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 131892.820210 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 131875.995486 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 135605.321508 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.itb.walker 136805.434783 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 133749.867620 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 132955.408458 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 138240.957967 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.itb.walker 135691.477886 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 136053.066212 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 144712.943464 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 77929.582558 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 137466.165414 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 138175.304878 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 131892.820210 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 131875.995486 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 135605.321508 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.itb.walker 136805.434783 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 133749.867620 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 132955.408458 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 138240.957967 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.itb.walker 135691.477886 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 136053.066212 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 144712.943464 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 77929.582558 # average overall miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.l2c.writebacks::writebacks 950197 # number of writebacks
system.l2c.writebacks::total 950197 # number of writebacks
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.ReadReq_mshr_hits::cpu3.dtb.walker 2 # number of ReadReq MSHR hits
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.l2c.ReadReq_mshr_hits::cpu3.itb.walker 14 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 1 # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu2.data 4 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu3.data 1 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.data 4 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.dtb.walker 2 # number of demand (read+write) MSHR hits
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.l2c.demand_mshr_hits::cpu3.itb.walker 14 # number of demand (read+write) MSHR hits
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.demand_mshr_hits::cpu3.inst 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.data 1 # number of demand (read+write) MSHR hits
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.l2c.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.overall_mshr_hits::cpu2.data 4 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.dtb.walker 2 # number of overall MSHR hits
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.l2c.overall_mshr_hits::cpu3.itb.walker 14 # number of overall MSHR hits
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.overall_mshr_hits::cpu3.inst 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.data 1 # number of overall MSHR hits
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.l2c.overall_mshr_hits::total 22 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 399 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 328 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 451 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 460 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker 1021 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.itb.walker 913 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 3572 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 4541 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data 5827 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data 9417 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 19785 # number of UpgradeReq MSHR misses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.l2c.SCUpgradeReq_mshr_misses::cpu3.data 1 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.l2c.ReadExReq_mshr_misses::cpu1.data 51110 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data 59801 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data 100893 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 211804 # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 6769 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 22662 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 28030 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total 57461 # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 26867 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data 39373 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3.data 79081 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 145321 # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data 18608 # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu2.data 26165 # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu3.data 50395 # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total 95168 # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 399 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker 328 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 6769 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 77977 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker 451 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.itb.walker 460 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst 22662 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 99174 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.dtb.walker 1021 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.itb.walker 913 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst 28030 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data 179974 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 418158 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 399 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker 328 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 6769 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 77977 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker 451 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.itb.walker 460 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 22662 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 99174 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.dtb.walker 1021 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.itb.walker 913 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst 28030 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data 179974 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 418158 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 6935 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2.data 6911 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu3.data 6765 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 20611 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 6456 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2.data 6468 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu3.data 6500 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 19424 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 13391 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2.data 13379 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu3.data 13265 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 40035 # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 50859000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 42041500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 56648000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 58330500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker 130896000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.itb.walker 115049500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 453824500 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 320918500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 412357500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 666329000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 1399605000 # number of UpgradeReq MSHR miss cycles
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data 72000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 72000 # number of SCUpgradeReq MSHR miss cycles
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 6190886500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 7284997500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 13845865500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 27321749500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 825092500 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 2804419500 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 3533391999 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total 7162903999 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 3312638000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 4909113000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 10398990500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 18620741500 # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2243882500 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu2.data 3379874000 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu3.data 7340646500 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total 12964403000 # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 50859000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 42041500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 825092500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 9503524500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 56648000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 58330500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 2804419500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 12194110500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker 130896000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.itb.walker 115049500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst 3533391999 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data 24244856000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 53559219499 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 50859000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 42041500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 825092500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 9503524500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 56648000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 58330500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 2804419500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 12194110500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker 130896000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.itb.walker 115049500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst 3533391999 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data 24244856000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 53559219499 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1277858000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1278109500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data 1223125500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 3779093000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1236963000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 1237416500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data 1206551998 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 3680931498 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2514821000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2515526000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3.data 2429677498 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 7460024498 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.007083 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.007782 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.002929 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.007729 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003542 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker 0.008248 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.003649 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.770968 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.796147 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.780846 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.461103 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.250000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.206825 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.184965 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.176179 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.107463 # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.004024 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.005814 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.006128 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.003650 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.033278 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.035619 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.040807 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.022503 # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.164962 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data 0.175328 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data 0.181383 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total 0.077752 # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.007083 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.007782 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.004024 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.073949 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.002929 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.007729 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005814 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.069415 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003542 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.008248 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.006128 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data 0.071685 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.016627 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.007083 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.007782 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.004024 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.073949 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.002929 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.007729 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005814 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.069415 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003542 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.008248 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006128 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data 0.071685 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.016627 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 127466.165414 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 128175.304878 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 125605.321508 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 126805.434783 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 128203.721841 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 126012.595838 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 127050.531915 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70671.327901 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70766.689549 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 70758.097059 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70740.712661 # average UpgradeReq mshr miss latency
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 72000 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 72000 # average SCUpgradeReq mshr miss latency
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121128.673449 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 121820.663534 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 137233.162856 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 128995.436819 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121892.820210 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123749.867620 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 126057.509775 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124656.793286 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 123297.651394 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 124682.218779 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 131497.964113 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 128135.241982 # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 120586.978719 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 129175.386967 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 145662.198631 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 136226.494200 # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127466.165414 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128175.304878 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121892.820210 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121875.995486 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 125605.321508 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 126805.434783 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123749.867620 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 122956.727570 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 128203.721841 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 126012.595838 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 126057.509775 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 134713.103004 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 128083.689656 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127466.165414 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128175.304878 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121892.820210 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121875.995486 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 125605.321508 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 126805.434783 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123749.867620 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 122956.727570 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 128203.721841 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 126012.595838 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 126057.509775 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 134713.103004 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 128083.689656 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184262.148522 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 184938.431486 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 180801.995565 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 183353.209451 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 191598.977695 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 191313.620903 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 185623.384308 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 189504.298703 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 187799.342842 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 188020.479856 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 183164.530569 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 186337.567079 # average overall mshr uncacheable latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.membus.trans_dist::ReadReq 76742 # Transaction distribution
system.membus.trans_dist::ReadResp 436146 # Transaction distribution
system.membus.trans_dist::WriteReq 33651 # Transaction distribution
system.membus.trans_dist::WriteResp 33651 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1056828 # Transaction distribution
system.membus.trans_dist::CleanEvict 193864 # Transaction distribution
system.membus.trans_dist::UpgradeReq 34231 # Transaction distribution
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.membus.trans_dist::UpgradeResp 34233 # Transaction distribution
system.membus.trans_dist::ReadExReq 881810 # Transaction distribution
system.membus.trans_dist::ReadExResp 881810 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 359404 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122584 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 61 # Packet count per connected master and slave (bytes)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6766 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3762035 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 3891446 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342687 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 342687 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4234133 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155714 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13532 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 139863648 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 140033090 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7303808 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7303808 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 147336898 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 1567 # Total snoops (count)
system.membus.snoop_fanout::samples 2745655 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.membus.snoop_fanout::1 2745655 100.00% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.membus.snoop_fanout::total 2745655 # Request fanout histogram
system.membus.reqLayer0.occupancy 68555500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.membus.reqLayer2.occupancy 1764002 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.membus.reqLayer5.occupancy 3043978655 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.membus.respLayer2.occupancy 2811928746 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.membus.respLayer3.occupancy 111188737 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Update to reflect changes to RealView platform code
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
stats: Update to reflect changes to RealView platform code
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.toL2Bus.snoop_filter.tot_requests 51453109 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 26058247 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 3008 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 2315 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 2315 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.toL2Bus.trans_dist::ReadReq 1484473 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 23684852 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 33651 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 33651 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 7933708 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 15738935 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 2275989 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 42908 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 42913 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 1970952 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 1970952 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 15741997 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 6463623 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 1272073 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 1223993 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47309096 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29178438 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 818931 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1715075 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 79021540 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2014946836 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1018609902 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2956128 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6054072 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 3042566938 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 1651979 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 38031624 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.016505 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.127406 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.toL2Bus.snoop_fanout::0 37403925 98.35% 98.35% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 627699 1.65% 100.00% # Request fanout histogram
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.toL2Bus.snoop_fanout::total 38031624 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 30654168986 # Layer occupancy (ticks)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.toL2Bus.snoopLayer0.occupancy 845171 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.toL2Bus.respLayer0.occupancy 15236717928 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.toL2Bus.respLayer1.occupancy 7805405781 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.toL2Bus.respLayer2.occupancy 292394209 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.toL2Bus.respLayer3.occupancy 700943896 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.kern.inst.arm 0 # number of arm instructions executed
system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- End Simulation Statistics ----------
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