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gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt

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Add Alpha Linux version of "hello world" test. --HG-- extra : convert_revision : 22cd31c58f18fd92bd61ee4b4a218926f7290045
2006-08-21 04:48:30 +02:00
---------- Begin Simulation Statistics ----------
Update refs for new CPU frequency changes. tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini: tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out: tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr: tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout: tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini: tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out: tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr: tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout: tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini: tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out: tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr: tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout: tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini: tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out: tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout: tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini: tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out: tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr: tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout: tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini: tests/quick/50.memtest/ref/alpha/linux/memtest/config.out: tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt: tests/quick/50.memtest/ref/alpha/linux/memtest/stdout: Update refs --HG-- extra : convert_revision : 8d9deb2b907843064b40e46207d9c9361941f022
2007-04-22 20:50:37 +02:00
sim_seconds 0.000003 # Number of seconds simulated
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
sim_ticks 3208000 # Number of ticks simulated
final_tick 3208000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
host_inst_rate 172950 # Simulator instruction rate (inst/s)
host_op_rate 172880 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 86758979 # Simulator tick rate (ticks/s)
host_mem_usage 253924 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.physmem.bytes_read::cpu.inst 25600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8788 # Number of bytes read from this memory
system.physmem.bytes_read::total 34388 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 25600 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 25600 # Number of instructions bytes read from this memory
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory
system.physmem.bytes_written::total 6696 # Number of bytes written to this memory
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.physmem.num_reads::cpu.inst 6400 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1183 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.physmem.bw_read::cpu.inst 7980049875 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2739401496 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10719451372 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7980049875 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7980049875 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 2087281796 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2087281796 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7980049875 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4826683292 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12806733167 # Total bandwidth to/from this memory (bytes/s)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.throughput 12806733167 # Throughput (bytes/s)
system.membus.data_through_bus 41084 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.dtb.read_hits 1183 # DTB read hits
Stats: Update the stats. --HG-- extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
2007-08-27 05:27:53 +02:00
system.cpu.dtb.read_misses 7 # DTB read misses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dtb.read_acv 0 # DTB read access violations
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.dtb.read_accesses 1190 # DTB read accesses
This brings M5 closer to modernity - the kernel being advertised is newer so it won't die on binaries compiled with newer glibc's, and enables use of TLS-toolchain built binaries for ALPHA_SE by putting auxiliary vectors on the stack. There are some comments in the code to help. Finally, stats changes for ALPHA are from slight perturbations to the initial stack frame, all minimal diffs.
2008-12-05 18:09:29 +01:00
system.cpu.dtb.write_hits 865 # DTB write hits
Stats: Update the stats. --HG-- extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
2007-08-27 05:27:53 +02:00
system.cpu.dtb.write_misses 3 # DTB write misses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.dtb.data_hits 2048 # DTB hits
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.dtb.data_accesses 2058 # DTB accesses
system.cpu.itb.fetch_hits 6400 # ITB hits
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
system.cpu.itb.fetch_misses 17 # ITB misses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.itb.fetch_acv 0 # ITB acv
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.itb.fetch_accesses 6417 # ITB accesses
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.numCycles 6417 # number of cpu cycles simulated
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts 6390 # Number of instructions committed
system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
system.cpu.num_int_insts 6317 # number of integer instructions
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.num_fp_insts 10 # number of float instructions
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.num_mem_refs 2058 # number of memory refs
system.cpu.num_load_insts 1190 # Number of load instructions
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
system.cpu.num_store_insts 868 # Number of store instructions
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.num_idle_cycles 0 # Number of idle cycles
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.num_busy_cycles 6417 # Number of busy cycles
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
stats: updates due to branch predictor warming
2014-02-16 18:40:34 +01:00
system.cpu.Branches 1050 # Number of branches fetched
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6400 # Class of executed instruction
Add Alpha Linux version of "hello world" test. --HG-- extra : convert_revision : 22cd31c58f18fd92bd61ee4b4a218926f7290045
2006-08-21 04:48:30 +02:00
---------- End Simulation Statistics ----------
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