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gem5/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt

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ARM: Add regression tests
2010-07-27 07:03:44 +02:00
---------- Begin Simulation Statistics ----------
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
sim_seconds 0.793670 # Number of seconds simulated
sim_ticks 793670137000 # Number of ticks simulated
final_tick 793670137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
host_inst_rate 583678 # Simulator instruction rate (inst/s)
host_op_rate 616385 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 814802699 # Simulator tick rate (ticks/s)
host_mem_usage 241980 # Number of bytes of host memory used
host_seconds 974.06 # Real time elapsed on the host
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
sim_insts 568539335 # Number of instructions simulated
sim_ops 600398272 # Number of ops (including micro ops) simulated
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.bytes_read::cpu.inst 38592 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1675072 # Number of bytes read from this memory
system.physmem.bytes_read::total 1713664 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 38592 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 38592 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 159552 # Number of bytes written to this memory
system.physmem.bytes_written::total 159552 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 603 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 26173 # Number of read requests responded to by this memory
system.physmem.num_reads::total 26776 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 2493 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2493 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 48625 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2110539 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2159164 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 48625 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 48625 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 201031 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 201031 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 201031 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 48625 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2110539 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2360195 # Total bandwidth to/from this memory (bytes/s)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.throughput 2360195 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 4941 # Transaction distribution
system.membus.trans_dist::ReadResp 4941 # Transaction distribution
system.membus.trans_dist::Writeback 2493 # Transaction distribution
system.membus.trans_dist::ReadExReq 21835 # Transaction distribution
system.membus.trans_dist::ReadExResp 21835 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side 56045 # Packet count per connected master and slave (bytes)
system.membus.pkt_count 56045 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1873216 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size 1873216 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 1873216 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 49213000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 240984000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
ARM: Update SE stats for TLB stats additions
2010-11-08 20:59:35 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 48 # Number of system calls
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.numCycles 1587340274 # number of cpu cycles simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.committedInsts 568539335 # Number of instructions committed
system.cpu.committedOps 600398272 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 533522631 # Number of integer alu accesses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.num_func_calls 1995305 # number of times a function call or return occured
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
system.cpu.num_conditional_control_insts 67050634 # number of instructions that are conditional controls
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.num_int_insts 533522631 # number of integer instructions
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.num_fp_insts 16 # number of float instructions
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.num_int_register_reads 3212467067 # number of times the integer registers were read
system.cpu.num_int_register_writes 614470972 # number of times the integer registers were written
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.num_mem_refs 219173606 # number of memory refs
system.cpu.num_load_insts 148952593 # Number of load instructions
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.num_store_insts 70221013 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.num_busy_cycles 1587340274 # Number of busy cycles
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 12 # number of replacements
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.icache.tagsinuse 577.773656 # Cycle average of tags in use
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.icache.total_refs 570073883 # Total number of references to valid blocks.
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks.
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.icache.avg_refs 886584.576983 # Average number of references to valid blocks.
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.icache.occ_blocks::cpu.inst 577.773656 # Average occupied blocks per requestor
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.icache.occ_percent::cpu.inst 0.282116 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.282116 # Average percentage of cache occupancy
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.icache.ReadReq_hits::cpu.inst 570073883 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 570073883 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 570073883 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 570073883 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 570073883 # number of overall hits
system.cpu.icache.overall_hits::total 570073883 # number of overall hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_misses::cpu.inst 643 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 643 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 643 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 643 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 643 # number of overall misses
system.cpu.icache.overall_misses::total 643 # number of overall misses
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.icache.ReadReq_miss_latency::cpu.inst 33685000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 33685000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 33685000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 33685000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 33685000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 33685000 # number of overall miss cycles
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.icache.ReadReq_accesses::cpu.inst 570074526 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 570074526 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 570074526 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 570074526 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 570074526 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 570074526 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52387.247278 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 52387.247278 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52387.247278 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 52387.247278 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52387.247278 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 52387.247278 # average overall miss latency
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 643 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 643 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 643 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 643 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 643 # number of overall MSHR misses
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32399000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 32399000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32399000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 32399000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32399000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 32399000 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50387.247278 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50387.247278 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50387.247278 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 50387.247278 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50387.247278 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 50387.247278 # average overall mshr miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.replacements 2512 # number of replacements
system.cpu.l2cache.tagsinuse 22024.775302 # Cycle average of tags in use
system.cpu.l2cache.total_refs 506990 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23599 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 21.483537 # Average number of references to valid blocks.
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.occ_blocks::writebacks 20978.651717 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 539.196236 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 506.927350 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.640218 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.016455 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.015470 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.672143 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 40 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 185478 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 185518 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 418626 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 418626 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 225913 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 225913 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 40 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 411391 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 411431 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 40 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 411391 # number of overall hits
system.cpu.l2cache.overall_hits::total 411431 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 603 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 4338 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 4941 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 21835 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 21835 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 603 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 26173 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 26776 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 603 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 26173 # number of overall misses
system.cpu.l2cache.overall_misses::total 26776 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31356000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 226076000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 257432000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1135420000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1135420000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 31356000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1361496000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1392852000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 31356000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1361496000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1392852000 # number of overall miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_accesses::cpu.inst 643 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 189816 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 190459 # number of ReadReq accesses(hits+misses)
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.Writeback_accesses::writebacks 418626 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 418626 # number of Writeback accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 247748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 643 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 437564 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 438207 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 643 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 437564 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 438207 # number of overall (read+write) accesses
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.937792 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022854 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.025943 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.088134 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.088134 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.937792 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.059815 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.061104 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.937792 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.059815 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.061104 # miss rate for overall accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52115.260489 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52101.194090 # average ReadReq miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52019.103656 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52018.673439 # average overall miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52019.103656 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52018.673439 # average overall miss latency
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.writebacks::writebacks 2493 # number of writebacks
system.cpu.l2cache.writebacks::total 2493 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 603 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4338 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 4941 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21835 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 21835 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 603 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 26173 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 26776 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 603 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 26173 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 26776 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24120000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 174020000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198140000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 873400000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 873400000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24120000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1047420000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1071540000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24120000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1047420000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1071540000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.937792 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022854 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.025943 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088134 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088134 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.937792 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059815 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.061104 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.937792 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059815 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.061104 # mshr miss rate for overall accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40115.260489 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40101.194090 # average ReadReq mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40019.103656 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40018.673439 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40019.103656 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40018.673439 # average overall mshr miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.dcache.replacements 433468 # number of replacements
system.cpu.dcache.tagsinuse 4094.241219 # Cycle average of tags in use
system.cpu.dcache.total_refs 216774472 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 495.412036 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 529622000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.241219 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999571 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999571 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 147602035 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 147602035 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 69169783 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1327 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 1327 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 216771818 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 216771818 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 216771818 # number of overall hits
system.cpu.dcache.overall_hits::total 216771818 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 189816 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 189816 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 247748 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 247748 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 437564 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses
system.cpu.dcache.overall_misses::total 437564 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2650304000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2650304000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4137794000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4137794000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 6788098000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 6788098000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 6788098000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 6788098000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 147791851 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 147791851 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1327 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1327 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 217209382 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 217209382 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 217209382 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 217209382 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001284 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.001284 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003569 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.003569 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13962.489990 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13962.489990 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16701.624231 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 16701.624231 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15513.383185 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15513.383185 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 418626 # number of writebacks
system.cpu.dcache.writebacks::total 418626 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 189816 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 189816 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247748 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 247748 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 437564 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2270672000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2270672000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3642298000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3642298000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5912970000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 5912970000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5912970000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 5912970000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003569 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11962.489990 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11962.489990 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14701.624231 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14701.624231 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.throughput 69093329 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 190459 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 190459 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 418626 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 247748 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 247748 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1286 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1293754 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count 1295040 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 41152 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 54796160 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size 54837312 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 54837312 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 847042500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 964500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 656346000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
---------- End Simulation Statistics ----------
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